CONFIGURABLE LOGIC

Eric Prebys P116B - Winter 2020 P116B - Configurable Logic Need for Configurable Logic

• As you’ve seen in lab, even very simple operations get pretty complex when using discrete components • The technology allows for much higher density, so we have two options, but the details depend on the application • We have two options • Design and fabricate Application Specific Integrated Circuits (ASICs) • The bar has been significantly lowered, but still fairly expensive and complicated, particularly if only a small number of parts are needed • Use some sort of general purpose high density component that can be configured for our needs • “Configurable logic” devices began to appear in the early 1970s • Any electrical design you do will very likely involve them P116B - Winter 2020 P116B - Configurable Logic RAM as Configurable Logic

• An Am x n-bit RAM chip can function as an arbitrary m->n truth table

[A → A ] m−1 0 [D → D ] m−1 0

Example: If I want to encode the expression

D = A ⋅ A ⋅ A 0 0 1 2

I would fill every 8th memory location (starting with READ 0) with an odd number, and the rest with even numbers.

• This is known as a “Look-up Table” (LUT) P116B - Winter 2020 P116B - Configurable Logic LUTs (cont’d)

• Advantages • Can implement literally any combinatorial truth table • Disadvantages • Slow and expensive for large tables • Configuration volatile and could take a long time to load simple things • No feedback or flip-flops • Can’t directly implement synchronous logic • Modern applications • As we’ll see soon, the basic logical operations in FPGAs are implemented using small LUTs P116B - Winter 2020 P116B - Configurable Logic Generic Logic Equations

• Consider a general truth table

A B C Q 0 0 0 0 0 0 1 1 OR these options Use ANDs to specify 0 1 0 0 together any combinations 0 1 1 1 that result in Q=1 1 0 0 1 1 0 1 0 Q = A⋅B ⋅C 1 1 0 0 1 1 1 0 +A⋅B⋅C +A⋅B ⋅C P116B - Winter 2020 P116B - Configurable Logic Programmable Array Logic (PAL*)

• Developed in 1978 by Monolithic Memories • Each input and its inverse are fed into a matrix of AND gates that are ORed together for each output • Original chips had all internal connections initially set. • Unwanted connections were burned out in the configuration process, much like ROMs • In fact, the same machines were used to burn both

*”PAL” is technically proprietary. Generic term is “PLD”. P116B - Winter 2020 P116B - Configurable Logic Advanced PAL Features

• Features that have been added to PALs include • Feedback lines from output to input • Output Flip-flops • Tri-state outputs

= P116B - Winter 2020 P116B - Configurable Logic Configurable Output Blocks

• Advanced PALs have configurable output blocks that can selectively be configured to be • Combinatorial • Latched (D flip-flop) • Tri-state P116B - Winter 2020 P116B - Configurable Logic Configuring PALs

• Original PALs could only be “burned” once. If you needed to change something, you needed to throw them out and program new ones • A later variant allowed PALs to be erased with UV light, and then reprogrammed • Later Generic Array Logic (GAL) chips offered increased functionality, and also the ability to be electrically erased and reprogrammed. P116B - Winter 2020 P116B - Configurable Logic PAL Configuration

• In most cases, it’s complicated to determine the gate level configuration of the PAL, so several Hardware Description Languages (HDLs) were developed for the purpose • PALASM – written in FORTRAN by John Birkner (1980) • Compiler for Universal Programmable Logic (CUPL) - Assisted Technology (1983) • Advanced Boolean Expressian Language (ABEL) – Data I/O (1983) • Compilers would produce a “JEDEC” “fuse map” to configure PAL • The functionality of these languages has been absorbed into modern HDLs, such as VHDL or Verilog • Although Xilinx still supports ABEL for internal “components” P116B - Winter 2020 P116B - Configurable Logic ABEL Programming Language

• Combinatorial Example: Full adder P116B - Winter 2020 P116B - Configurable Logic Easy Way

• ABEL has advanced features allowing • Math • Truth Tables • State Machines • Text vectors • etc P116B - Winter 2020 P116B - Configurable Logic PAL Programmers

• Example: Data I/O P116B - Winter 2020 P116B - Configurable Logic Field Programmable Gate Arrays (FPGAs)

• Field programmable gate arrays expanded on the capabilities of PALs by replacing the logic array with an array of “configurable logic blocks” (COBs), connected via on-chip routing highways. • Additional features • Low-slew internal clock lines • Versatile I/O blocks • Onboard timers • Onboard RAM P116B - Winter 2020 P116B - Configurable Logic Major FPGA Manufacturers

• Altera (1983) – the first commercial FPGAs (1983). Altera FPGAs were “burned”, but could be erased with UV light • Xilinx (1985) – compared to Altera, Xilinx had more functionality, but was not as fast. Needed to be dynamically configured at power up. Still the industry leader (36% compared to 31% for Altera) • Actel (late 80s) – biggest competitor to Xilinx and Altera, but still only 10% of the market • We will focus on Xilinx chips in this course P116B - Winter 2020 P116B - Configurable Logic Structure of an FPGA Device

CLB = “Configurable Logic Block” P116B - Winter 2020 P116B - Configurable Logic Configurable Logic Blocks (CLBs)

• The basic building block of FPGAs are look up tables (LUTs) feeding data latches

• Of course things have gotten a bit more complex… P116B - Winter 2020 P116B - Configurable Logic Xilinx Series 7 CLBs -> “Slice” P116B - Winter 2020 P116B - Configurable Logic Connections to Internal Busses

R Spartan-II FPGA Family: Functional Description

3-State Lines

CLB CLB CLB CLB

DS001_07_090600 Figure 7: BUFT Connections to Dedicated Horizontal Bus Lines

Clock Distribution networks. The DLL monitors the input clock and the distributed clock, and automatically adjusts a clock delay The Spartan-II family provides high-speed, low-skew clock element. Additional delay is introduced such that clock distribution through the primary global routing resources edges reach internal flip-flops exactly one clock period after described above. A typical clock distribution net is shown in they arrive at the input. This closed-loop system effectively Figure 8. eliminates clock-distribution delay by ensuring that clock Four global buffers are provided, two at the top center of the edges arrive at internal flip-flops in synchronism with clock device and two at the bottom center. These drive the four edges arriving at the input. primary global nets that in turn drive any clock pin. In addition to eliminating clock-distribution delay, the DLL Four dedicated clock pads are provided, one adjacent to provides advanced control of multiple clock domains. The each of the global buffers. The input to the global buffer is DLL provides four quadrature phases of the source clock, selected either from these pads or from signals in the can double the clock, or divide the clock by 1.5, 2, 2.5, 3, 4, general purpose routing. Global clock pins do not have the 5, 8, or 16. It has six outputs. option for internal, weak pull-up resistors. The DLL also operates as a clock mirror. By driving the output from a DLL off-chip and then back on again, the DLL Global GCLKPAD3 GCLKPAD2 can be used to deskew a board level clock among multiple Clock Rows GCLKBUF3 GCLKBUF2 Global Clock Column Spartan-II devices. In order to guarantee that the system clock is operating correctly prior to the FPGA starting up after configuration, the DLL can delay the completion of the configuration process until after it has achieved lock.

Global Clock Boundary Scan Spine Spartan-II devices support all the mandatory boundary- scan instructions specified in the IEEE standard 1149.1. A Test Access Port (TAP) and registers are provided that implement the EXTEST, SAMPLE/PRELOAD, and BYPASS instructions. The TAP also supports two USERCODE GCLKBUF1 GCLKBUF0 instructions and internal scan chains. GCLKPAD1 GCLKPAD0 The TAP uses dedicated package pins that always operate DS001_08_060100 using LVTTL. For TDO to operate using LVTTL, the V Figure 8: Global Clock Distribution Network CCO for Bank 2 must be 3.3V. Otherwise, TDO switches rail-to-rail between ground and VCCO. TDI, TMS, and TCK Delay-Locked Loop (DLL) have a default internal weak pull-up resistor, and TDO has Associated with each global clock input buffer is a fully no default resistor. Bitstream options allow setting any of digital Delay-Locked Loop (DLL) that can eliminate skew the four TAP pins to have an internal pull-up, pull-down, or between the clock input pad and internal clock-input pins neither. throughout the device. Each DLL can drive two global clock

DS001-2 (v2.8) June 13, 2008 www.xilinx.com Module 2 of 4 Product Specification 13 P116B - Winter 2020 P116B - Configurable Logic IO Blocks (IOBs)

• Highly configurable IO Blocks allow input/output/tri-state connection, with adjustable slew rate and logic levels P116B - Winter 2020 P116B - Configurable Logic Configuring FPGAs

• FPGAs can be configured in several ways • Schematic capture • Hardware description languages (HDLs) • Parametric GUI design tools (e.g. “wizards”) • In general, modules are compatible at the “pin” (interface) level, so multiple techniques can be used in a single design. • For example, it’s common to use schematic capture to specify the top level design and HDLs or wizards to design the lower level modules. P116B - Winter 2020 P116B - Configurable Logic Schematic Capture Associate the inputs and Draw schematic using a library of “parts” outputs with pins on the FPGA

• This is then “compiled” to generate a configuration file for the chip. • However, this is not the way we’re going to do it! P116B - Winter 2020 P116B - Configurable Logic HDLs for FPGAs

• ABEL is not nearly complex enough to deal with the advanced functionality of modern FPGAs • Although Xilinx still supports ABEL representations of sub- components within FPGAs • Two major HDLs are used • Verilog – first developed in 1985 • VHDL - Very High Speed Integrated Circuit (VHSIC) HDL – began in 1983 • We’ll be using Verilog • Stay tuned… P116B - Winter 2020 P116B - Configurable Logic Design Element Libraries

• In addition to standard logic, register, and memory elements, some of the “canned” design elements include • Parametric digital filters and transforms • Mathematical processors • Full processors • That can, e.g., run C or Python programs • Example: Xilinx “MicroBlaze” processor • Standard interface protocols • RS-232 • Ethernet • PCI • etc • Also tools to configure chip at the CLB level for maximum performance P116B - Winter 2020 P116B - Configurable Logic Loading Configuration

• Some FPGAs are “burned” or otherwise configured in a non-volatile way, like PLDs • Less common today • Others must have their configuration dynamically loaded when the power up • Can self load from a companion PROM • Can be loaded from host processor • Both: load default configuration from PROM, which can then be overridden by host processor R Spartan-II FPGA Family: Functional Description R Spartan-II FPGA Family: Functional Description Slave Serial Mode Multiple FPGAs in Slave Serial mode can be daisy-chained for configuration from a single source. The maximum In Slave Serial mode, the FPGA’s CCLK pin is driven by an Configuration amount of data that can be sent to the DOUT pin for a serial external source, allowing FPGAs to be configured from Table 8: Spartan-II Configuration File Sizedaisy chain is 220-1 (1,048,575) 32-bit words, or 33,554,400 Configuration is the process by which the bitstreamother logic of a devices such as microprocessors or in a P116B - Winter 2020 P116Bbits, which - Configurable is approximately Logic 25 XC2S200 bitstreams. The design, as generated by the Xilinx software, isdaisy-chain loaded into configuration. DeviceFigure 15 shows connections Configuration for File Size (Bits) configuration bitstream of downstream devices is limited to the internal configuration memory of the FPGA.a Master Spartan-II Serial FPGA configuring a Slave Serial FPGA XC2S15 197,696this size. devices support both serial configuration, usingfrom the a PROM. A Spartan-II device in slave serial mode master/slave serial and JTAG modes, as well asshould byte-wide be connected as shownXC2S30 for the third device from the336,768 After an FPGA is configured, data for the next device is configuration employing the Slave Parallel mode.left. Slave Serial mode is selected by a <11x> on the mode routed to the DOUT pin. Data on the DOUT pin changes on Loading Configurationpins (M0, M1, M2). XC2S50 Files559,200the rising edge of CCLK. Configuration must be delayed until INIT pins of all daisy-chained FPGAs are High. For Configuration File Figure 16 shows the timingXC2S100 for Slave Serial configuration. 781,216 more information, see "Start-up," page 19. The serial bitstream must be setup at the DIN input pin a Spartan-II devices are configured by sequentially loading XC2S150 1,040,096 short time before each rising edge of an externally frames of data that have been concatenated into a generated CCLK. XC2S200 1,335,840 configuration• file.FPGAs Table 8 shows howcan much nonvolatilebe daisy -chained and loaded from a single PROM storage space is needed for Spartan-II devices. Modes 3.3V 2.5V 3.3V 3.3V 3.3V 2.5V It is important to note that, while a PROM is commonly used to store configuration data before loading them into the Spartan-II devices support the following four configuration modes: 3.3 K FPGA, it is by no means required. Any of a number of M0 M1 VCCO M0 M1 VCCO M2 M2 different kinds of under populated nonvolatile storage •Slave SerialVCCI modeNT VCCINT already available either on or off the board (i.e., hard drives, DOUT DIN DOUT These pins determine •Master Serial mode FLASH cards, etc.) can be used. For more information on CCLK configuration mode •SlaveSpartan-II Parallel mode configuration without a PROM, refer to XAPP098, The Spartan-II Low-Cost, Efficient Serial Configuration of Spartan FPGAs. •Boundary-scan(Master Serial) mode Vcc (Slave) The ConfigurationCCLK mode pins (M2, M1, CLKM0) select among these configurationDIN modes with the optionDATA in PROMeach case of having the IOB pins either pulled up or left floating prior to PROGRAM CE CEO PROGRAM theDO endNE of configuration.INIT The selection codesRESET/OE are listed in DONE INIT Table 9. GND GND GND Configuration through the boundary-scan port is always available, independent of the mode selection. Selecting the boundary-scan mode simply turns off the other modes. The PROGRAM three mode pins have internal pull-up resistors, and default to a logic High if left unconnected. DS001_15_060608 Table 9: Configuration Modes Notes: Preconfiguration1. If the DriveDone configurationCCLK option is not active for any of the FPGAs, pull up DONE with a 330Ω resistor. Configuration Mode Pull-ups M0 M1 M2 Direction Data Width Serial D Figure 15: Master/Slave Serial ConfigurationOUT Circuit Diagram Master Serial mode No 000 Out 1 Ye s Ye s 0 0 1 In “slave” mode, the FPGA can Slave Parallel mode Ye s 010 In 8 No be programmed from an No 0 1 1 Boundary-Scan mode Ye s 100 N/A 1 No upstream FPGA or a host No 1 0 1 processor Slave Serial mode Ye s 110 In 1 Ye s No 1 1 1 Notes: 1. During power-on and throughout configuration, the I/O drivers will be in a high-impedance state. After configuration, all unused I/Os (those not assigned signals) will remain in a high-impedance state. Pins used as outputs may pulse High at the end of configuration (see Answer 10504). 2. If the Mode pins are set for preconfiguration pull-ups, those resistors go into effect once the rising edge of INIT samples the Mode pins. They will stay in effect until GTS is released during startup, after which the UnusedPin bitstream generator option will determine whether the unused I/Os have a pull-up, pull-down,DS001-2 or no(v2.8) resistor. June 13, 2008 www.xilinx.com Module 2 of 4 Product Specification 21

DS001-2 (v2.8) June 13, 2008 www.xilinx.com Module 2 of 4 Product Specification 17 P116B - Winter 2020 P116B - Configurable Logic P116B: The Alchitry-Au Board

• For this class, we’ll be using the Alchitry-Au development board, which includes • A Xilinx Artix-7 FPGA • 8 LEDs • An interface to other boards • USB-C host interface • Onboard configuration PROM (remember configuration at power up) P116B - Winter 2020 P116B - Configurable Logic

= used by Alchitry-Au P116B - Winter 2020 P116B - Configurable Logic Alchitry-Io Board

• The Alchitry Io board connects to the Alchitry Au board, and contains • 24 DIP switches • 24 LEDs • 5 push buttons • 4 7-segment displays P116B - Winter 2020 P116B - Configurable Logic UCD Breakout Board*

• Adds external connectivity • Digital and analog I/O • Dual channel 12-bit DAC

*Design by Seth Hillbrand, Physics Department P116B - Winter 2020 P116B - Configurable Logic Using Xilinx IDE (Vivado) Directly

• Powerful but complex! Steep learning curve.

Yikes!

• Overkill for us (and most users) P116B - Winter 2020 P116B - Configurable Logic Alchitry Lab

• Alchitry provides a greatly simplified IDE that hides the complexity of Vivado in the background and will help us get down to actually working with circuits much more quickly.

HDL Code Alchitry Labs Xilinx Vivado IDE IDE GUI Xilinx Constraint File

Xilinx Configuration (.bit) file

PC

Alchitry-Au Development Custom Alchitry-Io Board Breakout Interface Board: Board: DIP Connectors, switches, LEDs, DACs segment drivers P116B - Winter 2020 P116B - Configurable Logic Alchitry Lab IDE Download configuration to FPGA Build Download configuration to FPGA and PROM (load at power up)

HDL Source