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Logic Synthesis

⇒ Use of has become common industrial practice. The advantages are many:

→ Technology portability

→ Design Documentation

Logic Synthesis with VHDL → Constraint Driven Synthesis ⇒ Two major languages are and VHDL. This tutorial will con- ver logic synthesis via VHDL.

⇒ We will split the tutorials into three parts:

→ Introduction to VHDL via combinational synthesis examples

→ Sequential synthesis examples (registers, finite state machines)

Bob Reese → System examples (combined datapath and control) Electrical Engineering Department Mississippi State University

Bob Reese 5/95 CombSyn–2 Combinational Synthesis with VHDL Electrical & Mississippi State University Electrical & Computer Engineering Mississippi State University

Tutorial Caveats VHDL Synthesis Subset

⇒ The VHDL language has a reputation for being very complex - that ⇒ Tutorial examples have been made as simple and portable as pos- reputation is well deserved! sible. ⇒ Fortunately, the subset of VHDL which can be used for synthesis is → Will stay away from topics such as parameterization which SMALL - very easy to learn. may involve vendor–dependent features. ⇒ Primary VHDL constructs we will use for synthesis: → Will also stay away from coding styles which involve type → signal assignment conversion as this tends to add extra complications. nextstate <= HIGHWAY_GREEN ⇒ Examples have been tested with the and iewlogicV syn- → comparisons thesis tools; most of the synthesized schematics shown in the = (equal), /= (not equal), slides are from the Viewlogic synthesis tool. Some of the more > (greater than), < (less than) complex examples are only compatible with the Synopsys envi- <= ( less than or equal), >= (greater than or equal) ronment → logical operators ⇒ In these tutorials, the suggested styles for writing synthesizable (and, xor, or, nand, nor, xnor, not ) VHDL models come from my own experience in teaching an → ’if’ statement ASIC design course for Senior/Graduate EE students. if ( presentstate = CHECK_CAR ) then .... ⇒ Coverage of VHDL packages will be light; the block structural end if | elsif .... statements and VHDL configurations are skipped. Generics are → ’for’ statement (used for looping in creating arrays of not mentioned until late in the tutorial since support from a synthe- elements) sis point of view is vendor dependent. → Other constructs are when’ else’, ’case’ , ’wait ’. Also ”:=” for ⇒ This tutorial is no substitute for a good, detailed VHDL textbook or variable assignment. the language reference manual. Get one or both!!!

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General Comments on VHDL Syntax Combinational Logic Examples

⇒ Most syntax details will be introduced on an ’as–needed’ basis. ⇒ We will go through some combinational examples to introduce you to the synthesizable subset of VHDL. Usually, we will demon- → The full syntax of a statement type including all of its various strate multiple methods of implementing the same design. options will often NOT be presented; instead, these will be introduced via examples as the tutorial progresses. ⇒ Examples are:

→ There are many language details which will be glossed over or → 2 to 1 Mux simply skipped for the sake of brevity. → 8-level priority circuit ⇒ Generalities: → 3 to 8 Decoder → VHDL is not case sensitive. → Synthesis boundary conditions → The semicolon is used to indicate termination of a statement. → Ripple–carry → Two dashes (’––’) are used to indicate the start of a comment.

→ Identifiers must begin with a letter, subsequent characters must be alphanumeric or ’_’ (underscore).

→ VHDL is a strongly typed language. There is very little automatic type conversion; most operations have to operate on common types. Operator overloading is supported in which a function or procedure can be defined differently for different argument lists.

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Model Template 2–to–1 MUX –– Using when else entity model_name is port library IEEE; ( use IEEE.std_logic_1164.all; list of inputs and outputs –– model for 2 to 1 mux, 8– wide ); entity mux2to1 is end model_name; port ( signal s: in std_logic; architecture architecture_name of model_name is signal zero,one: in std_logic_vector(7 downto 0); begin signal y: out std_logic_vector(7 downto 0) ... ); VHDL concurrent statements end mux2to1; .... architecture behavior of mux2to1 is end architecture_name ; begin mux2to1 y <= one when (s = ’1’) else zero; 8 end behavior; zero 8 8 y one s

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Standard Logic 1164 2/1 MUX Entity Declaration library IEEE; entity mux2to1 is use IEEE.std_logic_1164.all; port ( ⇒ The LIBRARY statement is used to reference a group of previous- signal s: in std_logic; signal zero,one: in std_logic_vector(7 downto 0); ly defined VHDL design units (other entities or groups proce- signal y: out std_logic_vector(7 downto 0) dures/functions known as ’packages’. ); end mux2to1; ⇒ The USE statement specifies what entities or packages to use out ⇒ The entity declaration defines the external interface for the model. of this library; in this case ’USE IEEE.std_logic_1164.all’ imports all procedures/functions in the std_logic_1164 package. ⇒ The port list defines the external signals. The signal definition con- sists of the signal name, mode, and type. ⇒ The std_logic_1164 package defines a multi–valued logic system which will be used as the data types for the signals defined in our → For synthesis purposes (and for this tutorial), the mode can be examples. either in, out or inout. ⇒ → The VHDL language definition had a built–in type which In this tutorial, the signal types will be either std_logic (single bit) or only supported two values, ’1’ and ’0’ which was insufficient std_logic_vector (busses). for modeling and synthesis applications. ⇒ The array specification on the std_logic_vector type defines the width of signal: → The 1164 standard defines a 9–valued logic system; only 4 of std_logic_vector (7 downto 0) (descending range) these have meaning for synthesis: tor std_logic_vector (0 to 7) (ascending range) ’1’, ’0’, ’Z’ ( high impedance), ’–’ (don’t care). Both of these are 8–bit wide signals. The descending/ascending ⇒ The 1164 single bit type std_logic and vector type std_logic_vec- range declaration will affect assignment statements such as: (for busses) will be used for all signal types in the tutorial exam- y <= ”11110000”; ples. For descending rage, y(7) is ’1’; for ascending range y(0) is ’1’.

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2/1 MUX Architecture Declaration architecture behavior of mux2to1 is begin

y <= one when (s = ’1’) else zero; end behavior; ⇒ The architecture block specifies the model functionality.

→ The architecture name is user–defined. Multiple architectures can be defined for the same entity. VHDL Y7 Y1 Y2 Y3 Y4 Y6 Y5 Y0 configurations can be used to specify which architecture to Y Y Y use for a particular entity. Y Y Y Y Y MX2 MX2 MX2 MX2 MX2 MX2 MX2 MX2 S S S S S S S S A B A B A B A B A B A B A B A B → This tutorial will only use one architecture per entity and itwill

always be called behavior . S ONE2 ONE6 ONE5 ONE0 ONE7 ONE1 ONE3 ONE4 ZERO5 ZERO0 ZERO7 ZERO1 ZERO2 ZERO3 ZERO4 ZERO6 ⇒ The ’when ... else’ statement is a conditional signal assignment statement. ’When ... else’ statements can be chained such as: signal_name <= value1 when condition1 else value2 when condition2 else, ...... value N when conditionN else default_value;

⇒ The ’when ... else’ statement is a particular type of statement known as a concurrent statement as opposed to a sequential statement. The differences between concurrent and sequential statements will be discussed in more detail later.

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2/1 MUX Architecture Using Booleans 2/1 MUX Architecture Using a Process architecture behavior of mux2to1 is architecture behavior of mux2to1_8 is signal temp: std_logic_vector(7 downto 0); begin begin comb: process (s, zero, one) temp <= (s, s, s, s, others => s); begin y <= (temp and one) or (not temp and zero); y <= zero; if (s = ’1’) then end behavior; y <= one; ⇒ Boolean operators are used in an assignment statement to gener- end if; zero end process comb; ate the mux operation. end behavior;

⇒ The s signal cannot be used in a boolean operation with the one or ⇒ This architecture uses aprocess block to describe the mux opera- zero signals because of type mismatch s( is a std_logic type,one/ tion. are std_logic_vector types) → The process block itself is considered a single concurrent → An internal signal of type std_logic_vector called temp is statement. declared. Note that there is no mode declaration for internal → Only sequential VHDL statements are allowed within a signals. The temp signal will be used in the boolean process block. operation against the zero/one signals. → Signal assignments are assumed to occur sequentially so that ⇒ Every bit of temp is to be set equal to thes signal value. An array an assignment can supercede a previous assignment to the assignment will be used; this can take several forms: same signal. temp <= (others => s); ’others’ keyword gives default value → ’if ... else’, ’case’, ’for ... loop’ are sequential statements. temp <= (s, s, s, s, s, s, s, s) ; positional assignment, 7 downto 0 temp <= (4=>s, 7=>s, 2=>s, 5=>s, 3=>s, 1=>s, 6=>s, 0=>s) ; ⇒ The list of signals after the process block is called thesensitivity named assignment list; an event on any of these signals will cause the process block or combinations of the above. to be evaluated during model simulation.

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8–level Priority Encoder VEC2 VEC0 VEC1 1 2 3 4

–– vhdl model for 8 level priority circuit Y F F –– IO Interface Declaration Y AO2 SHEET 1 OF 1 AO1A entity priority is Y C E E

port ( OR4

priority A B A B A B

signal y1, y2, y3, y4, y5, y6, y7: in std_logic; C D C D signal vec: out std_logic_vector(2 downto 0) D D ); y1 priority 6 Jan 94 13:36 end priority; y2 y3 3 Y –– Architecture body y4 C C architecture behavior of priority is y5 vec AO1A Y Y begin y6 WIR:priority SCH:priority C B B process (y1,y2,y3,y4,y5,y6,y7) y7 NOR2 NAND2B A B begin A B A B

if (y7 = ’1’) then vec <= ”111”; A A elsif (y6 = ’1’) then vec <= ”110”; Y7 Y

elsif (y5 = ’1’) then vec <= ”101”; 1 2 3 4 elsif (y4 = ’1’) then vec <= ”100”; elsif (y3 = ’1’) then vec <= ”011”; AO1A elsif (y2 = ’1’) then vec <= ”010”; C

elsif (y1 = ’1’) then vec <= ”001”; A B else vec <= B”000”; end if;

end process; Uses ’elsif’ construct for logic end behavior; Y2 Y1 Y3 Y6 Y4 Y5

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Priority Encoder again..... 3 to 8 Decoder Example

⇒ In a process, the ordering of sequential statements which affect a entity dec3to8 is port ( common output define the priority of those assignments. signal sel: in std_logic_vector(2 downto 0); –– selector signal en: in std_logic; –– enable → By using normal ’if’ statements and reversing the order of the signal y: out std_logic_vector(7 downto 0) –– outputs are low true assignments we achieve the same results as with the ); end dec3to8; chained ’elsif’ statements. architecture behavior of dec3to8 is –– Architecture body begin architecture behavior of priority is process (sel,en) begin begin ’case’ statement used for process (y1,y2,y3,y4,y5,y6,y7) y <= ”11111111”; implementation begin if (en = ’1’) then vec <= ”000”; case sel is if (y1 = ’1’) then vec <= ”001”; end if; when ”000” => y(0) <= ’0’; if (y2 = ’1’) then vec <= ”010”; end if; when ”001” => y(1) <= ’0’; if (y3 = ’1’) then vec <= ”011”; end if; when ”010” => y(2) <= ’0’; if (y4 = ’1’) then vec <= ”100”; end if; when ”011” => y(3) <= ’0’; if (y5 = ’1’) then vec <= ”101”; end if; when ”100” => y(4) <= ’0’; if (y6 = ’1’) then vec <= ”110”; end if; when ”101” => y(5) <= ’0’; if (y7 = ’1’) then vec <= ”111”; end if; when ”110” => y(6) <= ’0’; end process; when ”111” => y(7) <= ’0’; end behavior; Since ’y7’ is tested last it will have highest end case; priority. end if; end process; end behavior;

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3 A 3 A Common Error Y B NAND3B Y5 SEL2 C ⇒ When using processes, a common error is to forget to assign an A Y output a default value. ALL outputs should have DEFAULT val- B NAND3B Y3 C ues!!!! A EN Y A B OR2A Y → If there is a logical path in the model such that an output isnot NAND3B Y4 SEL0 B A C assigned any value then the synthesizer will assume that the 4 Y 4 B OR2B A output must retain its current value and a latch will be B Y SEL1 OR3B Y6 generated. C ⇒ Example: In dec3to8.vhd do not assign ’y’ the default value of BA Y OR3 Y1 B”11111111”. If en is 0, then ’y’ will not be assigned a value! C process (sel,en) A Comment out the default Y begin assignment to ’y’. 5 NAND3B 5 Y2 CB ––––– y <= ”11111111”; if (en = ’1’) then BA Y Y7 ...... OR3 Y0 C A ⇒ In the new synthesized logic, all ’y’ outputs are latched! B Y OR3B C 6 dec3to8 6 WIR:dec3to8

SCH:dec3to8 6 Jan 94 13:48 SHEET 1 OF 1

A B C D

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Alternative 3–to–8 Decoder

–– vhdl model for the 3 to 8 decoder –– uses conditional signal assignments –– which are concurrent statements

entity dec3to8_alt is

Y6 Y5 Y4 Y7 Y0 Y1 Y2 Y3 port ( signal sel: in std_logic_vector(2 downto 0); –– selector signal en: in std_logic; –– enable Q Q Q Q Q Q Q Q signal y: out std_logic_vector(7 downto 0) –– outputs are low true DL1 DL1 DL1 DL1 DL1 DL1 DL1 DL1

D G D G D G D G D G D G D G D G ); end dec3to8_alt; Conditional signal

Y Y assignment used Y Y Y Y Y Y architecture behavior of dec3to8_alt is for each output bit. NOR3 NOR3 AND3A AND3A AND3B AND3B AND3B AND3B begin C A B C A B C A B C A B C A B C A B A B C A B C y(0) <= ’0’ when (en = ’1’ and sel = ”000”) else ’1’;

y(1) <= ’0’ when (en = ’1’ and sel = ”001”) else ’1’;

Y Y y(2) <= ’0’ when (en = ’1’ and sel = ”010”) else ’1’; OR2B OR2A y(3) <= ’0’ when (en = ’1’ and sel = ”011”) else ’1’; A B B A y(4) <= ’0’ when (en = ’1’ and sel = ”100”) else ’1’;

y(5) <= ’0’ when (en = ’1’ and sel = ”101”) else ’1’; EN SEL0 SEL1 GND SEL2 y(6) <= ’0’ when (en = ’1’ and sel = ”110”) else ’1’;

y(7) <= ’0’ when (en = ’1’ and sel = ”111”) else ’1’;

end behavior;

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Generic Decoder Generic Decoder (cont.)

⇒ Shown below is an architecture block for a generic decoder: .... for i in y’range loop architecture behavior of generic_decoder is if ( en = ’1’ and bvtoi(To_Bitvector(sel)) = i ) then begin y(i) <= ’0’ ; process (sel, en) end if ; begin ⇒ y <= (others => ’1’) ; In order to compare loop variablei with the value ofsel , a type con- for i in y’range loop version must be done on sel to convert from std_logic_vector to if ( en = ’1’ and bvtoi(To_Bitvector(sel)) = i ) then integer. y(i) <= ’0’ ; end if ; → The Standard Logic 1164 package defines a conversion from end loop; std_logic_vector to bit_vector (bit_vector is a primitive VHDL end process; type). end behavior; ⇒ This architecture block can be used for any ( 2 4,to ⇒ Unfortunately, the VHDL language standard does not define type 3 to 8, 4 to 16, etc). conversions between bit_vector and integer; these conversion functions are vendor dependent. ⇒ The ’for ... loop’ construct is used to repeat a sequence of state- ments. → ’bvtoi’ is the Synopsys bit_vector to integer conversion function; ’vlb2int’ is the Viewlogic equivalent; the Cypress → The y’range is the range of values for loop variable ’i’. The WARP equivalent is ’bv2i’. ’range attribute of the signal ’y’ is defined as the array range of the signal. In this case, ’i’ will vary from 7 to 0 if the array range of ’y’ was defined as ”7 downto 0”.

→ Other attributes useful for synthesis are: ’LEFT, ’RIGHT (left, right array indices); ’HIGH, ’LOW (max, min array indices); ’EVENT (boolean which is true if event occurred on signal).

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Synthesis Boundary Conditions 1 2 3 4 F F

What happens when: SHEET 1 OF 1 E Two outputs are reduced to the same logic equation?E W

An output is is reduced to ’0’, ’1’ or to a primary input? Z_LOW X Y Z_HIGH 6 Jan 94 13:55 boundtest D D –– synthesis ’boundary’ conditions.. entity boundtest is Y Y C C port ( WIR:boundtest SCH:boundtest signal a,b,c: in std_logic; Y Y Y INVA INVA INVA NAND2B NAND2B A B A B

signal w, x, y, z_low, z_high: out std_logic A A A B ); end boundtest; B

architecture behavior of boundtest is Y Y Y INVA INVA INVA

begin A A A A A –– x and y reduce to the same logic equation 1 2 3 4 A C B –– the w output should be just a wire from c... VDD GND –– the z_low output will be ’0’, the z_high will be ’1’ x <= a or b; y <= a or ( (b and not c) or (b and c)); w <= (c and b) or (c and not b); z_low <= b and not b; z_high <= b or not b;

end behavior;

Bob Reese 5/95 CombSyn–25 Combinational Synthesis with VHDL Bob Reese 5/95 CombSyn–26 Combinational Synthesis with VHDL Electrical & Computer Engineering Mississippi State University Electrical & Computer Engineering Mississippi State University 1 2 Ripple Carry Adder SUM1 SUM2 SUM0 COUT SUM3 Y AO1 SHEET 1 OF 1 F F C Y Y Y Y XOR XOR XOR XOR A B A B A B A B A B

Library IEEE; 6 Jan 94 14:07 adder4_alt E use IEEE.std_logic_1164.all; E OA1 Y WIR:adder4_alt SCH:adder4_alt Y Y Y Y XOR XOR XOR XOR

entity adder4 is port ( A B A B A B A B A B C signal a,b: in std_logic_vector (3 downto 0); D D signal cin: in std_logic; Y Explicit CarryIn AO1 signal sum: out std_logic_vector(3 downto 0); and CarryOut C A B signal cout: out std_logic C C ); OA1 end adder4; Y A B C B architecture behavior of adder4 is B signal c: std_logic_vector(4 downto 0); Y AO1 begin C A B A A process (a,b,cin,c) Temporary signal B3

begin 1 2

to hold internal OA1 Y c(0) <= cin; carries. A B for i in 0 to 3 loop C sum(i) <= a(i) xor b(i) xor c(i); Y

c(i+1) <= (a(i) and b(i)) or AO1 C

(c(i) and (a(i) or b(i))); A B end loop;

cout <= c(4); OA1 Use Looping construct to Y end process; create logic for ripple carry A B C end behavior; adder. A1 B1 A2 B2 B0 A0 A3 CIN

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Ripple Carry Adder Comments Summary

⇒ Logic synthesis offers the following advantages: ⇒ The Standard Logic 1164 package does not define arithmetic op- erators for the std_logic type. → Faster design time, easier to modify

⇒ Most vendors supply some sort of arithmetic package for 1164 → The synthesis code documents the design in a more readable data types. manner than schematics.

→ Some vendors also support synthesis using the ’+’ operation → Different optimization choices (area or speed) between two std_logic signal types (Synopsis). Others ⇒ Several combinational VHDL examples were examined. provide an explicit function call (Viewlogic). → Both concurrent and sequential statements can be used to → For code portability, it is best to avoid use of vendor–specific specify combination logic – which you use is up to individual arithmetic functions. preference.

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Sequential Circuits

⇒ Logic which contains both combinational logic and storage ele- ments form sequential circuits. All sequential circuits can be di- vided into a combinational block and a storage element block.

Inputs Outputs Logic Synthesis with VHDL Combinational Logic Sequential Circuits PresentState State NextState Flip–Flops CLK

Single Phase Sequential System

⇒ The above diagram shows a single-phase sequential system. In a single-phase system the storage elements are edge–triggered Bob Reese devices (flip-flops). Electrical Engineering Department → Moore–type outputs are a combinatorial function of PresentState signals. Mississippi State University → Moore–type outputs are a combinatorial function of both PresentState and external input signals.

⇒ Multiple-phase design is also supported since latches can be syn- thesized as the storage elements.

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Sequential Template 8–bit Loadable Register with Asynchronous clear library declarations entity model_name is library ieee; port use ieee.std_logic_1164.all; ( entity reg8bit is port ( list of inputs and outputs signal clk, reset, load: in std_logic; ); signal din: in std_logic_vector(7 downto 0); end model_name; signal dout: out std_(7 downto 0) ); end reg8bit; architecture behavior of model_name is internal signal declarations architecture behavior of reg8bit is begin signal n_state,p_state : std_logic_vector(7 downto 0); begin –– the state process defines the storage elements state: process ( sensitivity list –– clock, reset, next_state inputs) dout <= p_state; begin comb: process(p_state,load,din) vhdl statements for state elements begin end process state; n_state <=p_state; if (load=’1’) then n_state <= din; end if; –– the comb process defines the combinational logic end process comb; comb: process ( sensitivity list –– usually includes all inputs) state: process(clk, reset) begin begin vhdl statements which specify combinational logic if (reset = ’0’) then p_state <= (others => ’0’); end process comb; elsif (clk’event and clk = ’1’) then end behavior; p_state <= n_state; end if; end process state;

end behavior;

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reg8bit State Process DQ DOUT5 3 A 3 DIN5 B DFC1B AO1C Y A C CLK Y CLR B OR2A A B DQ DIN4 Y C AO1C state: process(clk, reset) DFC1B CLK begin CLR if (reset = ’0’) then p_state <= (others => ’0’); DOUT4 DQ A DOUT7 Y B OR2A elsif (clk’event and clk = ’1’) then A DFC1B CLK DIN7 B Y CLR p_state <= n_state; C AO1C end if; 4 4 DQ A Y end process state; B OR2A A DFC1B B CLK DIN6 Y CLR C AO1C DOUT6 DQ A ⇒ The state process defines a storage element which is 8–bits wide, Y B OR2A A DFC1B B CLK DIN1 Y CLR rising edge triggered, and had a low true asynchronous reset. C AO1C

→ DQ The output of this process is the p_state signal. A Y B OR2A A DFC1B 5 CLK DOUT15 DIN0 B Y CLR → Note that the reset input has precedence over the clock in C AO1C A Y B OR2A A DQ order to define the asynchronous operation. DOUT2 DIN2 B AO1C Y C DFC1B CLK A CLK Y CLR → The ’event attribute is used to detect a change in the clock B OR2A

A Y A B OR2A signal; comparing the current clock value against ’1’ implies B Y C AO1C DQ DOUT0 DIN3

that p_state gets the n_state value on a 0 to 1 transition DFC1B CLK CLR DOUT3 (rising edge). RESET_B A Y CLEAR_B B OR2A 6 6 A Y → The state holding action of the process arises from the fact B OR2B LOAD that p_state is not assigned a value is reset is not asserted reg8bit WIR:reg8bit and a rising clock edge does not occur. SCH:reg8bit 6 Jan 94 14:25 SHEET 1 OF 1

A B C D E

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wait Statement Finite State Machine Example

⇒ alternative method of specifying the storage elements is shown HG An FG HL:GRN HL:RED below: FL:RED FL:GRN

Traffic Light Controller state: process F F begin TIMER ALARM + CAR wait until ((clk’event and clk = ’1’) or (reset = ’0’)); T if (reset = ’0’) then p_state <= (others => ’0’); HGC HL:GRN else FL:RED T→START_SHORT_TIMER p_state <= n_state; end if; F FY HL:RED end process state; CAR FL:YEL

T ⇒ The wait statement is a sequential statement. start timer with short value F T →START_SHORT_TIMER ⇒ The wait statement causes a suspension of a process or proce- ALARM dure until the condition clause is satisfied. T HY HL:YEL FL:RED T→START_LONG_TIMER ⇒ The signals used in the condition clause form an implicit sensitivity list for the wait statement.

start timer with long value F HG → Can use ’wait on sig1, sig2, ..sigN until condition_clause’ to ALARM

explicitly specify the sensitivity list. T Upon RESET enter state HGC → Note that the process has no sensitivity list. T→START_LONG_TIMER

⇒ ’if’ statements used with processes generally give more flexibility and control than ’wait’ statements .

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Traffic Light Controller Block Diagram VHDL For Traffic Light FSM Control

library ieee; TimerIn Glue use ieee.std_logic_1164.all; N select long load –– vhdl model for the Traffic Light Control, sync reset, encoded states 0/1 0 entity tlc_enc is port( LONG REG SHORT REG signal reset, car, timer, clk: in std_logic; short load signal stateout: out std_logic_vector(2 downto 0); load 1 en signal highway_light, farm_light: out std_logic_vector(1 downto 0); signal start_short_timer, start_long_timer: out std_logic ); N N end tlc_enc; TLC Control State assignments Timer architecture behavior of tlc_enc is car Port B Port A car constant HGC: std_logic_vector(2 downto 0) := ”000”; start_short_timer start_A constant HY: std_logic_vector(2 downto 0) := ”001”; start_long_timer start_B constant FG: std_logic_vector(2 downto 0) := ”010”; timer alarm constant FY: std_logic_vector(2 downto 0) := ”011”; constant HG: std_logic_vector(2 downto 0) := ”100”; count constant GREEN: std_logic_vector(1 downto 0) := ”00”; constant YELLOW: std_logic_vector(1 downto 0) := ”01”; fl hl constant RED: std_logic_vector(1 downto 0) := ”11”;

2 2 signal p_state, n_state : std_logic_vector(2 downto 0);

begin stateout <= p_state; fl hl count statereg: process(clk, reset) if (reset = ’0’) then p_state <= HGC; elsif (clk’event and clk = ’1’) then p_state <= n_state; end if; end process statereg;

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VHDL For Traffic Light FSM (cont) VHDL For Traffic Light FSM Control (cont.)

comb:process(car, timer, p_state) All outputs should be begin assigned default –– default assignments –– VERY IMPORTANT values!! If you do not start_short_timer <= ’0’; assign default values start_long_timer <= ’0’; then outputs may get if p_state = FG then –– by default, stay in same state!!! synthesized with highway_light <= RED; farm_light <= GREEN; output latches! n_state <= p_state; if timer = ’1’ or car = ’0’ then Use ’if’ statements highway_light <= GREEN; farm_light <= RED; n_state <= FY; start_short_timer <= ’1’; end if; to enumerate end if; states. if p_state = HG then if p_state = FY then highway_light <= GREEN; farm_light <= RED; highway_light <= RED; farm_light <= YELLOW; if (timer = ’1’) then n_state <= HGC; end if; if timer = ’1’ then end if; Start timer with n_state <= HG; start_long_timer <= ’1’; end if; short timeout value end if; if p_state = HGC then (yellow light). highway_light <= GREEN; farm_light <= RED; if car = ’1’ then end process comb; n_state <= HY; start_short_timer <= ’1’; end if; end if; Start timer with end behavior; long timeout value. if p_state = HY then highway_light <= YELLOW; farm_light <= RED; if timer = ’1’ then n_state <= FG; start_long_timer <= ’1’; end if; end if;

Bob Reese 5/95 SeqSyn–11 Sequential Circuits Bob Reese 5/95 SeqSyn–12 Sequential Circuits Electrical & Computer Engineering Mississippi State University Electrical & Computer Engineering Mississippi State University

One–Hot Encoding for FSMs

⇒ One–Hot encoding of FSMs uses one flip–flop per state. STATEOUT1 START_LONG_TIMER START_SHORT_TIMER FARM_LIGHT0 STATEOUT2 HIGHWAY_LIGHT0 HIGHWAY_LIGHT1 FARM_LIGHT1 STATEOUT0

→ Only one flip–flop is allowed ’on’ at anytime.

→ E.G., states are ”00001”, ”00010”, ”00100”, ”01000”, ”10000” for a five state FSM. All other states are illegal. Y Y ⇒ One–Hot encoding trades combinational logic for flip–flops. AO1C AO1C Y Q Y Y DFMB CLR CLK NAND2B INVA INVA A B S A B

A B C A B C → A A Good for ’flip–flop’ rich implementation technologies.

→ Because the combinational logic is reduced, the length of the critical path can be reduced resulting in a faster FSM. Y Y Y Y Q Q Speed increase is more significant for larger finite state Y CLR CLR DFC1B OR4A DFC1B CLK CLK OR2A OR2A OR2A INVA D D A B C D A A B A B A B machines. Y Y AO1 AO1 Y INVA A B C A B C A Y Y Y AND3 OR2A NAND3B A B C A B C A B SET MER CAR CLK E I

Bob Reese 5/95 SeqSyn–13 Sequential Circuits Bob Reese 5/95 SeqSyn–14 Sequential Circuits Electrical & Computer Engineering Mississippi State University Electrical & Computer Engineering Mississippi State University

One Hot Encoding for TLC One Hot Encoding for TLC

library IEEE; use IEEE.std_logic_1164.all; comb:process(car, timer, p_state)

entity tlc_onehot is port ( begin signal reset, car, timer, clk: in std_logic; –– default assignments –– VERY IMPORTANT signal stateout: out std_logic_vector(4 downto 0); start_long_timer <= ’0’; start_short_timer <= ’0’; start <= ’0’; signal highway_light,farm_light: out std_logic_vector(1 downto 0); n_state <= p_state; signal start_long_timer,start_short_timer: out std_logic highway_light <= GREEN; farm_light <= RED; ); end tlc_onehot; if p_state(HG) = ’1’ then architecture behavior of tlc_onehot is highway_light <= GREEN; farm_light <= RED; constant HG: integer := 0; if (timer = ’1’) then n_state(HG) <= ’0’; n_state(HGC) <= ’1’; constant HGC: integer := 1; State assignments now constant HY: integer := 2; specify bit positions in end if; When changing the state FFs end if; constant FG: integer := 3; states you must turn constant FY: integer := 4; if p_state(HGC) = ’1’ then off current state FF highway_light <= GREEN; farm_light <= RED; and turn on next constant GREEN: std_logic_vector(1 downto 0) := ”00”; state FF. constant YELLOW: std_logic_vector(1 downto 0) := ”01”; if car = ’1’ then constant RED: std_logic_vector(1 downto 0) := ”11”; n_state(HGC) <= ’0’; n_state(HY) <= ’1’; start_short_timer <= ’1’; signal p_state, n_state : std_logic_vector(4 downto 0); end if; end if; begin stateout <= p_state; if p_state(HY) = ’1’ then Initial state is highway_light <= YELLOW; farm_light <= RED; state: process(clk, reset) ’00010’ if timer = ’1’ then begin n_state(HY) <= ’0’; n_state(FG) <= ’1’; if (reset = ’0’) then p_state <= (HGC => ’1’, others => ’0’); start_long_timer <= ’1’; elsif (clk’event and clk = ’1’) then end if; p_state <= n_state; end if; end if; end process state;

Bob Reese 5/95 SeqSyn–15 Sequential Circuits Bob Reese 5/95 SeqSyn–16 Sequential Circuits Electrical & Computer Engineering Mississippi State University Electrical & Computer Engineering Mississippi State University

One Hot Encoding for TLC LTIME STATEOUT2 FL1 HL1 HL0 STATEOUT3 STATEOUT1 STIME STATEOUT0 STATEOUT4 FL0 START

if p_state(FG) = ’1’ then Y Y Y highway_light <= RED; farm_light <= GREEN; Q Q Y Y DFMB PRE DFP1B CLR CLK CLK OR2A OR2A NAND2B INVA INVA if timer = ’1’ or car = ’0’ then D A B S A B A A n_state(FG) <= ’0’; n_state(FY) <= ’1’; A B A B start_short_timer <= ’1’; end if; end if; Y if p_state(FY) = ’1’ then Y Y OAI1 AO1 AO1C Y Q highway_light <= RED; farm_light <= YELLOW; Q Q CLR CLR CLR DFC1B DFC1B DFC1B CLK CLK CLK NAND2B D if timer = ’1’ then D D A B C A B A B C A B C n_state(FY) <= ’0’; n_state(HG) <= ’1’; start_long_timer <= ’1’; end if; end if; Y Y Y

AO1C AO1C AO1C Y Y Y AND2 OR3B INVA A B A B C A B C A B C B C A end process comb; A

end behavior; Y Y Y Y OR2A OR3B OR3B OR2A A B C A B C A B A B SET ARM CLK CAR E L

Bob Reese 5/95 SeqSyn–17 Sequential Circuits Bob Reese 5/95 SeqSyn–18 Sequential Circuits Electrical & Computer Engineering Mississippi State University Electrical & Computer Engineering Mississippi State University

Simple 4–bit Shift Register Loop function for Shift Register

library IEEE; use IEEE.std_logic_1164.all; ’din’ is serial input comb:process (p_state,din) entity shift4 is port( begin MSB of ’dout’ is signal clk, reset: in std_logic; n_state(0) <= din; the serial output signal din: in std_logic; for i in 3 downto 1 loop signal dout: out std_logic_vector(3 downto 0) n_state(i) <= p_state(i – 1); ); end shift4; end loop; architecture behavior of shift4 is end process comb; signal n_state, p_state : std_logic_vector(3 downto 0); Left Shift Operation (LSB to MSB) LSB begin n_state(0) n_state(1) dout <= p_state; D state: process(clk, reset) Q D n_state(2) DIN p_state(0) begin Q D if (reset = ’0’) then p_state <= (others => ’0’); p_state(1) elsif (clk’event and clk = ’1’) then Q Assign serial input ’din’ p_state(2) i=0 p_state <= n_state; to the ’data’ input of the MSB end if; first flip–flop i=1 end process state; i=2 Use ’for’ loop to connect comb:process (p_state,din) output of previous n_state(i) begin flip–flop to input of current n_state(0) <= din; D flop–flop p_state(i–1) for i in 3 downto 1 loop Q n_state(i) <= p_state(i – 1); p_state(i)

end loop;

end process comb; i’th stage end behavior;

Bob Reese 5/95 SeqSyn–19 Sequential Circuits Bob Reese 5/95 SeqSyn–20 Sequential Circuits Electrical & Computer Engineering Mississippi State University Electrical & Computer Engineering Mississippi State University

Scan Path Synthesis 1 2 3 4

⇒ The ’for–loop’ VHDL construct can be used to create a scan–path F F in your design. A scan path is a design technique used for improv- SHEET 1 OF 1 ing the testability of a design. DOUT0 DOUT1 DOUT2 DOUT3 E E → A scan path requires three extra pins on the design: ’scan’, shift4 ’scan_in’, and ’scan_out’. 6 Jan 94 14:46 D D

Q → When ’scan’ is asserted, all flip–flops in the design act like a CLR DFC1B CLK serial shift register; the ’scan_in’ pin is the serial input and D C C WIR:shift4 SCH:shift4 the ’scan_out’ pin the serial output. Whenscan ’ ’ is negated the design functions normally. DIN B B → Because all flip–flops in the design are on the scan path the Q Q Q

CLR CLR CLR circuit can be placed in any desired state. DFC1B DFC1B DFC1B CLK CLK CLK D D D A A ⇒ To enter a test vector via the scan path do:

→ 1 2 3 4 Assert ’scan’. → Apply the test vector serially to the ’scan_in’ input; this CLK requires N clocks if N flip–flops are on the scan path. RESET_B → Negate ’scan’, clock the circuit once. This will allow the circuit to operate normally for one clock cycle; the result of the test vector will be loaded into the flip–flops.

→ Assert ’scan’; clock N times to clock out the test vector result and to clock in the next test vector. Thus, each test vector requires N+1 clocks.

Bob Reese 5/95 SeqSyn–21 Sequential Circuits Bob Reese 5/95 SeqSyn–22 Sequential Circuits Electrical & Computer Engineering Mississippi State University Electrical & Computer Engineering Mississippi State University

4–bit Register with Scan Path Adding Scan to tlc_onehot.vhd

entity scanreg4 is port ( ⇒ Add ’scan’, ’scan_in’ to port list. ’scan_out’ will be MSB of port signal clk, reset_b, load: in std_logic; ’scan’, ’scan_in’ signal scan, scan_in: in std_logic; signals ’stateout’. signal din: in std_logic_vector(3 downto 0); signal dout: out std_logic_vector(3 downto 0) entity tlc_onehot_scan is port ( ); end scanreg4; ’scan_out’ will be signal reset, car, timer, clk: in std_logic; MSB of ’dout’; don’t need an extra pin signal scan, scan_in: in std_logic; architecture behavior of scanreg4 is for ’scan_out’. signal n_state, p_state : std_logic_vector(3 downto 0); signal stateout: out std_logic_vector(4 downto 0); signal highway_light,farm_light: out std_logic_vector(1 downto 0); begin signal start_long_timer, start_short_timer: out std_logic dout <= p_state; ); end tlc_onehot_scan; state: process(clk, reset) begin if (reset = ’0’) then p_state <= (others => ’0’); ⇒ Add ’scan’, ’scan_in’ to sensitivity list of process: state_machine. elsif (clk’event and clk = ’1’) then When ’scan’ is p_state <= n_state; asserted the scan end if; path is active. state_machine:process(scan, scan_in, reset, car, timer, p_state) end process state;

process (scan,scan_in,load,p_state,din) ⇒ Add scan path in Architecture body: begin n_state <= p_state; if (scan = ’1’) then if (scan = ’1’) then n_state(0) <= scan_in; n_state(0) <= scan_in; for i in 3 downto 1 loop for i in 4 downto 1 loop n_state(i) <= p_state(i – 1); n_state(i) <= p_state(i – 1); end loop; Register functions end loop; elsif (load = ’1’) then normally when else n_state <= din; ’scan’ is negated. end if; if p_state(HG) = ’1’ then end process; highway_light <= GREEN; farm_light <= RED; end behavior; .... etc...

Bob Reese 5/95 SeqSyn–23 Sequential Circuits Bob Reese 5/95 SeqSyn–24 Sequential Circuits A B C D

1 1

2 2

Electrical & Computer Engineering Mississippi State University Electrical & Computer Engineering Mississippi State University

Mapped to ITD stdcell library because ACT1 does not have tristate capability.

A1 DATA1 Register with TriState Output 3 3 A1 O B1 dfrf301 Q invf101 C2 O A1 O CLK2 DIN5 D2 RST3 invf101 oaif2201 A1 library IEEE; use IEEE.std_logic_1164.all; DATA1 A1 O B1 dfrf301 invf101 C2 O Q A1 O entity tsreg8bit is port ( signal clk, reset, load, en: in std_logic; D2 DIN4 CLK2 EN2 O DOUT4 oaif2201 RST3 DATA1 signal din: in std_logic_vector(7 downto 0); invf101 buff121 A1 EN2 signal dout: out std_logic_vector(7 downto 0) DATA1 O A1 O DATA1 B1 buff121 dfrf301 ); invf101 C2 O Q DOUT1 A1 O EN2 DIN7 D2 CLK2 DATA1 O end tsreg8bit; buff121 invf101 oaif2201 RST3 4 4 EN2 A1 DATA1 O DOUT5 architecture behavior of tsreg8bit is DATA1 buff121 A1 O B1 dfrf301 C2 Q EN2 signal n_state, p_state : std_logic_vector(7 downto 0); invf101 O O A1 O DATA1 DIN6 D2 CLK2 buff121 invf101 oaif2201 RST3 begin DOUT7 A1 Make Z assignment to DATA1 A1 O B1 dout <= p_state when (en = ’1’) dfrf301 specify tristate invf101 C2 O Q A1 O else ”ZZZZZZZZ”; D2 capability. DIN1 CLK2 DOUT6 invf101 oaif2201 RST3 A1 state: process(clk, reset) A1 O B1 DATA1 invf101 begin A1 O C2 O dfrf301 Q EN2 5 D2 O 5 invf101 DATA1 if (reset = ’0’) then p_state <= (others => ’0’); oaif2201 CLK2 buff121 elsif (clk’event and clk = ’1’) then A1 RST3 LOAD O B1 p_state <= n_state; CLEAR_B nanf201 A1 end if; O A1 DATA1 B2 nanf251 A1 O B1 dfrf301 DIN0 Q EN2 end process state; O C2 O DATA1 invf101 CLK2 buff121 comb: process (p_state, load, din) A1 O D2 DIN2 RST3 oaif2201 begin invf101 A1

A1 O B1 n_state <= p_state; DATA1 invf101 C2 O dfrf301 if (load = ’1’) then n_state <= din; A1 O Q D2 EN2 DOUT0 DIN3 O oaif2201 DATA1 end if; invf101 6 CLK2 buff121 6 RST3

end process comb; RESET_B CLK end behavior; EN tsreg8bit WIR:tsreg8bit

SCH:tsreg8bit 6 Jan 94 14:50 SHEET 1 OF 1

A B C D

Bob Reese 5/95 SeqSyn–25 Sequential Circuits Bob Reese 5/95 SeqSyn–26 Sequential Circuits DOUT2

DOUT3 Electrical & Computer Engineering Mississippi State University

VHDL Packages

⇒ A VDHL package is a mechanism for collecting procedures, func- tions, constants, and components for future re–use.

⇒ A package contains a package declaration followed by a package body.

→ Package declaration Logic Synthesis with VHDL package package_name is System Synthesis { external constant, procedure, function, component declarations } end package_name;

→ Package body

package body package_name is

Bob Reese {constant, procedure, function, component Electrical Engineering Department definitions } Mississippi State University end package_name; ⇒ Any items in the package declaration are available for external use. There can be items in the package body which are not in the package declaration; these items are only available for use within the package.

Bob Reese 5/95 System–2 System Design with VHDL Electrical & Computer Engineering Mississippi State University Electrical & Computer Engineering Mississippi State University

Example VHDL Package VHDL Functions

Library IEEE; use IEEE.std_logic_1164.all; ⇒ General form: package iscas is function function_name ( parameter list) return return_type is {variable declarations} procedure ripple_adder (a,b: in std_logic_vector; cin: in std_logic; begin sum: inout std_logic_vector; cout: out std_logic); {sequential statements} end iscas; end function_name; package body iscas is function xor3 (a,b,c: in std_logic) return std_logic is function xor3 (a,b,c: in std_logic) return std_logic is begin begin return (a xor b xor c); return (a xor b xor c); end xor3; end xor3; ⇒ A VHDL function computes a return value based upon its parame- procedure ripple_adder (a,b: in std_logic_vector; cin: in std_logic; ter list. sum: inout std_logic_vector; cout: out std_logic) is → All parameters passed to a VHDL function must be of modein; variable c: std_logic_vector((a’high–a’low+1) downto 0); i.e, the function is not allowed to modify any of the function begin parameters. c(0) := cin; for i in 0 to (a’high–a’low) loop → The default class of the elements in a parameter list for either sum(i+sum’low) := xor3 (a(i+a’low), b(i+b’low), c(i) ); procedures or functions is variable. c(i+1) := (a(i+a’low) and b(i+b’low)) or → Signals can be passed in the parameter list; in this case the (c(i) and (a(i+a’low) or b(i+b’low))); end loop; parameter list would look like: cout := c(c’high); (signal a, b, c: std_logic) end ripple_adder; → More on the difference between variables and signals will be end iscas; given later.

Bob Reese 5/95 System–3 System Design with VHDL Bob Reese 5/95 System–4 System Design with VHDL

Electrical & Computer Engineering Mississippi State University Electrical & Computer Engineering Mississippi State University

VHDL Procedures Signals vs Variables

⇒ General form: ⇒ Only signals are used as the connection ports for VHDL entities. procedure procedure_name ( parameter list) is → Variables are declared within process blocks, procedures, {variable declarations} and functions. begin {sequential statements} → Signals can only be declared within architecture bodies; they end procedure_name; can be passed as parameters to functions and procedures.

⇒ The ripple_adder procedure implements the ripple carry adder ⇒ Signals are assigned via ”<=”; Variables are assigned via ”:=”. used in previous examples. ⇒ From a simulation point of view: ⇒ The ripple_adder procedure uses the local xor3 function defined → Signals have events occurring on them and this event history within the package. is tracked via an internal event list. sum(i+sum’low) := xor3 (a(i+a’low), b(i+b’low), c(i) ); → Signal assignment can be delayed such as: ⇒ For generality, the input parameters ’a’ and ’b’ as well as the output a <= ’1’ after 10 ns ’sum’ are declared as unconstrained array types; i.e., no array → bounds are given for the std_logic_vector type. Variable assignment is always immediate. a <= ’1’; → Allows any width vector to be passed as a parameter. → Signals require more overhead in terms of storage and → Array indices must be computed using the ’low attribute as an simulation time than variables. A general rule of thumb is to offset in order to achieve independence from the actual array use variables wherever possible. indices which are passed in. ⇒ From a synthesis point of view, both variables and signals can turn into internal circuit nodes.

Bob Reese 5/95 System–5 System Design with VHDL Bob Reese 5/95 System–6 System Design with VHDL Electrical & Computer Engineering Mississippi State University Electrical & Computer Engineering Mississippi State University

Using the ripple_adder Procedure A Carry Select Adder

Each stage computes part of the Library IEEE; sum. Typically, the stage sizes in- ’work’ is the default library name for CI use IEEE.std_logic_1164.all; A crease; so a 16 bit adder stage packages. The ’all’ keyword says to SUM SUM sizes might be 4, 5, 7 = total of use work.iscas.all; use all externally available package B 16 bits. Ripple adders are used items in the ’iscas’ package. COUT entity adder_test is K bits for stage adders. port ( CS0 signal a,b: in std_logic_vector (15 downto 0); signal cin: in std_logic; 0 1 signal sum: out std_logic_vector(15 downto 0); 0 CI CI SUM signal cout: out std_logic A A SUM SUM ); B B 1 end adder_test; COUT COUT MUX L bits architecture behavior of adder_test is begin CS0 process (a,b,cin) variable temp_sum: std_logic_vector (sum’range); CS1 0 1 variable temp_cout: std_logic; 0 SUM begin CI CI ripple_adder(a, b, cin, temp_sum, temp_cout); A A SUM SUM sum <= temp_sum; B B 1 COUT COUT cout <= temp_cout; Call the ’ripple_adder’ procedure. M bits MUX end process; Variables are used as parameters within ’ripple_adder’ so variables CS1 must be passed in as arguments. CS2 end behavior; These variables are then assigned to the target signals...... etc.

Bob Reese 5/95 System–7 System Design with VHDL Bob Reese 5/95 System–8 System Design with VHDL Electrical & Computer Engineering Mississippi State University Electrical & Computer Engineering Mississippi State University

Carry_Select_Adder Procedure iscas Package Declaration

procedure carry_select_adder Library IEEE; (groups: iarray; a,b: in std_logic_vector; cin: in std_logic; use IEEE.std_logic_1164.all; sum: inout std_logic_vector; cout: out std_logic) is

variable low_index, high_index :integer; package iscas is variable temp_sum_a, temp_sum_b : std_logic_vector(sum’range); variable carry_selects :std_logic_vector(groups’range); type IARRAY is array (natural range <>) of integer; variable carry_zero :std_logic_vector(groups’low to (groups’high–1)); variable carry_one :std_logic_vector(groups’low to (groups’high–1)); procedure ripple_adder (a,b: in std_logic_vector; cin: in std_logic; begin sum: inout std_logic_vector; cout: out std_logic); low_index := 0; for i in groups’low to groups’high loop high_index := (groups(i)–1) + low_index ; procedure carry_select_adder if (i = 0) then –– first group, just do one ripple–carry (groups: iarray; a,b: in std_logic_vector; cin: in std_logic; ripple_adder (a(high_index downto low_index), b(high_index downto low_index), sum: inout std_logic_vector; cout: out std_logic); cin, sum(high_index downto low_index), carry_selects(0) ); end iscas; else –– need to do two ripple carry adders then use mux to select ⇒ We need to declare an array type for integers; call this IARRAY. ripple_adder (a(high_index downto low_index), b(high_index downto low_index), ’0’, temp_sum_a(high_index downto low_index), carry_zero(i–1)); This type will be used to pass in an integer array to the carry_se- lect_adder procedure; the integer array will be define the stage ripple_adder (a(high_index downto low_index), b(high_index downto low_index), ’1’, temp_sum_b(high_index downto low_index), carry_one(i–1)); sizes for the adder. if (carry_selects(i–1) = ’0’) then sum(high_index downto low_index) := temp_sum_a(high_index downto low_index); ⇒ Since xor3 is to be local to the iscas package; it is not in the pack- else age declaration. However, if it was to be made externally avail- sum(high_index downto low_index) := temp_sum_b(high_index downto low_index); end if; able, its declaration would be: carry_selects(i) := (carry_selects(i–1) and carry_one(i–1) ) or carry_zero(i–1); end if; low_index := high_index + 1; function xor3 (a,b,c: in std_logic) return std_logic; end loop; cout := carry_selects(groups’high); end ripple_adder;

Bob Reese 5/95 System–9 System Design with VHDL Bob Reese 5/95 System–10 System Design with VHDL Electrical & Computer Engineering Mississippi State University Electrical & Computer Engineering Mississippi State University A B C D

cout sum(15:0) sum(15:0) 8 4 5 6 7 0 1 2 3 9 cout 11 12 13 14 10 15 sum(5) sum(8) sum(4) sum(9) 8 8 sum(0) sum(2) sum(3) sum(1) sum(10) sum(15) sum(7) sum(6) sum(14)

Using the carry_select_adder Procedure sum(11) sum(12) sum(13)

n1042 n997 n1022 n1009 a(15) n1045 15 b(15) n962

15 n958

n1017 n1030 n1037 n979 n1028 n1015 n1000 n1035 n1001 n999 n1003 n1023 Library IEEE; n1043 n961 n964 n987 n991 n1046 n957 n988 7 7 n1005 use IEEE.std_logic_1164.all; n1010 n1016 n1038 n1031 n1024 n1018 n1011 n1060 a(0) n981

b(0) a(2) a(1) b(2) b(1) 0

0 a(10)

10 b(10)

10

1

use work.iscas.all; 1 2

a(3) 2

b(3) 3

a(9) 3

a(8) 9

a(4) 8

b(4) n1004 4

4 b(15)

15 15

n1019

a(15) n1029

n1039 n1002 n998 n983 n1032 n1062 n973 n1025 n1012 n1033 n1006

entity adder_cs is n1036 n976 n980 n1063 n1065 6 6 a(7) b(7) a(11)

port ( b(11)

7

11 13 a(13) n974 n1061 n985 b(13) a(8) n1064 b(9)

a(5) 9

b(8) 8 8 5

signal a,b: in std_logic_vector (15 downto 0); 7 11 13

b(5) 5 n984 n1007 n982 signal cin: in std_logic; n959 n975 n1034 n1026 n1013 a(6) 6 12 14 a(14) a(12) b(6) b(12)

signal sum: out std_logic_vector(15 downto 0); 6 12 14 5 signal cout: out std_logic 5 n1008 n1014 n1057 b(8) 14 8 b(14) a(14) b(14) a(8) ); 14 8 end adder_cs; Define local constant array of in- n960

tegers to define the stage sizes for n1021

14 a(14)

14

13 a(13)

13 b(14)

8 a(8) 8 b(13)

b(8) n1059

the adder. 4 + 5 + 7 = 16 bits. n969 n996 4 architecture behavior of adder_cs is 4

Must be a constant array so that n1056 n1020

n1027 n1055

12 a(12) 12 n972 n971

stage sizes are known at compile n1058 b(12)

begin n970 time.

n993

12

process (a,b,cin) a(12)

12 10

a(9)

10 b(12)

9 n995

b(10)

11 a(11) a(10)

11 b(11) n994 variable temp_sum: std_logic_vector (sum’range); n963 3 3 n1047 variable temp_cout: std_logic; n1054

n1041

3 3 n977

b(3) 7 a(7)

a(3) 7 b(7) n1053 n978

constant groups: iarray(0 to 2) := (4,5,7); n1044 n986 n1048 n968 n1052 n1050 a(9) a(6) a(3) a(2) 9 10 2 3 6 a(10) n1040 b(9) b(3) b(2) b(10) b(6) 9 10 2 3 6 n992 begin n1051 n989 2 2

carry_select_adder(groups,a,b,cin,temp_sum, temp_cout); n1049

n967

1

1 a(1)

b(1) 2

a(5) 2

sum <= temp_sum; b(2) 5

a(2) b(6) 6 a(6)

b(5) 6

5

4 a(4)

b(4) 4 n990 cout <= temp_cout; n966 b(0) b(1) 0 1 a(0) a(1) end process; 0 1 n965 1 1 a(15:0) b(15:0) b(0) 0 cin cin a(15:0) end behavior; b(15:0) D C B A

Bob Reese 5/95 System–11 System Design with VHDL Bob Reese 5/95 System–12 System Design with VHDL Electrical & Computer Engineering Mississippi State University Electrical & Computer Engineering Mississippi State University

VHDL Generic lists VHDL Generic lists (cont.)

⇒ VHDL generic lists are used in entity declarations for passing stat- Generic declaration which Library IEEE; ic information. is used to define the use IEEE.std_logic_1164.all; a,b,sum signal widths. use work.iscas.all; → Typical uses of generics are for controlling bus widths, feature Default value is specified inclusion, message generation, timing values. entity adder_test is as 16. generic ( N : integer := 16); ⇒ A generic will usually have a specified default value; this value can port ( be overridden via VHDL configurations or by vendor–specific signal a,b: in std_logic_vector (N–1 downto 0); back–annotation methods. signal cin: in std_logic; signal sum: out std_logic_vector(N–1 downto 0); → Generics offer a method for parameterizing entity signal cout: out std_logic declarations and architectures. Because the method of ); specifying generic values (other than defaults) can be end adder_test; vendor specific, generics will not be covered further in this architecture behavior of adder_test is tutorial. begin process (a,b,cin) variable temp_sum: std_logic_vector (sum’range); variable temp_cout: std_logic; begin ripple_adder(a, b, cin, temp_sum, temp_cout); sum <= temp_sum; cout <= temp_cout; end process;

end behavior;

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Operator Overloading Operator Overloading (cont.)

Library IEEE; use IEEE.std_logic_1164.all; function mux (a,b,c: std_logic; sel: std_logic_vector) return std_logic is variable y: std_logic; package genmux is begin –– 2/1 version, 1 bit inputs y := ’–’; –– Don’t care for default state function mux (a,b: std_logic; sel: std_logic) return std_logic; if (sel = ”00”) then y := a; end if; if (sel = ”01”) then y := b; end if; –– 2/1 version, N bit inputs if (sel = ”10”) then y := c; end if; function mux (a,b: std_logic_vector; sel: std_logic) return std_logic_vector; return(y); end mux; –– 3/1 version, 1 bit inputs –– 3/1 version, 1 bit inputs function mux (a,b,c: std_logic; sel: std_logic_vector) return std_logic; function mux (a,b,c: std_logic_vector; sel: std_logic_vector) return std_logic_vector is –– 3/1 version, N bit inputs variable y: std_logic_vector(a’range); function mux (a,b,c: std_logic_vector; sel: std_logic_vector) return std_logic_vector; begin y := (others => ’–’); –– Don’t care for default state –– 4/1 version, 1 bit inputs if (sel = ”00”) then y := a; end if; if (sel = ”01”) then y := b; end if; function mux (a,b,c,d: std_logic; sel: std_logic_vector) return std_logic; if (sel = ”10”) then y := c; end if; –– 4/1 version, N bit inputs return(y); function mux (a,b,c,d: std_logic_vector; sel: std_logic_vector) return std_logic_vector; end mux; –– 3/1 version, N bit inputs end genmux; function mux (a,b,c,d: std_logic; sel: std_logic_vector) return std_logic is variable y: std_logic; package body genmux is begin function mux (a,b: std_logic; sel: std_logic) return std_logic is y := d; variable y: std_logic; if (sel = ”00”) then y := a; end if; if (sel = ”01”) then y := b; end if; begin if (sel = ”10”) then y := c; end if; y := a; return(y); if (sel = ’1’) then y := b; end if; end mux; –– 4/1 version, 1 bit inputs return(y); end mux; –– 2/1 version, 1 bit inputs function mux (a,b,c,d: std_logic_vector; sel: std_logic_vector) return std_logic_vector is variable y: std_logic_vector(a’range); function mux (a,b: std_logic_vector; sel: std_logic) return std_logic_vector is begin variable y: std_logic_vector(a’range); y := d; begin if (sel = ”00”) then y := a; end if; if (sel = ”01”) then y := b; end if; y := a; if (sel = ”10”) then y := c; end if; if (sel = ’1’) then y := b; end if; return(y); return(y); end mux; –– 4/1 version, N bit inputs end mux; –– 2/1 version, N bit inputs end genmux;

Bob Reese 5/95 System–15 System Design with VHDL Bob Reese 5/95 System–16 System Design with VHDL Electrical & Computer Engineering Mississippi State University Electrical & Computer Engineering Mississippi State University

Test of ’mux’ Function D A B C Library IEEE; 8 use IEEE.std_logic_1164.all; 8

use work.genmux.all; y z(3:0) z(3:0) 2 3 0 1 z(2) z(1) z(0) z(3) 7 entity muxtest is 7 n152 n154 n156 port ( n150 n151 n153 n155 signal a,b,c: in std_logic; n149 n164 y 6 signal s_a: in std_logic_vector(1 downto 0); 6 signal y: out std_logic; k(0) 3 0 1 2 k(3) k(2) k(1) j(2) j(1) j(0) j(3) l(3) 2 3 0 1 l(2) l(1) signal j,k,l: in std_logic_vector(3 downto 0); l(0) 2 3 0 1 n159 5 5 n157

signal s_b: in std_logic_vector(1 downto 0); n162 signal z: out std_logic_vector(3 downto 0) ); 0 0 n163 s_a(0) s_a(0) 4 end muxtest; 4 n158 n160 architecture behavior of muxtest is 0 0 s_b(0) s_b(0)

3 3 begin 1 n161 s_a(1) y <= mux (a,b,c,s_a); z <= mux (j,k,l,s_b); 2 2 b 1 l(3:0) s_b(1) a s_a(1:0) j(3:0) k(3:0) c s_b(1:0) a c end behavior; b j(3:0) l(3:0) k(3:0) s_a(1:0) s_b(1:0) 1 The mux operator is overloaded; the 1 correct mux function is chosen by C D doing template matching on the pa- A B rameter lists.

Bob Reese 5/95 System–17 System Design with VHDL Bob Reese 5/95 System–18 System Design with VHDL Electrical & Computer Engineering Mississippi State University Electrical & Computer Engineering Mississippi State University

BlackJack Dealer BlackJack Dealer Control

⇒ BlackJack Dealer This example will be a BlackJack Dealer circuit (example taken GET from The Art of Digital Design, Prosser & Winkel, Prentice–Hall). wait for card ⇒ One VHDL model will be written for the control and one for the da- F card.rdy.sync T→hit tapath. A schematic will be used to tie these two blocks together. T

→ Later, a VHDL structural model will be used to connect the T wait until button card.rdy.delay blocks. is lifted F ⇒ Control: F→stand.out F→broke.out → Four States: Start game over Get –– get a card stand T + REG: Clear score Add –– add current card to score → broke F ace11flag.out Use –– use an ACE card as 11 F

Test –– see if we should stand or if we are broke ADD MUX: Select Card Add card value ⇒ Datapath: REG: Load score

→ 5–bit register for loading score; needs a synchronous clear. T F acecard ace11flag USE → Mux for choosing between card value, plus 10 and minus 10. F T

→ Adder for adding card with current score. MUX: Select ADD10 REG: Load score → ACE card detect (an ACE card has value ’0001’) T→ace11flag.out Use ACE as 11 → Comparator logic for checking is score is greater than 16 or To TEST greater than 21. state

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BlackJack Dealer Control (cont) BlackJack Datapath

5 +10 clear 5 –10 MUX 5 4 5 ADDER 5 Score 5 5

TEST Card Switches 2 REG

Cancel ACE=11 sel

F MUX: Select SUB10 Ace Finder score16gt REG: Load score acecard load F→ace11flag.out T score ace11flag.out T T score21gt ace11flag ace11flag F F 5 score16gt Comparator score21gt → T→broke.out T stand.out Miscellanous Flip Flops to Score is > 16 and Score > 21 and we be included in Control < 21 so stand can’t adjust an ACE value so we are broke Card card.rdy.sync Rdy stand.out stand button

To GET state

card.rdy.delay broke.out broke

Bob Reese 5/95 System–21 System Design with VHDL Bob Reese 5/95 System–22 System Design with VHDL Electrical & Computer Engineering Mississippi State University Electrical & Computer Engineering Mississippi State University

VHDL File for BlackJack Datapath VHDL File for BlackJack Datapath (cont.)

entity bjdpath is port ( signal clk,reset_b, load, clear_b: in std_logic; signal sel: in std_logic_vector(1 downto 0); –– adder process ADDER process signal card: in std_logic_vector(3 downto 0); –– adder_out <= score_out + mux_out signal acecard,score16gt,score21gt: out std_logic; adder:process (score_out, mux_out) signal score: out std_logic_vector(4 downto 0) begin );end bjdpath; c(0) <= ’0’; architecture behavior of bjdpath is for i in score_out’range loop signal adder_out, score_in: std_logic_vector(4 downto 0) adder_out(i) <= score_out(i) xor mux_out(i) xor c(i); mux_out, score_out : std_logic_vector(4 downto 0); c(i+1) <= (score_out(i) and mux_out(i)) or –– temporary signal for carries (c(i) and (score_out(i) or mux_out(i))); signal c: std_logic_vector (5 downto 0); end loop; end process adder; MUX for State process for begin card, plus 10, score register flip– mux_out <= ”01010” when (sel = B”00”) else minus 10. score_state: process(clk, reset_b) flops. begin ”10110” when (sel = B”10”) else if (reset_b = ’0’) then score_out <= ”00000”; ’0’ & card; elsif (clk’event and clk = ’1’) THEN Combinational logic acecard <= ’1’ when (card = B”0001”) else ’0’; Ace Finder score_out <= score_in; for Score Register END IF; score <= score_out; end process score_state; score16gt <= ’1’ when (score_out > B”10000”) else ’0’; –– combinational logic for score register score21gt <= ’1’ when (score_out > B”10101”) else ’0’; score_in <= ”00000” when (clear_b = ’0’) else end behavior; adder_out when (load = ’1’) else Comparators score_out;

Bob Reese 5/95 System–23 System Design with VHDL Bob Reese 5/95 System–24 System Design with VHDL Electrical & Computer Engineering Mississippi State University Electrical & Computer Engineering Mississippi State University

VHDL File for BlackJack Control VHDL File for BlackJack Control (cont.)

begin entity bjcontrol is port (

signal clk, reset_b, card_rdy, acecard: in std_logic; –– state process to implement flag flip–flops and FSM state signal score16gt, score21gt: in std_logic; state: process(clk, reset_b) signal hit, broke, stand: out std_logic; begin signal sel: out std_logic_vector(1 downto 0); if (reset_b = ’0’) then p_state <= ”00”; signal score_clear_b, score_load: out std_logic elsif (clk’event and clk = ’1’) THEN ); end bjcontrol; Entity declaration p_state <= n_state; architecture behavior of bjcontrol is and State Assignments ace11flag_pstate <= ace11flag_nstate; broke_pstate <= broke_nstate; –– declare internal signals here stand_pstate <= stand_nstate; signal n_state, p_state : std_logic_vector(1 downto 0); card_rdy_dly <= card_rdy_sync; signal ace11flag_pstate, ace11flag_nstate: std_logic; card_rdy_sync <= card_rdy; State process to define flip– signal broke_pstate, broke_nstate: std_logic; flops for various flags and END IF; signal stand_pstate, stand_nstate: std_logic; finite state machine . end process state; signal card_rdy_dly, card_rdy_sync: std_logic; broke <= broke_pstate; –– state assignments are as follows stand <= stand_pstate; constant get_state: std_logic_vector(1 downto 0) := B”00”; constant add_state: std_logic_vector(1 downto 0) := B”01”; constant test_state: std_logic_vector(1 downto 0) := B”10”; constant use_state: std_logic_vector(1 downto 0) := B”11”; constant add_10_plus: std_logic_vector(1 downto 0) := B”00”; constant add_card: std_logic_vector(1 downto 0) := B”01”; constant add_10_minus: std_logic_vector(1 downto 0) := B”10”;

Bob Reese 5/95 System–25 System Design with VHDL Bob Reese 5/95 System–26 System Design with VHDL Electrical & Computer Engineering Mississippi State University Electrical & Computer Engineering Mississippi State University

VHDL File for BlackJack Control (cont.) VHDL File for BlackJack Control (cont.)

comb: process (p_state, ace11flag_pstate, broke_pstate, stand_pstate, when use_state => acecard, card_rdy_dly, card_rdy_sync, score16gt, score21gt) sel <= add_10_plus; begin score_load <= ’1’; sel <= B”00”; ace11flag_nstate <= ’1’; score_load <= ’0’; score_clear_b <= ’1’; n_state <= test_state; hit <= ’0’; n_state <= p_state; ace11flag_nstate <= ace11flag_pstate; when test_state => stand_nstate <= stand_pstate; broke_nstate <= broke_pstate; ’use’ and if (score16gt = ’0’) then case p_state is ’test’ states n_state <= get_state; when get_state => elsif (score21gt = ’0’) then if (card_rdy_sync = ’0’) then hit <= ’1’; stand_nstate <= ’1’; elsif (card_rdy_dly = ’0’) then n_state <= get_state; stand_nstate <= ’0’; broke_nstate <= ’0’; elsif (ace11flag_pstate = ’0’) then if (stand_pstate = ’1’ or broke_pstate = ’1’) then broke_nstate <= ’1’; score_clear_b <= ’0’; n_state <= get_state; ace11flag_nstate <= ’0’; else end if; ’get’ and ’add’ sel <= add_10_minus; n_state <= add_state; states score_load <= ’1’; end if; ace11flag_nstate <= ’0’; when add_state => end if; sel <= add_card; score_load <= ’1’; when OTHERS => n_state <= p_state; if (acecard = ’1’ and ace11flag_pstate = ’0’) then n_state <= use_state; end case; else n_state <= test_state; end process comb; end if; end behavior;

Bob Reese 5/95 System–27 System Design with VHDL Bob Reese 5/95 System–28 System Design with VHDL Electrical & Computer Engineering Mississippi State University Electrical & Computer Engineering Mississippi State University

Top Level Schematic for Dealer Blackjack Dealer Simulation

Enter ’5’ Card Enter ’8’ Card Enter ’4’ Card

Initial Score of zero Score = 5 + 0 = 5

Score = 8 + 5 = 13

Score = 13 + 4 = 17; score is > 16 so we STAND.

Bob Reese 5/95 System–29 System Design with VHDL Bob Reese 5/95 System–30 System Design with VHDL Electrical & Computer Engineering Mississippi State University Electrical & Computer Engineering Mississippi State University

Blackjack Dealer Simulation (cont.) Structural VHDL

⇒ You do not have to use a schematic to connect VHDL blocks. ou Y First card is an Next card is Next card is Final card ’Ace’. a ’2’ a ’9’ is a ’10’ can write astructural VHDL model which ties the blocks together. (facecard) ⇒ Pros:

→ When you synthesize the design all of the VHDL blocks are flattened (collapsed into one block) and it is possible that the resulting logic may be more efficient.

→ The structural VHDL code is more portable to other design systems than a schematic.

⇒ Cons:

→ Writing structural VHDL code can be more error prone than creating a schematic (very easy to misplace a net when you don’t have a ’picture’ to go by).

→ The resulting flattened netlist can be more difficult to debug.

Assertion of STAND from We will use the 13 + 9 > 21 so we break; previous game first ’Ace’ as a val- however, we have an ’Ace’ causes us to ue of ’11’. so we can treat it as a val- start new ue of ’1’; the new score is: 1 + 2 + 9 = 12. game. Score = 11 + 2 = 13

12 + 10 > 21 so we are ’BROKE’.

Bob Reese 5/95 System–31 System Design with VHDL Bob Reese 5/95 System–32 System Design with VHDL Electrical & Computer Engineering Mississippi State University Electrical & Computer Engineering Mississippi State University

Structural VHDL for BlackJack Player Structural VHDL for BlackJack Player (cont)

entity bj_struct is port ( Normal entity signal load_net, clear_net, acecard_net : std_logic; Internal signal declara- signal reset_b, clk, card_rdy : in std_logic; declaration. signal sel_net : std_logic_vector (1 downto 0); tion for those nets not signal card: in std_logic_vector(3 downto 0); signal s21gt_net, s16gt_net: std_logic; connected to external signal stand, broke,hit: out std_logic; ports. begin signal score: out std_logic_vector(4 downto 0) ); c1: bjcontrol end bj_struct; Each component used in the port map ( design is given along with clk => clk, its port map. architecture structure of bj_struct is Need a component dec- reset_b => reset_b, component bjcontrol port ( laration for each differ- card_rdy => card_rdy, ’c1’ is the component label, signal clk,reset_b: in std_logic; ’bjcontrol’ gives the compo- ent type of component acecard => acecard_net, signal card_rdy, acecard: in std_logic; used in the schematic nent type. score16gt => s16gt_net, signal score16gt, score21gt: in std_logic; score21gt => s21gt_net, signal hit, broke,stand: out std_logic; hit => hit, broke => broke, stand => stand, signal sel: out std_logic_vector(1 downto 0); sel => sel_net, signal score_clear_b: out std_logic; score_clear_b => clear_net, signal score_load: out std_logic ); score_load => load_net); end component; Only two components in c2: bjdpath this design. component bjdpath port map ( port ( clk => clk, signal clk, reset_b: in std_logic; reset_b => reset_b, signal load, clear_b: in std_logic; load => load_net, signal sel: in std_logic_vector(1 downto 0); clear_b => clear_net, signal card: in std_logic_vector(3 downto 0); sel => sel_net, signal acecard, score16gt: out std_logic; card => card, signal score21gt: out std_logic; acecard => acecard_net, signal score: out std_logic_vector(4 downto 0) ); score16gt => s16gt_net, score21gt => s21gt_net, end component; score => score );

end structure;

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Results of bj_struct Synthesis

Bob Reese 5/95 System–35 System Design with VHDL