Are Increasingly Used for High Frequency

UNIVERSITY OF CINCINNATI

May 12, 2003

I, Qinghua (George) Kang , hereby submit this as part of the requirements for the degree of: DOCTOR OF PHILOSOPHY in Electrical Engineering It is entitled Characterization of Vertical Interconnects in 3-D Monolithic Microwave Integrated Circuits (3-D MMIC)

Approved by: Altan M. Ferendeci Fred R. Beyette Joseph T. Boyd David Mast Kenneth P. Roenker

CHARACTERIZATION OF VERTICAL INTERCONNECTS IN 3-D MONOLITHIC MICROWAVE INTEGRATED CIRCUITS (3-D MMIC)

A dissertation submitted to the

Division of Research and Advanced Studies of the University of Cincinnati

in partial fulfillment of the requirements for the degree of

DOCTOR OF PHILOSOPHY

in the Department of Electrical and Computer Engineering and Computer Science of the College of Engineering

2003

Qinghua (George) Kang

M.S. University of Cincinnati, Ohio, 1998 M.E. Tianjin University, China, 1994 B.S. Tianjin University, China, 1991

Committee Chair: Dr. Altan M. Ferendeci

ABSTRACT

In this research, a unique fabrication technology to build high-aspect-ratio via interconnects in 3D MMIC multilayer integration was developed from a combination of microelectronic and traditional MEMS microfabrication technologies. Based on these techniques, a set of test structures have been successfully fabricated to facilitate the vertical interconnect characterization. Fully cured polyimide thin films possess favorable electric and mechanical properties for the 3D MMIC applications. Using quarter wavelength T-junction resonator structure, polyimide was characterized for its microwave properties. High-frequency characterization of polyimide thin films was obtained in a wide frequency range. Experimental results have shown the feasibility of this method. In order to correctly evaluate the conductor loss in thin planar transmission lines, a modified conductor loss model was derived from conventional Wheeler’s incremental inductance rule to account for the field penetration as the physical strip thickness approaches the skin depth or even smaller. The closed-form formulas or simplified equations have been developed for microstrip and stripline with wide strip cases, and for general coplanar waveguide including SCPWG line. Meanwhile, experimental results verified the validity of the modified conductor loss model in evaluating the losses in thin transmission lines. It has been shown that as the conductor thickness becomes approximately greater than four times of the skin depth, both conventional Wheeler’s rule and its modified model agree with each other very well on the conductor loss estimation. Experimental results have revealed that at RF frequency, e.g. X band (8-12 GHz), the vertical interconnection discontinuities may contribute significantly to the insertion loss and the phase change. With the advanced conductor loss models for evaluating the characteristics in the test structures, lumped-element equivalent circuit models can be derived from the via module measurement results. These models are of great practical importance in a complex circuit design.

 Qinghua (George) Kang 2003

ii ACKNOWLEDGEMENTS

I would like to express my sincere appreciation to my advisor, Dr. Altan M. Ferendeci, for his invaluable guidance, advice and support with which it is possible for me to successfully take the vast step of changing of field and jumping into a totally different and new research area. His inspirations, encouragement and knowledgeable insights guided me through the mysteries of electrical engineering and RF/microwave engineering. The experience working under his supervision in his research group at this university will have profound impact on my future career development. He is, and will be, my mentor and role model during my life time. I would also like to sincerely thank my dissertation committee members, Dr. Fred R. Beyette, Dr. Joseph T. Boyd, Dr. David Mast, Dr. Kenneth P. Roenker, and Dr. Misoon Mah (Air Force Research Laboratory, Dayton, OH) for their support and advice on this research. I am also indebted to the members of the Microwave and Millimeter Wave Electronics Lab at UC for their encouragement and assistance throughout every step of the project. Among them, I am particularly grateful to Bosui Liu, Yu Albert Wang and Jing Sun for their helpful discussion and hand-to-hand help. I would also like to thank my fellow graduate students, Jay Cheng, Oleh B. Krutko, Dr. Ming Pan and many others for their help and for bringing fun into my graduate life at this department. And my special thanks go to Mr. Ron Flenniken for his help with making the masks and using the clean- room. Finally, I would like to thank my family, my parents-in-law, my wife, Ji and my daughter, Amanda for their love and full heart support. Without their support and understanding, this would be impossible to me. And this dissertation is dedicated to them, and my mom and my late father as well. It is my parents who raised me and taught me at the very beginning of my learning experience to become a positive figure and useful member in the society of human beings.

iii LIST OF RELATED PUBLICATIONS

A. M. Ferendeci, Q. Kang, B. Liu and M. Mah, “Characterization of Monolithically Processed Vertical Interconnects for Microwave 3DIC,” Proceedings of IPACK ’01, The pacific Rim/ASME International Electronic Packaging, paper number: IPACK2001-15777, Kauai, Hawaii, July 8-13, 2001.

Altan M. Ferendeci, Peng Xu, Bosui Liu, Yu Albert Wang, George Kang, and Misoon Mah, “3D-IC Hybrid Power Amplifier for Vertically Interconnected Multilayer Phased Array Antenna Module”, 2001 Government Microcircuit Applications Conference (GOMAC), March, 2001.

Yu Albert Wang, Qinghua Kang, Bosui Liu, Altan M. Ferendeci, and Misoon Mah, “Interlayer MEMS RF Switch for 3D MMICs", IEEE MTT-S Digest, Vol.2, pp. 1245- 1248, June 2000.

Bosui Liu, Yu Albert Wang, George Kang, Altan M. Ferendeci, and Misoon Mah, “Vertically Interconnected 3D Module for Conformal Phased Array Antennas”, IEEE International Conference on Phased Array Systems and Technology, Proceedings 2000, pp. 49-52, May 2000.

Altan M. Ferendeci, Bosui Liu, George Kang and Misoon Mah, "Vertically Interconnected Multilayer Microwave Circuits", 2000 Government Microcircuit Applications Conference (GOMAC), March 2000.

Bosui Liu, Albert Wang, George Kang, Peng Xu, Altan M. Ferendeci and Misoon Mah, "Micromachined 3D Multilayer Monolithic Microwave Circuits", NASA Ideas Seminar - Technology Presentations, Cleveland, OH, Nov. 1999.

iv Q. Kang and A. M. Ferendeci, “Characterization of Vertical Interconnects in 3-D System in a Package,” Proceedings of IPACK 2003, The pacific Rim/ASME International Electronic Packaging, paper number: IPACK2003-35247, Maui, Hawaii, July 6-11, 2003.

v TABLE OF CONTENTS

ABSTRACT ……………………………………………………………………………..I ACKNOWLEDGEMENTS ...... III LIST OF RELATED PUBLICATIONS ...... IV TABLE OF CONTENTS ...... VI LIST OF TABLES ...... VIII LIST OF FIGURES ...... IX LIST OF SYMBOLS ...... XIII CHAPTER 1 INTRODUCTION...... 1 1.1. THREE-DIMENSIONAL INTEGRATION OF MICROWAVE CIRCUITS ...... 1 1.2. HIGH-FREQUENCY CHARACTERIZATION OF DIELECTRIC MATERIALS ...... 10 1.3. CONDUCTOR LOSS IN MICROWAVE PLANAR AND 3D CIRCUITS ...... 11 CHAPTER 2 POLYIMIDE FOR 3-D MMIC APPLICATIONS...... 13 2.1. POLYIMIDE CHEMISTRY ...... 13 2.1.1. Polyimide Structures and Synthesis...... 13 2.1.2. Polyimide Properties ...... 15 2.2. METAL-POLYIMIDE INTERFACIAL PHENOMENA...... 17 2.2.1. Chromium-Polyimide Interface ...... 18 2.2.2. Copper-Polyimide Interface...... 20 2.3. POLYIMIDE THIN FILM PROCESSING OVERVIEW ...... 21 2.3.1. Spin Coating...... 22 2.3.2. Adhesion Promoters...... 23 2.3.3. Polyimide Panarization ...... 24 2.3.4. Patterning of Polyimide Thin Films...... 25 2.4. PROCESSING OF POLYIMIDE THIN FILMS...... 29 2.4.1. General Processing Guidelines ...... 29 2.4.2. Processing Experiments and Results ...... 31 2.5. SUMMARY...... 37 CHAPTER 3 CHARACTERIZATION OF THIN FILM DIELECTRICS ...... 38 3.1. MICROSTRIP LINE CHARACTERISTICS ...... 38 3.1.1. Characteristic Impedance and Effective Dielectric Constant ...... 39 3.1.2. Effect of Strip Thickness...... 41 3.1.3. Dispersion in Microstrip Line...... 41 3.1.4. Losses in Microstrip Line...... 44 3.1.5. Quality Factor...... 45 3.1.6. Discontinuities Associated with T-resonator Measurement ...... 46 3.2. T-PATTERN MICROSTRIP RESONATOR FOR THIN FILM SUBSTRATE CHARACTERIZATION ...... 48

vi 3.2.1. General Procedure...... 49 3.2.2. Fabrication of Test Structures ...... 50 3.3. THIN FILM CHARACTERIZATION RESULTS AND DISCUSSIONS...... 54 3.3.1. Conductor Loss in Thin Microstrip ...... 54 3.3.2. Characterization Results...... 58 3.3.3. Error Analysis for εr Measurement...... 65 3.4. SUMMARY...... 68 CHAPTER 4 FEM SIMULATIONS OF 3-D MMIC INTERCONNECTS...... 70 4.1. MAXWELL’S EQUATIONS ...... 70 4.2. FEM FORMULATION FOR ELECTROMAGNETICS...... 72 4.3. FEM SIMULATIONS OF 3-D INTERCONNECTS ...... 74 4.3.1. Sidewall Confinement Effects ...... 75 4.3.2. Via and Thruhole Shape Effects...... 78 4.3.3. Stripline Connecting Angle Effects ...... 81 4.4. EQUIVALENT CIRCUITS FOR IDEAL VIAS...... 82 4.5. DESIGN CONSIDERATIONS...... 88 CHAPTER 5 FABRICATION AND CHARACTERIZATION OF INTERCONNECTED 3-D MMIC SAMPLE CIRCUITS...... 91 5.1. METAL ELECTRODEPOSITION...... 91 5.2. FABRICATION OF VERTICAL INTERCONNECTS...... 94 5.3. CHARACTERIZATION OF VERTICAL INTERCONNECTS ...... 107 5.3.1. Conductor Loss in Thin Stripline and SCPWG ...... 107 5.3.2. Interconnect Characterization Results ...... 119 5.4. SUMMARY...... 128 CHAPTER 6 CONCLUSIONS AND RECOMMENDATIONS ...... 130 6.1. CONCLUSIONS...... 130 6.2. RECOMMENDATIONS FOR FUTURE WORK ...... 133 REFERENCES...... 136 APPENDICES...... 144 TM APPENDIX A DERIVATION OF EQ. 3.40 USING MATHEMATICA ...... 144 TM APPENDIX B MATHEMATICA CALCULATION OF CONDUCTOR LOSS IN THIN MICROSTRIP...... 146 APPENDIX C FOUR-POINT PROBE MEASUREMENT OF METAL CONDUCTIVITY ...... 148 APPENDIX D MATLAB PROGRAM FOR THIN FILM CHARACTERIZATION...... 149 APPENDIX E PROCEDURE FOR EXTRACTING EQUIVALENT CIRCUIT USING HP LIBRA UNIX VERSION (V6.1) ...... 153 APPENDIX F CALCULATING CONDUCTOR LOSS IN THIN STRIPLINE USING TM MATHEMATICA ...... 156 APPENDIX G CALCULATING CONDUCTOR LOSS IN THIN SCPWG LINE USING TM MATHEMATICA ...... 160

vii LIST OF TABLES

Table 2-1 Typical chemical and electrical properties for commonly used polyimides .... 17 Table 2-2 Peel strength of polyimide on metal substrates ...... 18 Table 2-3 Typical etch rates of common microelectronic materials [ 50]...... 28 Table 2-4 Processing details for the deposition of PI1111 and PI2611 films...... 32 Table 2-5 FilmetricTM measurements for PI1111 films ...... 33 Table 3-1 A typical design of T-pattern structures at different primary resonances ...... 58 Table 4-1 Common Numerical Methods for Microwave engineering [80]...... 74 Table 4-2 Results of different via-thruhole combinations ...... 79 Table 4-3 Equivalent circuit components for different viahole modules ...... 84 Table 4-4 Equivalent circuit components for different connecting angles at frequency 8- 12 GHz...... 87 Table 5-1 Physical dimensions of vertical interconnect test structures ...... 122 Table 5-2 Via equivalent circuit components for SCPWG and stripline test structures 125

viii LIST OF FIGURES

Figure 1.1 3D MMIC passive transmitter module for phased-array systems...... 3 Figure 1.2. Size reduction by using LTCC circuit integration...... 4 Figure 1.3. A typical LTCC fabrication process...... 5 Figure 1.4. A 2.4-GHz radio front end implemented with LTCC ...... 6 Figure 1.5. Multiplanar coplanar stripline interconnect fabricated by NASA GRC ...... 7 Figure 1.6. 2-D and 3-D hybrid vertical integration of power combining network using Si micromachining developed at University of Michigan ...... 8 Figure 2.1 Chemical structure of the polyimide...... 14 Figure 2.2 Imidization of polyimide structure...... 14 Figure 2.3 Pyromellitic dianhydride-oxydianiline (PMDA-ODA) building block...... 18 Figure 2.4 (a) Lowest unoccupied level of the PMDA fragment and Cr 3dxy orbital (occupied). The orbitals are shown at a large separation (noninteracting). (b) Occupied orbital of the complex that occurs as a result of the interaction of the unoccupied a2 orbital and filled Cr 3dxy orbital. For orbitals, the opposite phases are indicated by + or – , and the filled and empty orbitals are shaded and unshaded, respectively...... 19 Figure 2.5 Comparison of the process steps involved in patterning polyimide by wet etching, dry etching, and photopatterning of photosensitive polyimide...... 26 Figure 2.6 FilmetricTM measurement points on 2-inch wafer (thick film in shadowed area)...... 34 Figure 2.7 PI1111 polyimide film thickness vs. deposition layers...... 34 Figure 2.8 SEM micrograph of a via hole 24 µm in diameter etched in 11 µm thick PI1111 film using CF4/O2 RIE process, gold as masking material...... 35 Figure 2.9 Effect of CF4 flow rate on the RIE polyimide film (PI1111) etching rate ..... 36 Figure 2.10 Effect of temperature on the RIE etch rate of polyimide films (PI2611)..... 37 Figure 3.1 Microstrip configuration...... 39 Figure 3.2 Microstrip open-end discontinuity and its equivalent representations...... 47 Figure 3.3 Microstrip T-junction and its equivalent circuit...... 47 Figure 3.4 SEM micrograph of microstrip T-pattern fabricated with polyimide substrate ...... 53 Figure 3.5 Field penetration in microstrip ...... 54 Figure 3.6 Microstrip line conductor loss in dB/cm at 10 GHz versus t/δs (metal thickness/skin depth)...... 57 Figure 3.7 Conductor loss error calculated between Wheeler’s rule and its modified model...... 57 Figure 3.8 Frequency response of a quarter-wavelength T-pattern resonant structure with lower primary resonance and its harmonics...... 59 Figure 3.9 Expanded measurement of the resonance and 3dB bandwidth ...... 59 Figure 3.10 Measured dielectric constant for PI2611 thin film substrates...... 61 Figure 3.11 Measured loss tangent for PI2611 thin film substrates ...... 62 Figure 3.12 Comparison of PI2611 polyimide thin film loss tangent results with or without conductor loss correction and those from literature [67] ...... 63

ix Figure 3.13 Conductor loss varying with frequency in the thin microstrip line with the 7 strip W=76.5 µm, t=1.4 µm on the PI2611 thin film h =35 µm (σc=2.67x10 S/m) 64 Figure 3.14 Conductor loss varying with t/skin-depth ratio in the thin microstrip line 7 with the strip W=76.5 µm, t=1.4 µm on the PI2611 thin film h =35 µm (σc=2.67x10 S/m)...... 65 Figure 4.1 Tetrahedral element with denoted nodes (1 to 4) and edges (E1 to E6). ri1 and ri2 are node vectors and r is an arbitrary vector which lies in the tetrahedron...... 73 Figure 4.2 Geometry of the post vertically connecting stripline to stripline transmission lines. Side walls (trenches) are placed along the sides. Stripline-microstrip-CPWG transitions were designed for measurement ports...... 75 Figure 4.3 Effects of the confining trenches on the electrical field around via-holes: (a) with trenches, (b) without trenches...... 77 Figure 4.4 Sidewall confinement effects on the viahole (a) insertion loss and (b) return loss...... 78 Figure 4.5 Loss factors for the confined and unconfined viaholes...... 78 Figure 4.6 Insertion and return losses for different via-thruhole combinations...... 79 Figure 4.7 Surface current distributions on (a) the via surface only, (b) besides the via, on the strips and separate ground plane...... 80 Figure 4.8 The via modules with different connecting angles...... 81 Figure 4.9 Insertion and return losses for the via modules with different connecting angles...... 82 Figure 4.10 (a) Geometry of the post connecting vertically stripline to stripline transmission lines. (b) equivalent circuit of a vertical post...... 83 Figure 4.11 Scattering parameters of cyl-cirthru via-hole from FEM simulation and equivalent circuit...... 84 Figure 4.12 Another equivalent circuit (a) and the transformation between T- and π-type circuits (b) ...... 85 Figure 4.13 Vertical interconnect through a ground plane of finite thickness and its equivalent circuit...... 85 Figure 4.14 Scattering parameters of cyl-cirthru viahole (90° connecting angle) from FEM simulation and equivalent circuit...... 86 Figure 4.15 Scattering parameters of cyl-cirthru viahole (0° connecting angle) from FEM simulation and equivalent circuit...... 87 Figure 4.16 Equivalent circuit components (total inductance and capacitance) of cyl- cirthru viahole (90° connecting angle) as a function of the frequency...... 87 Figure 5.1 Generalized plot of normalized current display (I/Ilim) as a function of current density. Also shown are electrodeposit characteristics that may be encountered at different current densities. Ilim is the diffusion limiting current...... 92 Figure 5.2 Fabrication procedures for 3D vertical interconnects ...... 95 Figure 5.3 AZ4620 soft baking procedure...... 97 Figure 5.4 SEM picture of a plated copper post on strip after insulating AZ4620 is removed...... 98 Figure 5.5 SEM picture of plated posts covered by polyimide...... 99 Figure 5.6 SEM picture of an exposed post top right after polishing...... 100 Figure 5.7 SEM picture of polished posts after deconstructive removing of polyimide101 Figure 5.8 Enlarged SEM picture of an polished post...... 101

x Figure 5.9 A photograph of the thruhole opened around the lower half of the via post 102 Figure 5.10 A SEM picture of plated post sitting on its first half portion with square thruhole ...... 103 Figure 5.11 A SEM picture of plated post sitting on its first half portion with circular thruhole ...... 103 Figure 5.12 SEM picture of a polished post of full height with circular thruhole after deconstructive removing of polyimide ...... 104 Figure 5.13 SEM picture of a polished post of full height with square thruhole after deconstructive removing of polyimide ...... 104 Figure 5.14 SEM picture of the measurement port at the shallow side ...... 106 Figure 5.15 SEM picture of the measurement port at the deep side...... 106 Figure 5.16 Field penetration in stripline...... 108 Figure 5.17 Stripline conductor loss in dB/cm versus frequency and t (metal thickness) from Wheeler’s rule for W=24 µm, b=44 µm, εr=3.3 and σ=3x107 S/m (deposited metal) ...... 111 Figure 5.18 Stripline conductor loss in dB/cm versus frequency and t (metal thickness) from modified method for W=24 µm, b=44 µm, εr=3.3 and σ=3x107 S/m (deposited metal) ...... 111 Figure 5.19 Stripline attenuation expressed as S21 in dB versus frequency with conductor loss incorporated for W=22 µm, b=44 µm, εr=3.3, t=0.85 µm and σ=3x107 S/m (deposited metal)...... 112 Figure 5.20 Conventional coplanar waveguide (CPW) ...... 112 Figure 5.21 Shielded coplanar waveguide with ground planes [96] ...... 113 Figure 5.22 Conformal transformation of the first quadrant of CPW conductor backing and upper shielding into parallel plate geometry: (a) Z-plane, (b) T-plane, and (c) W-plane [ 96] ...... 113 Figure 5.23 SCPWG line conductor loss in dB/cm versus frequency and t (metal 7 thickness) from Wheeler’s rule for h1=h2=22 µm, εr=3.3 and σ=3x10 S/m (deposited metal)...... 117 Figure 5.24 SCPWG line conductor loss in dB/cm versus frequency and t (metal 7 thickness) from modified method for h1=h2=22 µm, εr=3.3 and σ=3x10 S/m (deposited metal)...... 118 Figure 5.25 SCPWG line attenuation expressed as S21 in dB versus frequency with 7 conductor loss incorporated for h1=h2=22 µm, εr=3.3, t=0.85 µm and σ=3x10 S/m (deposited metal)...... 118 Figure 5.26 CPW ports for interconnect characterization and the probe pads [91] ...... 119 Figure 5.27 The CPW probe pads grounding effect on thin stripline insertion loss measurements...... 120 Figure 5.28 LIBRA model for simulating CPW probe pads grounding effect...... 121 Figure 5.29 A schematic model of the test structure for interconnect characterization 122 Figure 5.30 A lossy lumped-element equivalent circuit for a lossy vertical via...... 122 Figure 5.31 Experimental and simulation results for the SCPWG test structure vertically connected by vias...... 123 Figure 5.32 LIBRA model of the test structure with lumped-element equivalent circuit for the via ...... 124

xi Figure 5.33 Experimental and simulation results for the stripline test structure vertically connected by via ...... 125 Figure 5.34 LIBRA model of the via lumped-element equivalent circuit with resistive loss ...... 126 Figure 5.35 Phase difference for the via in ideal simulation and test structure...... 126 Figure 5.36 A cross-section view of the stripline test structure connected by two vias 127 Figure 5.37 LIBRA model for the stripline test structure with two vertical vias ...... 127 Figure 5.38 Experimental and simulation results for the stripline test structure with two vias ...... 128 Figure 6.1 (a) CPW-to-stripline transition and its electric field, (b) electric field of CPW with ground plane and (c) electric field of stripline...... 134

xii LIST OF SYMBOLS

a Activation energy a Coplanar waveguide center strip half width

ae Effective a due to metallization thickness b Stripline substrate thickness b Distance between coplanar waveguide center and lateral ground plane edge be Effective b due to metallization thickness B Magnetic flux density vector

BT Susceptance BW Fractional bandwidth c Speed of light

C, Ce Capacitance

Cg Modification coefficient for ground plane effect in Wheeler’s rule

Cg Capacitance due to center ground plane

Ch,W Error contribution coefficient due to substrate height and strip width error

Coc Excess capacitance due to open end

Ct Modification coefficient for strip lateral side effect in Wheeler’s rule

Cw Modification coefficient for strip large side effect in Wheeler’s rule d Via diameter D Electric flux density vector DOP Degree of planarization E Electric field vector f Frequency

f0 Center frequency

f1 Lower side frequency

f2 Higher side frequency

fd Cut-off frequency of dispersion

fp Cut-off frequency of first higher order parallel plate mode in T-junction

xiii fT Cut-off frequency of the lowest order TE mode

Fz Form factor of Z0 h Substrate thickness h1 Distance between coplanar waveguide center plane and upper shielding h2 Coplanar waveguide circuit substrate thickness H Magnetic field vector H Via height

H1 Magnetic field at strip lower side

H2 Magnetic field at strip upper side k, k0 Wave number j Imaginary symbol J Electric current density

Ji Source current l Stub length L Length

L. Le Inductance

LA Insertion loss

Ploss Power loss q Coplanar waveguide filling factor Q Quality factor

Q0 Unloaded quality factor

Qc Quality factor due to conductor loss

Qd Quality factor due to dielectric loss

Qr Quality factor due to radiation loss

QL Loaded quality factor r Etching rate

r0 Etching rate constant R Gas constant, 8.314 J/Kmole R Conductor impedance per unit length

xiv R Resistor

Reff Modified conductor impedance per unit length

Rs Conductor surface resistivity

Rstrip Strip conductor impedance per unit length S Coplanar waveguide slot width

Se Effective S due to metallization thickness t Metallization or film thickness t Time tf Feature final step height tg Ground plane metal thickness

ti Feature initial height tanδ Loss tangent of the dielectric material T Absolute temperature

Tg Polymer glass transition temperature

vp Phase velocity W Strip width

We Effective W due to metallization thickness

We(f) Dispersion in effective W

Y0, Ye Admittance

Z0 Characteristic impedance a Z0 Characteristic impedance with air as dielectric

Z0(f) Frequency-dependent characteristic impedance

Ze Characteristic impedance for lumped-element circuit

Zs Metal wave impedance

αc Attenuation constant due to conductor loss ’ αc Conductor attenuation with surface roughness correction

αd Attenuation constant due to dielectric loss

αr Attenuation constant due to radiation loss

xv αT Total attenuation constant β Propagation constant

βe Lossless propagation constant γ Complex propagation constant

γc Metal propagation constant

δn Field penetration depth, half of the skin depth

δs Skin depth ∆ RMS surface roughness ∆l Excess length of open end

ε Permittivity

ε0 Permittivity of free space

εc Complex permittivity

εe, εre Relative effective dielectric constant

εe(f) Dispersion of εe

εr Substrate dielectric constant

εr0 Coplanar waveguide upper half filling dielectric constant η Free space wave impedance, 120π ohm

λ Wave length

λ0 Free space wave length

λg Guided wave length

µ Permeability

µ0 Permeability of free space ρ Electric charge density

ρc Resistivity of strip conductor σ Conductivity of dielectric substrate, electric conductivity

σc Conductivity of conductor ω Angular frequency Γ Reflection coefficient

xvi Chapter 1 Introduction

In today’s wireless and mobile communications systems, the high-speed, high- performance and wideband transmission of communication signals are achieved by means of miniaturized large-scale integrated circuits. 2D layout of circuit elements has reached a highly mature state but the developments to advance the technology reached a saturation stage. The next step is to move the high-density circuitry from two- dimensional planar design to three-dimensional, multilayer technology. Monolithic microwave integrated circuits (MMIC) have become the dominant microwave circuit technology, which incorporates solid-state devices and RF components in a densely packaged configuration. Through integration of analog and digital circuits on one single chip, the "system on a chip" concept can be realized with considerable size and cost reduction [1]. This technological trend in the communication systems arena poses not only interesting, but also challenging issues. It also brings in revolutionary changes in circuit design, fabrication, and implementation. Emerging military, space, and commercial communications systems, as well as unique military applications in radar and missile seekers, are placing a high premium on low-cost, small, light–weight RF electronic components, while at the same time increasing demands for higher functionality. The ability to integrate in three dimensions can increase the density of circuit integration, reduce costs, and add performance that cannot be achieved in conventional planar circuit architecture.

1.1. Three-Dimensional Integration of Microwave Circuits Three-dimensional monolithic microwave integrated circuits (3-D MMICs) have the potential for providing an overarching circuit integration technology that can significantly reduce the size, weight, and cost of microwave and millimeter-wave components. The capability to integrate diverse substrate technologies opens the door for real multifunction chips, combining analog, digital, RF, and optoelectronic functions.

1 This natural approach to three-dimensional (3-D) vertical integration can not only provide higher density circuits, but also by freeing RF circuit design from the limitations of the two-dimensional (2-D) layout, can reach levels of performance not possible in a planar geometry. A successful example of the highly developed 2D integration is the design of present day microprocessors and has resulted in a dramatic reduction of chip size and increase in operation speed [2]. The layout and integration of elements have reached the maximum possible stage. Circuit miniaturization can further be easily achieved by means of three-dimensional integration where circuits are stacked in vertical dimensions. Multilevel integration results in circuits with multiple power and ground planes and with planar transmission line transitioning between different layers using plated-through vertical interconnects. This technology is increasingly used for high frequency, microwave, and millimeter applications because of a reduction in parasitics and module size [3]. Figure 1.1 shows a 3D MMIC passive transmitter unit developed in Microwave and Millimeter Wave Electronics Laboratory at the University of Cincinnati for the application in phased-array antenna systems. Such a system requires many of transmit/receive (T/R) modules conformally placed on any arbitrary physical surface. In the 1980s, great effort was placed on the development of planar monolithic microwave integrated circuits (MMIC) that combine many functions on a single circuit while providing high performance and low cost. Communications and radar systems benefited from these advances through steady decreases in both cost and weight. However, it has become clear that the performance advantages inherent in MMICs cannot be realized by conventional packaging at the system level. Consequently, many new packaging technologies have evolved at the chip level, such as ball-grid arrays (BGA) and multichip modules (MCM), which are made of ceramic materials, thin films over silicon (also known as high-density integration or HDI), or printed wiring board. Their main features are that they combine RF distributed networks, biasing lines, and multiple MMICs in a package. Despite these advances, MCM technology has not fully realized its expectations for low cost, very small size, high-performance systems operating at higher frequencies. Various loss mechanisms associated with interconnects and passive

2 components, coupling between circuits, and resonances within the package severely degrade the system performance.

Figure 1.1 3D MMIC passive transmitter module for phased-array systems

As the demands in RF and microwave circuit integration increase, several new technological approaches, other than the novel technology which is developed in this research, have also been under the development to achieve multilayer circuit integration and packaging. One of the important technologies widely used for the integrating passives, particularly for RF functional passive modules, is low temperature cofired ceramics (LTCC). With the added new design dimension in the z-direction provided by LTCC, a lot of passive components can be stacked and integrated in 3D structures with improved performance. By implementing this extra degree of integration, conventional

3 circuits can be shrunk to a small volume of space with reduced size, as shown in Figure 1.2 [4].

Figure 1.2. Size reduction by using LTCC circuit integration

Unlike other technologies, such as CMOS process, fabrication of LTCC is a parallel process. Each layer is fabricated separately and independent of each other. Individual layer can then be examined and inspected. If failure is found, only the defective layer, instead of the whole structure, need to be fabricated again. High yield, reduction in cost and timesaving can be achieved. A typical LTCC process is illustrated in Figure 1.3 [5]. Generally the LTCC circuit fabrication process can be characterized with multiple complementary steps. These are green tape preparation, formation of via holes, via filling, screen printing and high resolution lines, stacking and collating green tapes, laminating, co-firing at lower temperature (relative to high temperature co-fired ceramics at temperature above 1000 ºC), and normally the post-firing process to trim the circuit and to mount discrete components.

Figure 1.3. A typical LTCC fabrication process

Even though the co-firing temperature is lower than that of HTCC, it is still about 850 ºC which is high enough to destroy most of the active devices made from semiconductors if they are co-fired in this process. To realize a multichip module (MCM), MMICs, chip devices, and other SMD components have to be integrated in the LTCC environment. Several techniques are suitable for use: bonding, flip-chip, soldering or pasting, buried in cavities or mounted on the top of the substrate. In this sense, most of the LTCC circuits are still a combination of integrated circuits in a module or package. Figure 1.4 shows an LTCC-based radio front-end module which integrates the CMOS transceiver MMICs with LTCC embedded passive components and a loop antenna [6]. The MMIC components, such as LNA (low noise amplifier), PA (power amplifier) and mixer, are surface-mounted on the top layer connected by vias to embedded components. Examples of LTCC applications in wireless communications include the compact low-pass and band-pass filters in [7, 8] and the LTCC duplexers in [9, 10]. It has been reported recently that a RF front-end module (FEM), integrating over

5 50 components in a package with a overall size of only 6.7 x 5.5 x 1.8 mm3, for GSM (Global System for Mobile Communications) triple-band mobile phones has been built based on LTCC technology [11].

Figure 1.4. A 2.4-GHz radio front end implemented with LTCC

Another technological means to realize 3D integration of RF and microwave circuits is using Si micromachining technology [12]. Silicon micromachined microwave and millimeter-wave circuit integration provides a comprehensive technique to integrate a very large degree of functionality on a single substrate with high density and at a relatively low cost. The micromachined circuit is essentially self-packaged, without the need for external carriers or external hermetic packaging. Because the components are all shielded by the micromachined structure, there is no significant electromagnetic coupling and no spurious resonances caused by the package. The vertically layered structure of the micromachined circuit presents an excellent opportunity for 3D integration, resulting in the potential for substantial reduction in size. The ability to flip-chip active components based on diverse substrate material technologies, such as millimeter-wave power

6 amplifier circuits and optoelectronic circuits, into the micromachined structure may provide the potential to integrate high-level multifunctional systems into a single planar technology. Micromachined passive components have been developed that replace large off-chip components that formerly required expensive, bulky, and heavy hybrid circuit integration [12-15]. As a requirement of all three-dimensional integration and on-wafer packaging, multilayer interconnects are critical to realize a vertical integration. Figure 1.5 shows a multilayer coplanar stripline interconnect achieved by using Si micromachining [12].

Figure 1.5. Multiplanar coplanar stripline interconnect fabricated by NASA GRC

Based on the specific circuit integration requirements, the interconnection can be realized by a combination of 2D and 3D hybrid vertical integration as shown in Figure 1.6, which is an integrated power combining network [12]. Even though silicon micromachining has demonstrated a great potential for 3-D integration of RF and microwave components, usually for high frequency applications the

7 transmission loss associated with the RF components is prohibitive to implement the lumped and distributed elements, especially in low-resistivity silicon wafers. The high co-firing temperature in LTCC technology prevents most of the active components from being integrated in a simple package. Since Si micromachining requires mostly MEMS process technologies, this technology is better suited for higher frequency applications. In view of the limitations of the LTTC and the Si-micromaching technologies, there is need for a better 3D-IC technology which can overcome the difficulties of the above two technologies. This is one of the motivations of this research to develop an alternative and advanced technology to achieve 3D multilayer circuit integration.

Figure 1.6. 2-D and 3-D hybrid vertical integration of power combining network using Si micromachining developed at University of Michigan

The use of microelectromechanical systems (MEMS) technology for microwave applications provides a unique, comprehensive technique to integrate a very large degree of functionality on a single substrate with extremely high density and a relatively low cost. In addition, RF MEMS technology has widespread applications in phased arrays and reconfigurable apertures for defense and telecommunication systems, switching networks for satellite communications, and single-pole-N-throw switches for wireless

8 applications (portable units and base stations) [16,17]. It promises to solve some of the most vexing problems still confronting the field of high-frequency technology for today’s wireless and mobile communications systems. In this study, a novel RF MEMS integration technology is developed to achieve the three-dimensional integration of microwave and millimeter-wave components with improved performance using multilayer vertical interconnects. For the multilayer packaging of microwave or millimeter wave circuits, vertical interconnects play an important role in interconnecting circuits of different levels. This allows the planar circuits to be stacked vertically in three dimensions (3D). So the performance of vertical interconnects becomes an important design issue in MMIC packaging. As frequency increases, the propagation characteristics of vertical interconnects have an ever stronger effect on the performance of the interconnected electronic circuits. Recently, considerable research efforts have been directed to address these issues [18-23]. For the vertical interconnects, there are two major concerns which affect the performance of interconnected layers: (1) low insertion and return losses, and (2) field and electrical interference with the system elements. The latter is more important in communication applications. To achieve the isolation of high-density packed RF circuits like the phased-array antenna system, confinement walls or posts can be placed around the vertical interconnects and the transmission lines to shield the interference. Studies have shown the shielding between the planar transmission lines can provide good isolation of interference between them, which means closer packaging density is possible [24, 25]. As stated early, this research develops a novel packaging technology based on the advanced RF MEMS technology to integrate planar RF components into 3-D multilayer module using microfabricated vertical interconnects. To explore the effects of three dimensional integration, first, a numerical commercially available full-wave solver, Ansoft HFSS, will be used to solve the Maxwell equations with proper boundary conditions to simulate the 3D interconnects in the ideal environments. And equivalent circuits were extracted from the simulation results. The vertical integration of RF test components, for simplicity which are various transmission lines, is achieved by an

9 innovative MEMS-based processing of vertical interconnection vias. More thorough experimental characterization has been conducted on the physical test structures. Based on these results, more accurate and real physical equivalent models are obtained. Understanding of the simulated solutions and experimental results, and the resulting equivalent circuits will provide design guidelines for the successful implementation of 3D-IC circuit technology. The equivalent circuit models developed in this study can be incorporated into circuit simulation software for the design of vertical interconnects in a complicated 3D integration of RF circuitry. The microfabrication technology developed for building the vertical via test structures can also be utilized for the processing of mass production of 3D MMICs.

1.2. High-Frequency Characterization of Dielectric Materials As applications for microwave circuitry expand, particularly in portable wireless communications systems and as digital integrated circuit speeds continue to increase, high frequency data on material properties (dielectric constant, loss tangent and attenuation) become very important for the circuit design. Many of the materials used in electronic packaging have not been characterized for their high frequency performance over the broad range that is of interest to design engineers. Furthermore, new materials are continually being developed that need to be characterized. Typically, low frequency data is available based on capacitor measurements using inductance-capacitance- resistance (LCR) meters or impedance analyzers at frequencies up to approximately 100 MHz. High frequency data is often obtained with bulk material measurements in single- frequency resonant cavities. And this method is not quite feasible for thin-film substrate characterization. In order to obtain the broader high frequency data, a test method utilizing a microstrip T-pattern resonator was developed which addressed the aforementioned limitations of standard test methods. With the development of MMIC technology, on- wafer characterization of thin film substrates for the broader high frequency applications is critical for a successful design. In this research microstrip T-pattern resonator circuit is employed for the polyimide thin film substrate characterization, which is applicable to characterizing any thin film substrates.

1.3. Conductor Loss in Microwave Planar and 3D Circuits In the 3D integration of MMICs, radiation loss from the physical structures of certain circuits can be easily eliminated by packaging the components in the nature of enclosed structures, mostly between two ground planes. Therefore the losses in these circuits are composed of dielectric loss from the substrate and conductor loss from the metals. In most cases, conductor loss is dominant and the dielectric loss is relatively small when good quality substrates are used. Conductor loss in transmission lines is due to the presence of imperfect conductors and the penetration of fields into the conductors. The magnitudes of the fields and current decay exponentially with penetration into the conductor, by an amount of 1/e in a distance of one skin depth. Normally the thickness of the conductors is greater than several times of the skin depth. In this case, a useful technique for the practical evaluation of attenuation due to conductor loss for TEM or quasi-TEM lines is the “Wheeler incremental inductance rule” [26]. Conductor loss calculation based on the incremental inductance rule is not valid if conductor thickness becomes very thin and on the order of the skin depth, such as in monolithic microwave integrated circuits. Transmission lines, such as microstrip line, stripline and coplanar waveguide, are widely used in microwave and RF integrated circuits due to their superior compatibility to the circuit environment for easy integration and manufacturing. In 3D multilayer integration of RF and microwave components, stripline and shielded coplanar waveguide find more applications because of the nature of their structure favoring multilayer interconnection. However, microstrip line can still be used for the top level planar structure, such as matching networks, planar antennas and various other RF components. High speed and high density integration in modern integrated circuits, especially in monolithic microwave integrated circuits, demand very thin metallization lines in the processing due to cost and other manufacturing considerations. In such thin metal lines, the conductor loss becomes dominant and limits the performance of the circuits. Therefore, an accurate calculation of the conductor loss is needed for planning the power budget at the system-level point of view beforehand.

11 In this research, the metallization thickness for the dielectric characterization microstrip-T resonators and the multilayer interconnection transmission lines is normally in the order of magnitude close to the skin-depth in the specific frequency ranges. Thus the conventional formulas based on the Wheeler’s rule for the calculation of conductor loss can not provide accurate evaluation of the losses. In order to account for the skin- effect in the loss calculation in microstrip transmission line case, several models have been proposed in the literature [27-29]. But no ready models can be used to evaluate the conductor losses in the 3D nature of transmission lines such as stripline and shielded coplanar waveguide. A substantial part of the effort has been devoted to develop and evaluate the conductor loss models for the 3D multilayer integration. As a result, these models facilitate the extraction of equivalent circuit models for the vertical vias from the experimental test structures.

Chapter 2 Polyimide for 3-D MMIC Applications

To achieve the 3-D dimensional packaging of microwave integrated circuits (MIC's), the choice of polymeric thin films as interdielectric for these multilayer structures is very important. A good polymer interdielectric material should have high process compatibility and good electric characteristics. In general, the key requirements for an ideal interdielectric polymeric thin film are as follows: low dielectric constant, good thermal stability, low water absorption, good adhesion (metal and self), low coefficient of thermal expansion (CTE), good planarization, spin or spray coatability, dry etch capability, and laser ablatability [30]. In practice, a compromise is often made between the process compatibility and the dielectric properties. Polyimide has been widely used as a dielectric material in microelectronic applications because it has high thermal stability, excellent metal/polymer adhesion, and the ability to tailor physical properties through appropriate molecular engineering. Polyimides, through a two-step process which consists of solution coating of polyimide precursor poly (amic acid) and subsequent curing, can be deposited as thin films by spin or spray coating and, therefore, are suitable for many microelectronic applications.

2.1. Polyimide Chemistry 2.1.1. Polyimide Structures and Synthesis Polyimides are long-chain organic polymers characterized by the presence of the phthalimide structure (structure A as shown Figure 2.1) in the polymer backbone [31]. As shown in Figure 2.1, this backbone can be more generally illustrated as a detailed structure B, where R and R’ are mainly aromatic groups which are responsible for the high thermal stability of the polymers. The differences between the R and R’ groups determine different polyimides with different physical, chemical and electrical properties.

13 O O O C C C N N R N R’

C C C O O O n A B

Figure 2.1 Chemical structure of the polyimide.

In their final polymerized stages, polyimides are intractable, insoluble, and lack ease of processibility. However, by using a two-step process that involves the polymerization of a soluble polyimide precursor called poly(amic acid) that is thermally converted to the polyimide, thin films of polyimides can be made for a variety of applications. The conversion of soluble poly(amic acid) to polyimide is generally accomplished by heating and is called curing or imidization. The curing reaction polymerizes the precursor molecules when the cyclization occurs and H2O molecules are released and eliminated, as shown in the Figure 2.2.

O O HOOC COOH C C

-H2O N NR’ ∆ HNOC CONHR’ C C n O O n C D

Figure 2.2 Imidization of polyimide structure.

The imidization generally begins at a temperature great than 150°C, and complete imidization occurs at a temperature great than 300°C. The precursor poly(amic acid) is soluble in polar solvents such as dimethyl formamide and N-methylpyrolidone (NMP). For microelectronic applications, thin films are deposited on the substrates by spin or spray coating of the poly(amic acid) solution, and the thin films are then cured and

14 imidized. The curing typically involves two-step process: first a soft cure at a temperature of 120 to 250°C is performed in air at normal atmosphere pressure to remove the coating solvent; then, it is followed by a hard cure performed at a temperature of 300 to 450°C in a N2 atmosphere to complete the imidization. The degree of imidization has significant effect on the chemical and physical properties of polyimides. Fully cured polyimides, for example, are not soluble in any of the organic solvents, but partially cured polyimides are soluble in the polar solvents. Studies have shown that there is minimal degradation during the curing process. A large number of polyimides that differ in the chemical structures of R and R’ (see Figure 2.1) have been synthesized. Commercially available polyimides that have been used in electronics include Kapton and Pyralin manufactured by Dupont, and PIQ (polyimide isoindoloquinazolinedione) manufactured by Hitachi Co. of Japan. Kapton polyimides are derived from pyromellitic dianhydride (PMDA) and 4,4’-diaminodiphenyl ether (DADPE). Pyralin polyimides are sold as a solution of poly(amic acid) derived from PMDA and DADPE or from benzophenone tetracarboxylic dianhydride (BTDA) and DADPE. Polyimide thin films used in microelectronic applications are often patterned by use of photolithography. Since the patterning process requires many processing steps, photosensitive polyimides have been under development for a number of years and have become commercially available. 2.1.2. Polyimide Properties The physical and chemical properties of polyimides are strongly dependent on the imidization degree, the molecular weight, and the chemical structures of R and R’ in the polymer backbone. The polyimide precursors, poly(amic acids), are highly soluble polyelectrolytes. They are soluble in polar solvents, e.g., N-methyl pyrrolidone, dimethylformamide, dimethylacetamide, etc., and can readily form salts. The molecular weight difference between the precursor molecules and cured polyimide molecules is quite small, indicating minimal degradation after curing. Studies have shown that both curing temperature and time are important in obtaining the complete cure [32], which leads to stable and strong chemical and physical properties of the polymers. Polyimide for electronic applications must be able to withstand a large number of heat-treatment processes. Even if the number of high-temperature steps is minimized,

15 there are a number of essential operations that need to be carried out at high temperature. These include sealing, packaging, die bonding, wirebonding, and soldering. Due to the aromatic groups in the polymer backbone and especially in the structure of R’, the glass

transition temperature (Tg) of commonly used polyimides is significantly higher than the

Tg of most organic polymers. The resistance of aromatic polyimides to ionizing radiation such as high-energy electrons, neutrons, and gamma radiation is excellent. The electrical and mechanical properties are unaffected by exposure to radiation dose of 1010 rad of high-energy electrons [33] and 108 rad (Si) of gamma radiation [34]. However, polyimides are affected by long-term exposure to UV light. Mechanical properties are degraded after 4000 hr exposure to UV light [33]. The solubility of polyimides is dependent on the degree of imidization, the polymer backbone and side chain structures, and the molecular weight of the polymer. In general, the solubility decreases with an increase in degree of imidization and an increase in molecular weight. Fully imidized aromatic polyimides are very resistant to organic solvents and are soluble in concentrated H2SO4 and HNO3. Solubility in organic solvents can be improved by modifying the structure of polyimides. The increase in solubility, however, is generally accompanied by a decrease in the thermal stability. Polyimides possess some favorable properties for applications in electronics, as tabulated in Table 2-1 [30]. The dielectric constant of polyimides is in the range of 2.7 to 3.7 at 1 MHz and room temperature. A low dielectric constant is necessary to get high- speed signal propagation devices and high radiation efficiency for the microstrip patch antennas built on these dielectric substrates. The dissipation factor (loss tangent tanδ) of polyimides is very small, in the range of 0.001 to 0.003 at the same frequency. The volume resistivity and dielectric strength of polyimides are favorably high, on the order of 1016 Ωcm and 106 Vcm-1, respectively. Two concerns for the use of polyimides as dielectrics are the absorption of water vapor and the effect of moisture on electric and mechanical properties of polyimides. The dielectric constant has been found to increase linearly as with increasing relative humidity. It has been found that cure conditions have a small effect on dielectric constant, but have a much stronger effect on the dissipation factor. The dissipation factor increases as relative humidity increases. Breakdown voltages decrease from 3.3 MV/cm at 0% RH to 1.6 MV/cm at 100% RH, and cure

16 conditions have an insignificant effect on breakdown voltage [35]. Meanwhile, polyimides have also good mechanical properties, such as the high Young’s modulus and tensile strength obtained for polyimide thin films.

Table 2-1 Typical chemical and electrical properties for commonly used polyimides

Dielectric Dissipation Tg Water constant factor (°C) absorption (%) Polyimide (PI) 3.4-3.8 0.002 >320 1.7 Fluorinated PI 2.7-3.0 0.002 <300 0.7 Silicone PI 3.0-3.5 0.0016 <300 0.9 Low stress PI 2.9 0.002 >400 0.5 Acetylene Terminated PI 2.9-3.4 0.002 <320 1.4

Good adhesion to the substrate is an important requirement of polyimides for microelectronic applications. In general, the aromatic polyimides show good adhesion to the surface of aluminum and chromium, but have poor adhesion to silicon or silicon dioxide. Adhesion can be improved by applying an adhesion promoter that adheres well to both the substrates and polyimides. To better explore the interfacial phenomena between polyimides and metals, which are often used to build the microwave circuits such as transmission lines and other passive components, the following section is devoted to this understanding.

2.2. Metal-Polyimide Interfacial Phenomena A key requirement of any multichip module packaging approach is the issue of metal/polymer interface characteristics such as adhesion, chemical reaction and diffusion. The adhesion of polymer films is highly dependent on the surface chemistry of both the metal and the polymeric dielectric material. In the case of polyimide, numerous studies have shown that to achieve good adhesion, one must use a metal primer layer such as Cr or Ti. These metals have been shown to form chemical bonds at the polyimide interface resulting in strong bonding of the deposited metal layer. Particularly the polyimide having a pyromellitic dianhydride-oxydianiline (PMDA-ODA) building block is commonly used. The fundamental unit of this polymer chain is shown in Figure 2.3. It consists of two parts: (1) a PMDA part, which contains

17 four C=O bonds, a benzene ring, and two N atoms; and (2) an ODA part, which consists of two benzene rings connected through an ether oxygen [36]. The metal-polyimide interactions have been intensively studied for a number of metals, including Cr, Ti, Ni, Co, and Cu. The adhesion of polyimide to metal differs according to the kind of metal, as shown in Table 2-2 [37]. Adhesion to aluminum is superior, and the adhesion to copper or nickel, which is occasionally used as deposited on copper wire, is also in an acceptable range. In the following discussions, the metal-polymer interface properties are summarized for Cr and Cu to illustrate strong and weak bonding characteristics.

O O C C

N N O

C C O O

PMDA part ODA part

Figure 2.3 Pyromellitic dianhydride-oxydianiline (PMDA-ODA) building block.

Table 2-2 Peel strength of polyimide on metal substrates Substrate or surface Adhesive strength* Al 1 Cr 0.8 Ni 0.7-0.8 Mo 0.4-0.5 Ag 0.2 Au 0.1 * Adhesive strength is normalized by the value of aluminum.

2.2.1. Chromium-Polyimide Interface Previous research result has indicated that for this strongly interacting metal, reaction occurs immediately upon metal deposition formed on the polyimide [36]. In the investigation, electronic structures derived from molecular orbital calculation for various

18 configuration of the Cr-polyimide complex were used to interpret the spectroscopy result, which gives a satisfactory explanation for the calculation and the result. In this theory, since chromium is at the beginning of the transition metal series and is essentially 3d electron poor, it is energetically favorable for it to be located at sites of high coordination. A model of the interaction of Cr with PMDA-ODA can be constructed as follows:

a b

Figure 2.4 (a) Lowest unoccupied level of the PMDA fragment and Cr 3dxy orbital (occupied). The orbitals are shown at a large separation (noninteracting). (b) Occupied orbital of the complex that occurs as a result of the interaction of the unoccupied a2 orbital and filled Cr 3dxy orbital. For orbitals, the opposite phases are indicated by + or – , and the filled and empty orbitals are shaded and unshaded, respectively.

Chromium initially bonds in highly coordinated sites on the PMDA fragment, forming a Cr-polyimide complex. Increased coverage results in saturation of such energetically active sites and forces Cr to interact with the phenyl rings of the ODA fragment. This occurs as the overlayer thickness approaches one monolayer. Central to the formation of the Cr-polyimide complex is the charge transfer from the deposited Cr atom to the lowest unoccupied molecular orbital (LUMO) of the repeat unit of the monomer. The relative stability of these complexes depends on the site coordination. For Cr, the most stable complex is the one with the highest coordination on PMDA. The manner in which charge is transferred from Cr to the various atoms in the polymer repeat unit indicates that the chemical bond between Cr and the polyimide is delocalized in nature. The mechanism of delocalized bonding can be illustrated in the molecular orbital overlapping shown above (see Figure 2.4) [36].

2.2.2. Copper-Polyimide Interface With respect to chemical reactivity, Cu represents a contrast to Cr, since its filled d orbitals (3d10) lead to significantly weaker interaction with the polymer. Since Cu is more electron-rich than Cr, it is not as energetically favored as Cr to occupy high coordination sites. Such chemistry weakens the interaction with the underlying polymer, and consequently incomplete coverage due to island formation was observed. Such an effect of chemical reactivity on the interfacial structure has been found to be important for all the metal-polyimide interfaces. It was reported that when polyamic acid (polyimide precursor) was heated in contact with copper, the properties of the resultant polyimide deteriorated [37]. This phenomenon occurred by the migration of copper into the polyamic acid film during curing. The migrated copper interacts with the imide ring and lowers the bond energy of the imide ring, which results in a lowering of the thermal decomposition temperature. This deterioration can be prevented by depositing a thin metal layer, such as chromium, on copper, which also provides better adhesion. Polyimide bonding characteristics have been investigated for three other 3d metals, Ni, Ti, and Co [38-40]. Together these studies reveal a consistent chemical trend in which the bonding strength and the chemical reactivity depend upon the number of the d electrons in the metal. The overall bonding characteristics are well explained by the formation of metal-polymer complexes. On this basis, Ti is similar to Cr, as it interacts strongly with the polyimide, while Ni is similar to Cu, although its reactivity is somewhat higher. The trend in the chemical reactivity is also reflected in the interfacial morphology obtained with initial metal coverages. Again Ti is similar to Cr, with uniform coverage, while Ni is close to Cu, with island formation. Aluminum, a metal with p valence states, has also been investigated. Its bonding strength and chemical reactivity are intermediate between those Cr and Cu. For microfabrication process, a thin layer of metal Cr or Ti is often deposited between polyimides and desired metal circuits for better adhesion or preventing deteriorative reaction.

20 2.3. Polyimide Thin Film Processing Overview Because of their processibility, polyimides have a wide range of applications in microelectronics. A variety of techniques can be used to deposit and pattern polyimide films over a wide range of geometry. Polyimides can be obtained in solution form as poly(amic acid) or soluble polyimide. This solution can be deposited by a variety of techniques such as spin or spray coating, screening, dipping, or roll coating to produce a wide range of film thickness (1 to 100 µm). The ability of the polyimide solutions to flow before curing promotes the planarization of the underlying substrate or conductor patterns. During curing at moderate temperatures (300 to 420°C), the poly(amic acid) is converted to polyimide, which has excellent thermal, mechanical, and chemical stability and is thus resistant to degradation during subsequent processing steps such as metal deposition, etching, or photolithography. The polyimide films can be patterned by a variety of techniques such as wet etching, plasma or reactive ion etching (RIE), ion milling, laser ablation, or direct photopatterning of the photosensitive polyimide. Two types of Pyralin polyimides made by Dupont, PI1111 and PI2611, have been used in this research. In general, the properties of polyimide layers made from these polyamic acid precursors are similar to each other. Pyralin PI1111 is a fluorinated polyamic acid intended for use as a stress buffer layer in semiconductor IC applications and as dielectric layer in high density interconnects. The chemical structure is designed to impart good mechanical and electrical properties. In addition, PI1111 has an adhesion promoter incorporated into the formulation, thereby eliminating the need for a separate priming cycle prior to coating. This product exhibits excellent thermal, electrical, mechanical and adhesion properties which are maintained throughout high temperature processing cycles. The features of cured PI1111 polyimide include [41]: • very high purity • high tensile strength of around 215 MPa • flexible with good elongation up to about 50% • high glass transition temperature above 350 °C • low weight loss of 2.0% when held at 500 °C for 2 hours • low dielectric constant: 2.8 • low moisture absorption: 0.9% at 50% RH

21 • low coefficient of thermal expansion (CTE): 27 ppm/°C Pyralin PI2611 is a fully aromatic polyimide with high molecular weight, based on BPDA/PPD (biphenyldianhydride/1,4-phenylenediamine) backbone chemistry. This product has similar and comparable properties as PI1111 possesses, a desirable combination of film properties such as low stress, low CTE, low moisture uptake, high modulus and good ductility for microelectronic applications. Both PI1111 and PI2611 products are supplied as polyamic acid precursors dissolved in an N-methyl-2- pyrrolidone (NMP) based solvent carrier suitable for spin coating applications and other coating techniques. 2.3.1. Spin Coating Spin coating is the most common technique for depositing thin polyimide films. It is a well-characterized process that is used frequently for depositing photoresists in IC processing, and automated spin coating equipment is widely available. Spin coating has also been modeled to predict the effects of a variety of process parameters on coating thickness and uniformity. The thickness of spin-coated polyimide films depends strongly on the solution viscosity and concentration, and can be accurately controlled over a wide range by varying the dispense volume and the time and angular speed of spinning. The most sensitive process parameter for controlling film thickness is the spin speed; film thickness generally varies with spin speed according to a power law relationship:

t = kω r Eq. 2.1

where t is the film thickness and ϖ is the angular spin frequency. For example, typical values for soft-cured (at 120°C) Pyralin PI2555 polyimide spun for 60 seconds are k = 90 and r = -0.7 [35]. In order to get good uniformity and planarization across the substrate, the largest practical film thickness achievable by a single spin coating run is limited, on the order of 15 microns. Thicker films, such as those required for interlayer dielectrics in IC packaging and MMIC (monolithic microwave integrated circuits) applications, are deposited with multiple coatings. In general, the deposition of thick polyimide films by spin coating requires high viscosity solutions that are spun at low angular speeds for short

22 times. All of these factors adversely affect the uniformity of coating thickness. Furthermore, spin coating is limited to square or round substrates a few inches in diameter with no large surface topography. Since smooth surfaces of interlayer dielectrics lead to lower roughness of circuit conductor surface, which lowers the conductor loss in device performances, spin coating is employed to carry out the deposition of polyamic acid precursors for both PI1111 and PI2611. 2.3.2. Adhesion Promoters Adhesion of polyimide films depends highly on the surface chemistry of both the substrate and the polyimide, the substrate roughness and cleanliness, the deposition conditions, and the degree of polyimide curing. Long-term environmental effects, particularly the combination of high temperature and humidity, can significantly degrade the adhesion of polyimides to some materials. Adhesion promoters are frequently used to improve the initial adhesion of polyimide to various surfaces or to reduce the degradation in adhesion due to environmental effects. Two types of adhesion promoter most commonly used in depositing polyimide films are the silane-based adhesion promoters and aluminum chelate compounds. The mechanisms involve the adhesion promoter molecules reacting with the corresponding groups on substrate surface and forming strong chemical bonds. In practice, either type of adhesion promoter is applied as a very thin coating, usually by spin coating, prior to deposition of the polyimide. As being pointed out early, PI1111 has an adhesion promoter incorporated into the formulation, thereby eliminating the need for a separate priming cycle prior to coating. PI2611 is not self-priming and needs the adhesion promoter. Dupont VM-651 adhesion promoter can be used for this purpose. VM-651 is an organosilane for improving the adhesion of Pyralin polyimide coatings to substrates such as silicon dioxide or silicon nitride coated wafers. It is easy to apply and effective at very low organosilane concentrations. Among all the organosilanes that possess either amino or epoxy groups, α-amino propyltriethoxysilane (active ingredient in VM-651) was found to give the best and most consistent overall results [42]. Experimental results indicate that only a monomolecular layer is needed to promote adhesion. These results indicate that a Si-O bond is formed with the substrate. Adhesion results are sensitive to the number of bonding site on the substrate surface. For

23 example, adhesion to silicon dioxide is typically superior to adhesion to silicon nitride. These promoters are not effective with substrates which do not form any native oxide. Because of this feature, chromium or titanium metal thin layer, which often possesses native oxide, is deposited as priming layers between polyimides (both PI1111 and PI2611) and Au or Cu, and between silicon substrates and Au or Cu. Adhesion promoter VM-651 is a concentrate which must be diluted with water or methanol/water solutions before application. 2.3.3. Polyimide Panarization Planarization is important for the successful fabrication of semiconductor IC and MMIC devices. One of the chief advantages of polyimides as an interlayer dielectric is its ability to planarize underlying conductor topography. The step height of conductor lines is reduced, sidewalls angles are reduced, and sharp corners become more rounded. This planarization effect improves the accuracy, resolution, and yield of subsequent photolithography and patterning operations. Due to hydrodynamic force, a freshly coated polyimide solution will initially form a planar surface over any topographical feature whose height is less than the thickness of the deposited film. As the solvents evaporate, however, the viscosity of the polyimide solution increases until it is eventually unable to flow. Further solvent evaporation causes the film to shrink and partially conform to the underlying topography. The common

measure of planarization over a step or conductor line of initial height ti is the degree of planarization (DOP), defined as t DOP = 1− f Eq. 2.2 ti where tf is the final step height in the polyimide film after curing. The DOP is highly dependent on the solution viscosity and solids content, the molecular weight of polyimide, and the spacing between conductor features, and it may depend on the

thickness of the polyimide film if it is less than the conductor step height ti. The DOP increases for multiple coats of polyimide, due to the incremental planarization of each coat. Thus, for a given film thickness, several thin coatings are preferable over a few thick coatings from the standpoint of planarization.

24 2.3.4. Patterning of Polyimide Thin Films The formation of a fine pattern in polyimide thin films is required for the interconnecting of the circuits on the different physical levels of the device. Via-hole structures are often encountered in 3-D MMICs in order to wire the circuitry in a vertical fashion. Therefore, patterning of polyimide interlayer dielectric thin film is crucial in MMIC fabrication. Polyimide films can be patterned by a variety of techniques, including wet or dry etching through a photolithographically defined mask, direct photopatterning of photosensitive polyimides, or laser ablation. The process steps involved in wet etching, dry etching, and direct photopatterning are illustrated in Figure 2.5 for comparison. • Wet etching At the earliest stage of patterning polyimides, wet etching was the primary technique. As shown in Figure 2.5, a pattern is first defined in a positive or negative photoresist film deposited on the polyimide. The unmasked polyimide is then selectively dissolved, and the photoresist is stripped. Fully cured polyimide films can only be etched with a solution containing hydrazine hydrate (H2NNH2 : H2O). Additives such as ethylene diamine (NH2CH2CH2NH2) have been added to increase the etch rate and improve the linearity of etch rate with time [43]. Since hydrazine is toxic and highly pyrophoric, it is not recommended for popular lab usage. A number of etchants can be used to etch polyimide if it is in partially imidized state. Ordinary alkaline solutions that are used to develop positive photoresists, such as potassium hydroxide, sodium hydroxide, and tetralkyl ammonium hydroxide, will etch partially cured polyimide. In this way, the photoresist can be developed and the polyimide can be etched in a single step. If a negative photoresist is used, the organic developers (such as xylene) will not etch polyimide, and separate etchants are required to wet etch the polyimide. The residues left by these alkaline etchants must be neutralized with acetic acid and water rinses. The photoresist is then removed with standard photoresist solvents that will not attack partially cured polyimide. This precludes the use of some strong resist strippers that contain NMP.

Figure 2.5 Comparison of the process steps involved in patterning polyimide by wet etching, dry etching, and photopatterning of photosensitive polyimide.

Small aspect ratio (thickness/width) is a limitation for all wet etch processes. Low resolution and small aspect ratio are also the primary limitations of wet etching of polyimides. Another drawback of wet etching is that with the exception of the hydrazine etchants, it requires that the polyimide should not be fully cured, and the partial cure is difficult to control. Since the etch rate depends on the degree of cure, it is difficult to

26 reproduce etch rate and control pattern geometries. Finally, the additional shrinkage of the films during the final full cure after wet etching may cause further loss of resolution and/or localized cracking due to the stress that is concentrated at patterned features. Based upon these reasons, wet etching was not used in this research. • Dry etching Almost all of the limitations involved in wet etching can be overcome by etching polyimide using “dry” vacuum processes such as plasma etching or reactive ion etching (RIE), in which the substrates are placed on the lower electrode in a parallel system sustaining an RF plasma. Other dry etching processes include reactive ion beam etching (RIBE) or ion beam-assisted etching (IBAE), in which a beam of reactive ions (e.g., O+) or inert ions (e.g., Ar+) are accelerated toward the substrates, which may be flooded with a reactive gas such as O2. In all of these processes, the etching reactions are initiated by the ions that are accelerated perpendicularly to the film surface; therefore, these processes can produce high-aspect-ratio features with nearly vertical sidewalls in fully cured polyimide films. The process reproducibility is much higher than wet etching. By varying the process parameters, such as reactor pressure, gas composition and flowrate, and RF power or ion beam energy, and etc., the etch rate, the selectivity for etching different materials, and the tapered angle of sidewalls can be accurately controlled. RIE is the most commonly used polyimide dry etching process, in which the substrates are placed on the powered electrode in a parallel plate plasma system. Polyimide is usually etched in a gas mixture of oxygen and a fluorine-containing gas such

as CF4 or SF6. The feed gas may contain certain percentage of argon for the actinometry purpose. Research results have shown that the polyimide etch rate increases rapidly with increasing fluorine concentration, reaching a maximum at about 20% CF4 or 60% SF6, and then decreasing at higher fluorine concentrations [44-46]. It is explained that when an excess of F atoms (higher CF4 concentration) exists, polyimide surfaces can be passivated by the formation of fluorocarbon compounds and etching is inhibited [44,47]. However, a maximum etching rate at a low CF4 concentration of only 2.5% was also reported [48].

The explanation is that the percentage of CF4 in O2 required to achieve maximum etching rate depends strongly on the load size, increasing load size demands a higher CF4 concentration. The fluorine concentration is also a sensitive parameter for controlling the

27 sidewall angle of etched features. A tapered sidewall is often desired for good metal step

coverage, and this taper can be controlled by adjusting the CF4 content in the plasma etch gas [49]. Since polyimides etch at nearly the same rate as photoresists, RIE etching of thick polyimide films requires that a masking layer of a slow etching material be deposited and patterned on top of the polyimide, as shown in Figure 2.5. Materials that have been used as masking layers include metals such as Al, Cr, Ti, or Mo, inorganic materials such as plasma-deposited silicon nitride or silicon dioxide, or spin-on glasses such as SiO2 or aluminum chelate compounds. The typical etch rates of common microelectronic materials in dry etching processes are tabulated in Table 2-3 as the reference for choosing appropriate masking material for the corresponding fabrication process. In this research, it has been found out that thin layers of aluminum or gold deposited on top of polyimide can serve as good masking layers while conducting the reactive ion etching of fully cured PI2611 and PI1111 polyimide films.

Table 2-3 Typical etch rates of common microelectronic materials [50] Dry etching conditions Etch rate (Å /min) In CF4 +4% O2 plasma (with etch tunnel) Silicon nitride 100 Silicon (111) 690 Silicon (polycrystalline) 990 Silicon dioxide (thermal) 40 Silicon dioxide (CVD) 120 Tungsten 100 Molybdenum 100 Titanium 100 Tantalum 100 Aluminum 0 GaAsP 0 Waycoat IC photoresist 20 AZ1350J photoresist 40 In Cl2 +50% O2 plasma (without etch tunnel) Chromium 20 In C2Cl2F4 plasma (without etch tunnel) Gold 100

28 2.4. Processing of Polyimide Thin Films 2.4.1. General Processing Guidelines Both PI1111 and PI2611 products are supplied as polyamic acid precursors dissolved in NMP based solvents suitable for spin coating applications. These products can be coated and patterned over a variety of substrates and metals surfaces. Prior to spin coating the substrate should be cleaned, free of particles and any surface contamination. Traditional wet and dry cleaning techniques can be used to accomplish this. Since PI1111 has already incorporated an adhesion promoter into its formulation, no additional application of adhesion promoter is necessary. But for PI2611, an aminosilane based adhesion promoter such Dupont VM-651 should be used to enhance adhesion to silicon, ceramic and patterned metallization. VM-651 is a concentrate which must be diluted as DI water or methanol/DI water solutions (0.01 to 0.1%) before application. While water solutions of VM-651 yield the most uniform results, methanol/water solutions can be used to accelerate drying. Primed wafers may be stored up to 24 hours before coating with polyimide. There are a lot of dispensing tools and methods for applying polyimide solutions to the substrates. General guidelines for dispensing materials of this type are as follow: 1. For best results, coating should be done in a clean room environment, with the relative humidity level < 50%. 2. Always coat substrates which are at room temperature. 3. Dispensing should be done in the center and as close to substrate as possible. 4. Never trap air into the solution. 5. Take time to allow any bubbles to dissipate out of solution, if left in, comet-like coating defects could result. 6. A clean-off at dispense is necessary before the spinning. 7. Allow a short delay prior to spin for the polyimide to flow as far as possible and relax. It is important to assure that the polyimide is dispensed in the exact center of the wafer. Acceleration to final spin speed should be as slow as possible to allow the polyimide to flow across the substrate. Often one or more intermediate spin speeds can be used to

29 allow the polyimide gradually cover more than 80% of the substrate before continuing on to the final spin speeds. The final spin speed and spin time is determined by the film thickness desired. To reduce backside contamination potential it is often beneficial to prolong the spin cycle until the bulk of the excess polyimide has been removed from the substrate. Longer spin times will improve coating uniformity but will reduce the film thickness. In production applications an edge bead remover (EBR) and/or backside rinse (BSR) maybe added to the coating cycle to remove polyimide from the edge and back of the wafer prior to baking. Commercially available NMP or cyclopentanone based solvent blends can be used for this purpose. Thick films of polyimide can be obtained through multiple coating techniques. An intermediate soft bake is typically performed between coats at 170°C on a hot plate or in a convection oven. It is possible to spin apply 2-4 coats in this manner prior to final cure. Curing process converts the polyamic acid into a fully aromatic, insoluble polyimide and drives off the NMP solvent carrier. This process requires elevated temperatures and controlled environments to achieve the best results. There is sufficient energy at 200°C to nearly complete the polyimide imidization process. However higher temperatures are required to completely dissociate the carrier solvent, fully imidize the film and complete polymer orientation, thereby optimizing electrical and mechanical properties. Coated films are usually baked in two process stages. The first stage is called soft bake and the second stage called curing. In order to optimize the planarization of polyimide films, a pre-soft bake process is conducted by placing the coated films in fab air at room temperature for 30 minutes. Then a soft bake is carried out in two steps: first bake in a lower temperature process and then an escalated temperature is used. The temperatures and times of the soft baking processes depend on the type of ployimide used (see next section for detail). The soft-bake process removes most of the solvent from the coating and produces partial imidization of the polyamic acid. Hot plates or convection ovens can be used for the process. Caution should be taken here is that after spinning and during baking processes, the wafers should be kept in a horizontal position.

30 Final curing (second stage bake) can be done in a programmable oven to complete the imidization and consolidation of the film. An inert atmosphere such as nitrogen or forming gas is preferable although air can be used as the ambient up to 300°C. The loading temperature can be at ambient or at the previous soft bake temperature. Ramp rates are predicted around film thickness and substrate composition. Polymeric films have a natural “solvent-removable rate.” If this rate is exceeded, bubbles, thickness variations and poor surface texture could result. Slow ramping and cooling is recommended to minimize substrate deformation and optimize film uniformity. Final cure temperatures are predicted around the desired ultimate cured film properties and subsequent processing temperatures. Nominally 350°C for 30 minutes is an adequate cure for most applications. As discussed in previous section, fully cured polyimide films are difficult to pattern using traditional wet etching techniques. Both dry etching and laser ablation techniques have become the preferred process routes for patterning polyimide films. RIE, a preferable dry etching technique, is widely used for this purpose. Specific RIE conditions depend on the type of polyimide, film thickness, and resolution or desired

aspect ratio. An etch gas composition of 75-80% oxygen and 25-20% CF4 is typical. Power level (or power density) is usually 100-500 watts (or 5-25 watts/cm2) and vacuum pressure in the range of 100-500 mTorr. After RIE, it may be necessary to clean patterned vias or metal conductors of residues. Reverse sputtering, or a low pressure and a little higher power oxygen or etch gas plasma clean may be used for this purpose. The high modulus, thermal stability and low stress of cured polyimide films make them well suited for most thin film metallization processes. Building multiple layer circuits is a straightforward process. Prior to deposition it is helpful to slightly roughen the surface of the cured polyimide film using oxygen plasma to improve the mechanical adhesion of the next metallization or polymeric layer. A dehydration bake performed between 100-200°C is also recommended prior to metal deposition but not necessary for subsequent polyimide layers. Adhesion promoters such as VM-651 are frequently used in the application of polyimide dielectric layers over patterned metallization. 2.4.2. Processing Experiments and Results In this research polyimides were used as interlayer dielectrics in the 3-D MMIC devices. The polyimide films on the ground plane or between the circuit planes were

31 deposited with the direct contact of chromium as inter-metal layer (nominally 300 Å) between the major conductor planes (nominally 1-2 µm) to enhance adhesive strength, where copper or gold was used. Spin coating was proven to be the best application processing for this purpose. As far as the desired film thickness was determined, the spin speeds and times could be determined by consulting the spin speed curves [41,51]. All the processing steps comply with the concerns discussed in the previous section, such as dispensing, coating, soft-baking and curing conditions. It is necessary to point out that both PI1111 and PI2611 polyamic acid solutions have a manufacturer specifying “shelf life” even if they are kept in freezer storage. Thus, before using the solution, it was made sure that the material did not expire. For a comparison, the processing details of a single layer of polyimide film deposited on the metallized substrates by using PI1111 and PI2611 polyamic acid solutions are summarized in Table 2-4.

Table 2-4 Processing details for the deposition of PI1111 and PI2611 films PI1111 PI2611 Substrate cleaning Required Required and dehydration Adhesion promoter None Diluted VM-651 Spread: 500 rpm, 5s Spin: 5000 rpm, 30s Oven at 130°C, 15mins Spin coating First spin: Spread: 500 rpm, 5s Spread: 500 rpm, 5s Spin: 2000 rpm, 30s Spin: 2000 rpm, 30s Second spin: (Target: 8.5 µm cured) Spread: 1000 rpm, 10s Spin: 2000 rpm, 15s (Target: 11 µm cured)

Pre-soft bake Room temp., 30mins Room temp., 30 mins In fab air In fab air

Soft bake Step 1: Step 1: Oven at 60°C, 30mins Oven at 90°C, 30mins Step 2: Step 2: Oven at 130°C, 30mins Oven at 130°C, 30mins

Curing (Hard bake) Programmable oven Programmable oven (with N2 atmosphere) (with N2 atmosphere) Starting: R.T. Starting: R.T. Ramp: +1°C/min Ramp: +4°C/min Curing temp.: 350°C Curing temp.: 350°C Soak: 30mins Soak: 30mins Ramp: -1°C/min Ramp: -4°C/min Ending: R.T. Ending: R.T.

32 In general, the deposition of thick polyimide films by spin coating requires high viscosity solutions that are spun at low angular speeds for short times (see Eq. 2.1). All of these factors adversely affect the uniformity of coating thickness. In order to obtain good uniformity, thick films can be deposited with multiple coatings with an intermediate low temperature curing process between coatings. It has been found that an additional spin coating of polyamic acid solution can be spun onto the layer of polyimide film after soft baking, and then curing the substrate to finish the imidization. In this way multiple layers of polyimide films with high thickness were obtained. For spinning PI2611 polyamic acid solution onto PI2611 polyimide film, there was no need to apply VM-651 adhesion promoter, while oxygen plasma roughening the surface improved the adhesion if the substrate polyimide film was fully cured. For better results of multiple layers, carrying full curing after each two-layer deposition of polyamic acid precursors is recommended. PI1111 and PI2611 can be spun and coated up to 4 layers before a full curing. Experimental results for the deposition of one or more layers (up to three layers) of polyimide films onto 2-inch silicon wafers using PI1111 polyamic acid solutions are tabulated in Table 2-5, and the thickness measurement points are shown in Figure 2.6. The FilmetricTM thickness measurements were confirmed by the defining-and-etching DektakTM step thickness measurements. Due to the viscosity characteristics, it has been found that the polyimide on the wafer outer edges was thicker than that in the central area (shown in Figure 2.6 as shadowed area).

Table 2-5 FilmetricTM measurements for PI1111 films 1 layer 2 layers 3 layers A 10.69 20.98 33.29 B 10.73 21.22 33.38 C 10.49 21.14 33.01 D 10.71 21.42 33.31 E 10.44 21.29 32.93 Ave. 10.61 21.21 33.18

Figure 2.6 FilmetricTM measurement points on 2-inch wafer (thick film in shadowed area)

The polyimide films in Table 2-5 were prepared following the procedures outlined in Table 2-4 for the single layer or repeated for multiple layers. Since the sample is PI1111, the process is that 2-layer film was cured once and 3-layer film was cured twice, one after two-layer deposition and the other in the final. From the thickness measurement results, it has been shown that fairly high uniformity of the polyimide films can be deposited across the wafers, except the edge regions. Better results can further be obtained by optimizing the process parameters. By plotting the polyimide film thickness as a function of the deposition layers, it was shown that there was a linear relationship between the thickness and the number of deposition layers which meant more deposition layers could produce the desired film thickness (as shown in Figure 2.7).

m) 30 u ( s s e

n 20 k ic h 10 ilm t f

0 01234 number of layers

Figure 2.7 PI1111 polyimide film thickness vs. deposition layers

34 Etch rate of gold in CF4/O2 plasma RIE process is significantly smaller than that of polyimide films. Using a thin layer of gold (200-500 Å) deposited on top of the polyimide film as masking material, polyimide film can be patterned in the RIE process. If there is not a cooling system to cool the RF powered plate where the wafers are placed, there is a possibility that as the RIE processing proceeds the wafer temperature will increase. Since etch rate depends exponentially on reaction temperature (T) as shown in Eq. 2.3, increasing temperature will dramatically increase the etch rate in all directions, and the aspect ratio will decrease. To achieve high aspect ratio, the powered plate holding the wafers in the parallel RIE system had to be cooled to maintain a constant temperature

during etching. As indicated in the etching rate (Eq. 2.3), r0 increases linearly with RF power and a, activation energy, is basically constant (R is the gas constant, 8.314 J ⋅ K −1 ⋅ mole −1 ).

−a = RT Eq. 2.3 r r0e Figure 2.8 shows a via hole 24 µm in diameter that has been RIE etched in PI1111 polyimide film 11 µm thick, using gold as the etch mask. Even without a cooling system, fairly good aspect ratio has been achieved as the tapered sidewalls.

Figure 2.8 SEM micrograph of a via hole 24 µm in diameter etched in 11 µm thick PI1111 film using CF4/O2 RIE process, gold as masking material.

35 To probe further about the polyimide etch rate using the RIE system, a number of experiments have been carried out using PI1111 polyimide films with an RF power level of 100 watts at 13.56 MHz and the vacuum pressure in the range of 350-500 mTorr. The etch gas composition was controlled by three volumetric flow rate meters. In all the

experiments O2 flow rate was kept at 40 ml/min, Ar flow rate at 20 ml/min, and CF4 flow rates of 4 ml/min (lower flow rate), 7 ml/min (higher flow rate) or no CF4 input were investigated. The experimental results are summarized in Figure 2.9.

2.5 n)

i 2.0 m / m 1.5 (u te a

r 1.0 g n i h 0.5 Etc

0.0 -1012345678

CF4 flow rate (C C M )

Figure 2.9 Effect of CF4 flow rate on the RIE polyimide film (PI1111) etching rate

In order to study the temperature effect on the etch rate and the CF4/O2 etch rate of the PI2611 polyimide thin films, a set of experiments were conducted in an RIE chamber with controlled temperature. The RF power level was chosen at 250 watts (30

KHz), the etchant composition in flow rate was O2:CF4:Ar at 16:2:2 ml/min and the chamber pressure was maintained at about 200 mTorr. The effect of temperature on the etch rate of PI2611 polyimide thin films is shown in Figure 2.10. It can be seen that the variation of polyimide etch rate with temperature obeys the exponential behavior as described by Eq. 2.3. Thus an activation energy of 10.967 KJ/mole for the RIE processing of PI2611 thin films can be obtained, and r0 is about 54.13 µm/min.

36 1.6

1.4 ) n i 1.2 m / m

(u 1.0 te Ra

h 0.8 c t E

0.6

0.4 0 20406080100 Temp. (C)

Figure 2.10 Effect of temperature on the RIE etch rate of polyimide films (PI2611)

2.5. Summary Polyimides, through a two-step process which consists of solution spin-coating of polyimide precursor polyamic acid and subsequent high-temperature curing, can be deposited in thin film form with good film uniformity and topography. The thin film thickness can be precisely controlled by the processing parameters and number of layers. Good planarization property of spin-coated polyimide thin films provides the compatibility and possibility for interlayer conductor circuits integration, and hence three dimensional stacking of MMIC components. Fully cured polyimide thin films possess favorable electric and mechanical properties for the 3D MMIC applications. For the patterning of fully cured polyimide, RIE is a good thin film patterning process. With controlled processing parameters for the RIE process, desired features of specific structures can be obtained. However, in order to obtain the good polyimide properties and desirable features, special cautions and procedures have to be taken, as discussed in the content of this chapter.

37 Chapter 3 Characterization of Thin Film Dielectrics

An accurate knowledge of the complex dielectric constant of a substrate is very important for circuit design since this value determines major parameters of planar transmission lines such as the characteristic impedance, phase velocity and attenuation constant. Dielectric properties of monocrystalline materials such as silicon, quartz, sapphire and GaAs do not change form material to material. However, for plastic and amorphous materials such as glass, and polycrystalline materials such as ceramics, the dielectric constant depends on the manufacturing process and the composition of the final material. Polyimides, used as interlayer dielectrics in 3-D MMIC devices, are polymeric materials with amorphous molecular structures. These dielectric interlayers are generally deposited and patterned using the processes described in previous chapter. Their chemical and physical properties depend strongly on the processing parameters such as curing temperature and imidization degree. In order to characterize the processing of polyimide thin films and control the final film parameters, an accurate and simple relative dielectric constant measurement technique is necessary, especially for the relative dielectric constant (εr) measurement in the high frequency range. On-wafer measurement of thin films is relatively easy when planar transmission lines are used. Many on-wafer dielectric characterizations of thin films use microstrip transmission lines or microstrip-type resonant structures. Microstrip transmission line characteristics (such as characteristic impedance, losses or attenuation, and dispersion) will be summarized in the following section followed by the characterization of the polyimide substrates.

3.1. Microstrip Line Characteristics Microstrip line is one of the most popular types of planar transmission lines, primarily because it can be fabricated by photolithographic processes and is easily

38 integrated with other passive and active microwave devices. The geometry of a microstrip line is shown in Figure 3.1.

Figure 3.1 Microstrip configuration

A conductor of width W and thickness t is printed on a thin, metal backed (grounded) dielectric substrate of thickness h and relative permittivity εr. Since the field lines between the strip and the ground plane are not contained entirely in the substrate region, the fields propagating along the microstrip is not purely TEM waves [52]. In most practical applications, however, the dielectric substrate is electrically very thin (h<<λ), and so the fields are quasi-TEM. Thus, a good approximation for the phase velocity, propagation constant and characteristic impedance can be obtained from the quasi-static solutions. The phase velocity and propagation constant can be expressed as c Eq. 3.1 v = p ε e β = ϖ µ ε ε = ε Eq. 3.2 0 0 e k0 e

where εe is the effective dielectric constant of the microstrip line. Since some of the field lines are in the dielectric region and some are in air, the effective dielectric constant satisfies the relation, 1+ ε r < ε < ε 2 e r The quasi-TEM analysis is presented as follows. 3.1.1. Characteristic Impedance and Effective Dielectric Constant Closed-form design formulas for the effective dielectric constant and characteristic impedance of microstrip lines have been reported in the literature [52-54].

39 These results are derived from either rigorous quasi-static solutions or the numerical analyses of full-wave solutions. The effective dielectric constant of a microstrip line is given approximately by ε +1 ε −1 Eq. 3.3 ε = r + r F(W / h) e 2 2  1 + 0.04(1−W / h)2 for W/h ≤ 1  + F(W / h) = 1 12h /W  1  for W/h ≥ 1  1+12h /W The effective dielectric constant can be interpreted as the dielectric constant of a homogeneous medium that replaces the air and dielectric regions of the microstrip. Given the dimensions of the microstrip line, the characteristic impedance can be calculated as

 60  8h + W  ≤  ln   for W/h 1  ε  W 4h  Eq. 3.4 Z = e 0  120 π  for W/h ≥ 1 ε []+ + +  e W / h 1.393 0.667 ln(W / h 1.444 ) For a given characteristic impedance and dielectric constant, the expressions for

W/h in terms of Z0 and εr are given as

 8e A for Z ε > 89 .91( A > 1.52 )  2 A − 0 e  e 2 Eq. 3.5 W =  2  ε − 1  0.61   B -1 - ln(2B -1) + r ln( B − 1) + 0.39 − h π  ε  ε    2 r  r   ε ≤ ≤  for Z 0 e 89 .91( A 1.52 ) where

Z ε +1 ε −1 0.11 A = 0 r + r 0.23 +  ε +  ε  60 2 r 1 r  377π B = ε 2Z 0 r The results shown above are based on the assumption that the thickness of the strip conductor is negligible. But, in practice, the strip has a finite thickness t that affects the line characteristics.

40 3.1.2. Effect of Strip Thickness The effect of strip thickness on characteristic impedance and effective dielectric constant of microstrip lines has been thoroughly investigated. Simple and accurate formulas for characteristic impedance and effective dielectric constant with finite strip thickness are [55]

 60  8h W   ln + e  for W/h ≤ 1 ε W 4h  Eq. 3.6 =  e  e  Z0  120π  for W / h ≥ 1  ε []+ + +  e We / h 1.393 0.667ln(We / h 1.444) where

W 1.25 t  4πW  + 1+ ln (W/h ≤ 1/2π )  π   We  h h  t  =  h W 1.25 t  2h   + 1+ ln  (W/h ≥ 1/2π )  h π h  t  ε +1 ε −1 Eq. 3.7 ε = r + r F(W / h) − C e 2 2 in which ε −1 t / h C = r 4.6 W / h

It can be seen that the effect of thickness on Z0 and εe is insignificant for small values of t/h. However, the effect of strip thickness is significant on conductor loss in microstrip line. 3.1.3. Dispersion in Microstrip Line The quasi-static methods of microstrip analysis do not take into account the non- TEM nature of the microstrip mode. The non-TEM behavior causes the effective dielectric constant and characteristic impedance of the microstrip to be functions of frequency. Of these two, the variation of the effective dielectric constant is more significant. An exact evaluation of these variations involves a full-wave analysis of the microstrip configuration, which is more accurate but much more complicated than the quasi-static analysis. There are several semi-empirical techniques [56-58] available that lead to a closed-form solution for the dependence of effective dielectric constant and

41 characteristic impedance on frequency (f). One dispersion model based on that the quasi- TEM microstrip mode couples strongly with the lowest order TE mode [56] is briefly discussed as follows. 1. Dispersion of effective dielectric constant: ε − ε Eq. 3.8 ε ()f = ε − r e e r + ()2 1 f / fT

where fT is the cutoff frequency of the lowest order TE mode c Eq. 3.9 f = T ()+ ∆ ε 2 W W r

h ε and ∆W is the fringing edge of the strip, ∆W = e −W ε ε cZ 0 0 r where W is the line width at low frequencies obtained from quasi-static analysis. 2. Dispersion in effective width: W − W Eq. 3.10 W ()f =W + eff e + ()2 1 f / fT 120πh where W is the effective width of planar waveguide at zero frequency,W = eff eff ε Z 0 e 3. Frequency-dependent characteristic impedance: 120πh Eq. 3.11 Z ()f = 0 ()ε () We f e f It is shown from the discussion above that the effective dielectric constant monotonically increases with the increasing of frequency. Two extreme cases are, (a) as f → 0 (static analysis), the effective dielectric constant is equal to the quasi-static value; (b) as f → ∞, the effective dielectric constant approaches the dielectric constant of the substrate. It implies that the fields are concentrated in the region between the strip and the ground plane and energy propagates inside the substrate. From the microstrip configuration, it can be seen that the microstrip modes cannot be pure TE or TM waves either. In the optimization and computer-aided design of microstrip circuits, the following expressions for the effect of frequency on Z0 and εe are widely used [57, 58].

42 ε ( f ) −1 ε Eq. 3.12 Z ( f ) = Z e e 0 0 ε − ε e 1 e ( f ) ε − ε Eq. 3.13 ε ()f = ε − r e e r + ()m 1 f / f50 where f f = k ,TM 0 50 + − ε 1.73 0.75 {0.75 (0.332 / r )}W / h

 ε −1  c tan −1 ε e   r ε − ε  f =  r e  k ,TM 0 π ε − ε 2 h r e = m m0 mc

3 = + 1 +  1  m0 1 0.32  1+ W / h 1+ W / h 

 1.4   − 0.45 f   1+ 0.15 - 0.235exp  for W/h ≤ 0.7 m = +    c  1 W/h   f 50   1 for W/h > 0.7 The frequency dependence of the effective dielectric constant describes the influence of dispersion on the phase velocity (see Eq. 3.1), whereas the frequency dependence of the effective width describes the influence of dispersion on the characteristic impedance (see Eq. 3.11). For the thin substrates and high-impedance lines, the influences of frequency on the Z0 and εe are very small and negligible. The frequency below which dispersion effects may be neglected is given by the relation [53] Z Eq. 3.14 f = 0.3 0 d ε − h r 1 where fd is in gigahertz and h is in centimeters. Eq. 3.14 shows that fd is approximately 25

GHz for a 50 Ω microstrip line on the εr = 3.0 substrate (e.g., polyimide substrates) of thickness h = 50 µm. Thinner substrates even have higher fd values, which make the thin film microstrip (TFM) structure more favorable in MMICs with TFM employing a narrow-width microstrip conductor on thin low-dielectric constant materials such as polyimides or benzocyclobutene (BCB) polymers.

43 3.1.4. Losses in Microstrip Line All transmission lines have loss due to finite conductivity and/or lossy dielectric. In conventional transmission lines these losses are very small, but in the MMIC transmission lines these losses can be significant since the feature sizes are dramatically small and power levels are much lower. The attenuation constant is defined as = Power loss per unit length Pl (z) Pl (z 0) Eq. 3.15 α = ()= = 2 Power transmitted 2P(z) 2P0 The total attenuation constant due to different facts in the microstrip line can be written as α =+α α Tcd Eq. 3.16 α α where c designates the conductor loss and d the dielectric loss. A comprehensive treatment of conductor loss and dielectric loss in a microstrip structure has been given in literature [59-61]. The evaluation of attenuation due to conductor loss is based on the “Wheeler incremental inductance rule” for TEM or quasi-TEM transmission lines [26]. In this method the conductor loss of a line is due to current flow inside the conductor which is related to the tangential magnetic field at the surface of the conductor, and thus to the inductance of the line. The conductor loss can be expressed as  R 32 − (/Wh)2 13. 8A se dB / unit length (Wh/)≤1  + 2 e  hZ0 32 (/Whe ) Eq. 3.17 α =  c RZε ()f  06./67Wh 61. ×+10−5 A se0 Wh/ e dB / unit length (/Wh>1)   e +  e  h  Whe /.1444 where h 12. 5 2B =+  +  A 11 π ln  We  t  = πµ ρ ρ Rfsc0 and c is the resistivity of strip conductor 1  ≥ hW(/h) = 2π B  1 2πW (W / h ≤ )  2π Regardless of how attenuation is calculated, measured attenuation constants for practical lines are usually higher. The main reason for this discrepancy is the fact that realistic transmission lines have metallic surfaces that are somewhat rough, which

44 increases the loss, while the theoretical calculations assume perfectly smooth conductors. A quasi-empirical formula that can be used to correct for surface roughness for any transmission line is [62]

2 Eq. 3.18    ∆   α ' = α + 2 −1   c c 1 tan 1.4    π  δ      s  

where αc is the attenuation due to perfectly smooth conductors, αc’ is the attenuation

corrected for surface roughness, ∆ is the rms surface roughness, and δs is the skin depth of the conductors. Considering microstrip as a quasi-TEM line, the attenuation due to dielectric loss can be determined as ε ( f ) −1  ησ e 4.34 dB/unit length  ε ( f )(ε −1) Eq. 3.19 α = e r or d  ε ε ( f ) −1 tanδ 27.3 r e dB/unit length  ε −1 ε λ  r e ( f ) 0 σ = ϖε ε δ where 0 r tan and is the conductivity of dielectric substrate. These expressions are obtained by multiplying the TEM case with a “filling factor”, which accounts for the fact that the fields around the microstrip line are partly in air (lossless) and partly in the dielectric. The dielectric loss is normally very small compared with the conductor loss for most microstrip substrates. However, exceptions may occur with some semiconductor substrates because of the lower resistivity in the substrates. The losses due to the radiation and surface wave propagation are not discussed in this section. However, the radiation loss will be treated in the next section when the Q factor of the microstrip structure is concerned, especially with the presence of discontinuities. 3.1.5. Quality Factor There is another way to characterize the losses in microstrip lines, especially for resonant structures. The quality factor, Q, of a microstrip line can be related to the total loss in the line by

45 β Eq. 3.20 Q = α 2 T where β = 2π/λg. When losses in a resonant line are considered, loss factor due to radiation at the open-end discontinuities must also be taken into account. The corresponding radiation Q-factor is given by Z ( f ) = 0 Qr 2  h  Eq. 3.21 480π   R  λ   0  where

ε ( f ) +1 []ε ( f ) −1 2  ε ( f ) +1 R = e − e ln e  ε ( f ) []ε 3 / 2 ε − e 2 e ( f )  e ( f ) 1 So the total Q of the resonator can be expressed by 1 1 1 1 1 1 Eq. 3.22 = + = + + Q Q0 Qr Qd Qc Qr

Here Qc, Qd, and Qr are the quality factors corresponding to conductor, dielectric, and

radiation losses, respectively. Q0 is the unloaded circuit quality factor defined as follows [63]: 8.68π ε ( f ) Eq. 3.23 Q = e 0 λ α + α 0 ( c d ) 1 1 1 Eq. 3.24 = + Q0 Qd Qc 3.1.6. Discontinuities Associated with T-resonator Measurement Microstrip circuits inevitably incorporate transmission line discontinuities of one type or another. A complete understanding and design of microstrip circuits require characterization of various discontinuities included in the circuit. Since discontinuity dimensions are usually much smaller that the wavelength in a microstrip, they can be modeled by lumped-element equivalent circuits. For polyimide dielectric characterization, only discontinuities associated with the T-pattern resonator, such as open end and T-junction, are considered.

46 • Open end An open-end discontinuity occurs frequently in a number of circuits such as resonators, matching stubs, filters, and microstrip antennas. The equivalent circuit of an open end is represented by an excess capacitance Coc, which can be transformed into an equivalent length of transmission line, ∆l, as shown below.

∆ Coc l

T T T

Figure 3.2 Microstrip open-end discontinuity and its equivalent representations

The equations for calculating the excess length which is more convenient for circuit design, and relating it to an excess capacitance are [53] ∆l ε + 03. Wh/.+ 0 264 Eq. 3.25 = e   0.412 ε −  +  h e 0.258  Wh/.08 

∆l ε Eq. 3.26 = e Coc cZ0

• T-Junction For a symmetric T-junction structure, the equivalent circuit and parameters can be expressed as follows:

T1a T1b

d1a d1b

Z1a Z1b d2 T2

Figure 3.3 Microstrip T-junction and its equivalent circuit

47 The reference plane displacement and the shunt susceptance can be calculated as [64], 2 Eq. d  Z  f   Z 1 =−0.0551 2 1    1 D  Z  f   Z 3.27 2  21 p   2 2 Eq. d   Z  Z  f  Z  Z 2 =−05..005+0.7exp−1.6 1  + 0.25 1   − 0.17ln1  1 D   Z  Z  f  Z  Z 3.28 1  2 21 p  2  2

2 2 2 Eq.  f   1  Z   d   n2 = 1−π     1  + 0.5 − 2    f  12  Z   D  3.29  p1    2   1  

2 2 Eq. B λ ε + 2  Z Z  f   Z   Z   1 d T 1 = 5.5 r 1+ 0.9 ln 1 + 4.5 1   − 4.4 exp−1.3 1  − 20 2   1 Y D ε  Z Z  f   Z   η   n 2 D 3.30 2 1 r  2 2  p1   2     2 where D, fp, Z0 and λ are respectively the equivalent parallel plate line width, first higher order mode cut-off frequency, characteristic impedance and guide wavelength of the microstrip line. The subscripts 1 and 2 represent series and shunt lines. Expressions for

the calculation of D and fp are given as ηh Eq. 3.31 D = ε e Z 0

f p (GHz) = 0.4Z 0 / h Eq. 3.32 where η=377 Ω and h is in millimeters.

3.2. T-pattern Microstrip Resonator for Thin Film Substrate Characterization As applications for microwave circuitry expand, particularly in portable wireless communications systems and as digital integrated circuit speeds continue to increase, high frequency data on material properties (dielectric constant, loss tangent and attenuation) are very important for the circuit design. Many of the material systems used in electronic packaging have not been characterized for their high frequency performance over the broad range that is of interest to design engineers. Furthermore, new materials are continually being developed that need to be characterized. Typically, low frequency data is available based on capacitor measurements using inductance-capacitance- resistance (LCR) meters or impedance analyzers at frequencies up to approximately 100

48 MHz. High frequency data is often obtained with bulk material measurements in single- frequency resonant cavities. This method is not feasible for thin-film substrate characterization. In order to obtain the broader high frequency data, researchers [65-67] have developed a test method utilizing a microstrip T-pattern resonator circuit which addressed the aforementioned limitations of standard test methods. But the material systems tested are only restricted to the thick-film substrates and printed-wiring board (PCB) laminates. With the development of MMIC technology, on-wafer characterization of thin film substrates for the broader high frequency applications is critical for a successful design. In this study microstrip T-pattern resonator circuit is employed for the polyimide thin film substrate characterization, which would be applicable to any thin film substrates. 3.2.1. General Procedure T-pattern is an open-end transmission-line stub that resonates approximately at odd-integer multiples of its quarter-wavelength frequency. Measurements of the conductor width, thickness, stub length, and conductivity as well as the dielectric thickness, surface roughness, and circuit impedance are made to determine the dielectric constant, loss tangent and attenuation [59-63]. Dispersion at high frequency, open end and junction effects [53,64] are also incorporated into the characterization process as the correction factors to obtain more accurate results. The general procedure is as follows: • To determine material's dielectric constant 1. Based on the measured stub length, line width, and resonant frequency, the effective dielectric constant can be calculated at primary resonance and others. λ c Eq. 3.33 l = n = n n = 1,3,5,Κ ε 4 4 f e 2. Corrections for open-end and T-junction effects are calculated from the line dimensions and measured impedance. This procedure results in a corrected effective dielectric constant from which the material's dielectric constant is computed. 3. At high-order resonant frequencies the calculation is repeated to determine the dielectric constant. However, additional corrections for frequency dispersion

49 are made using the physical, impedance, and primary-resonance data in order to obtain the effective dielectric constant for the given frequency. • To determine material loss tangent The material loss tangent is derived from the Q measurements at each resonant frequency and from the physical and electrical measurements. The total quality factor (Q) is determined by dividing the resonant frequency by the 3-dB bandwidth (BW is a fractional bandwidth). 1 f Eq. 3.34 ==0 Q − BW ff21 The measured Q parameter includes the effects of conductor, dielectric and radiation losses and can be expressed as: 1111 Eq. 3.22 =++ QQcdQ Qr

where Qc = Q due to the conductor losses; Qd = Q due to the dielectric losses;

and Qr = Q due to the radiation losses. The radiation losses may be negligible

since they are very small. Qd can then be expressed as: QQ Eq. 3.35 Q = c d − QQc

Q represents the measured value at each resonant frequency while Qc is calculated from the measured physical properties (line width, thickness, roughness, etc.) as well as the impedance, conductivity, and calculated dielectric

constant. Loss tangent is then derived from Qd, the material dielectric constant

(εr), as well as the effective dielectric constant (εe) at each frequency using the following relationship: ε (ε −1) Eq. 3.36 tanδ = e r ε ε − Qd r ( e 1) 3.2.2. Fabrication of Test Structures For the thin-film polyimide substrates of several tens of microns thick that are used in the 3-D transmitter/receiver module [3] the T-pattern resonators with the primary resonant frequencies at 2.0, 3.33, 4.0 and 10.0 GHz are designed to fit in on 2-inch silicon substrates over which the polyimide thin layers were spun and deposited. The fabrication

50 started with the metallization of silicon substrate with Cr/Au/Cr or Cr/Cu/Cr, then the spin-coating of polyimide precursor and cured for the stable thin film. To minimize CPW to microstrip transition interference, viaholes for grounding the CPWG probe pads were opened using reactive-ion etching (RIE). These were then filled by metal plating. Afterwards a metallization layer was deposited and patterned for the test structures on thin polyimide film. Details of the fabrication process are as follows: a) Preparation of clean silicon substrate Silicon was chosen as the supporting material for circuit fabrication due to its broad availability and outstanding properties [68]. Before proceeding with other fabrication processes, silicon wafer was thoroughly cleaned and dehydrated. The wafer was cleaned with deionized (DI) water, acetone, and methanol alternatively and then rinsed with DI water to remove any chemicals and particles on the surface. Finally, silicon wafer was placed in 120 °C convection oven for 15 minutes for dehydration. This was a simple yet critical step in the entire fabrication process. b) Deposition of conductor ground plane A composite film of Cr/Cu/Cr with thickness 500 Å /1~2 µm/500 Å was sputtered on cleaned silicon wafer surface in the RF discharge chamber to form the bottom ground plane. In the RF sputtering process, ionized metal particles bombard the wafer surface and form a better metal/substrate bonding. Thin layers of Cr films were used here to further improve the adhesion between Cu and the supporting substrate and the subsequent polyimide layers (as discussed in Section 2.2). c) Deposition of polyimide thin film dielectrics As explained in Chapter 2, polyimide layers, (Dupont-PI2611) were deposited by spin-coating of the precursors and then high-temperature hard curing, following the steps outlined in Table 2-4. Different thicknesses were achieved by depositing necessary number of polyimide layers. d) Formation of RIE masking layer Formation of RIE masking layer started with the deposition of an RF sputtered aluminum layer over the polyimide surface. Then the openings for vias were patterned by photolithography followed by Al wet etching. This patterned Al layer served as the RIE masking layer since the thin aluminum oxide layer formed on its

51 surface prevented the metal from being etched in the RIE environment. The aluminum wet etchant is a mixture of HNO3, H3PO4 and CH4COOH and escalated etching temperature were performed with special care to form sharp features. e) RIE of polyimide As discussed in the previous chapter, patterning of fully cured polyimide is achieved by a fluoride-containing RIE process, especially for high aspect ratio patterns. The RIE processing was performed at 30 KHz with RF power of 250 watts,

and gas composition maintained by the flow rate ratio of O2:CF4:Ar at 16:2:2 ml/min and chamber pressure about 200 mTorr. Based on the desired aspect ratio and feature sidewall tapering, different substrate temperatures can be chosen for different etch rates (see Figure 2.10). In this process a typical etching temperature at 40ºC was employed since the aspect ratio was not critical for plating the vias in the next step of copper plating process. f) Plating of via for grounding CPW probe pads The vias formed in the previous step were used to grow the posts to make the CPW probe pads as RF ground. In this way the effect of CPW transition from the microstrip T-resonator were minimized. Before the plating, Al masking layer was stripped by the aluminum etchant. Posts were formed by copper electroplating. Cu electroplating solution had the composition of 10ml H2O: 1 ml H2SO4: 1 g

CuSO4:5H2O crystal. Pulsed constant direct current with 50% duty cycle (5 ms on, 5 ms off) and peak current ranging from 15 mA to 30 mA was applied between two electroplating electrodes. Cu growth rate varied with exposed area and peak current, thus the current density was an important parameter needed to be controlled for the quality of plated copper grain. A typical growth process took several hours with a current density about 5 mA/cm2. g) Formation of microstrip T-type resonator After the posts were plated through the via holes, the wafer was carefully cleaned with DI water and then dehydrated in 120 ºC oven. Before the deposition of Cr/Cu circuit plane on the top of the polyimide, the surface was roughened by half minute of oxygen ashing process in the RIE chamber. This step was critical to make sure the conductor layer had good adhesion to the polyimide surface. After the ashing

52 process, desired thickness of Cr/Cu metal layer was sputtered onto the wafer. Then microstrip T-type resonator structures were patterned by photolithography and metal

etching. Copper was etched by an etchant solution of H2SO4:HNO3:H2O in 1:1:10

volumetric ratio, and Cr was etched with HCl (37% acid):H2O in 1:1 (v/v) solution. In order to activate Cr etching, an aluminum foil was used to touch the wafer surface to lower the electro-potential and trigger chemical reaction. Special attention and cautions were taken to prevent metal over-etching and to preserve good resolution of the T-pattern. As a result of the well-controlled metal patterning, highly satisfactory structures have been obtained. A typical micro-fabricated microstrip T-pattern structure is shown in Figure 3.4. The microstrip lines and CPW were designed to have characteristic impedances of 50 Ω. Measurements were carried out on these test structures using HP (now Agilent) 8510C vector network analyzer with CascadeTM Microtech Air Coplanar GSG microprobes. Proper TRL calibration was performed before S-parameter measurements were made to shift the reference planes to the probe tips.

Figure 3.4 SEM micrograph of microstrip T-pattern fabricated with polyimide substrate

53 3.3. Thin Film Characterization Results and Discussions 3.3.1. Conductor Loss in Thin Microstrip Conductor loss in transmission lines is due to the presence of imperfect conductors and the penetration of fields into the conductors. In the conductor, the magnitude of the fields and currents decay exponentially by an amount of 1/e over a distance of one skin depth (see illustration in Figure 3.5). Normally the thickness of the conductors is greater than several times of the skin depth. In this case, a useful technique for the practical evaluation of attenuation due to conductor loss for TEM or quasi-TEM lines is the Wheeler incremental inductance rule [26]. The conductor loss in microstrip transmission line whose metal thickness is in this range has been discussed in Section 3.1.4. Conductor loss calculation based on the incremental inductance rule is not valid if conductor thickness becomes very thin and on the order of the skin depth, which is the case in this study of the monolithic microwave integrated circuits.

Figure 3.5 Field penetration in microstrip

In order to provide insight into the loss mechanism of a strip structure, recent studies have used numerical analysis to simulate and compute the current distribution over the cross section of the conductor and the relationship to the ac resistance [69-71]. These numerical results have revealed that the skin current of the strip is concentrated toward the ground plane in a microstrip structure and the edge effect is obviously presented in the current density distribution. The penetration of the field into the thin conductor has great impact on the ac resistance when calculating the conductor internal impedance based on the dissipation of power into the conductor [72].

54 In general, the microstrip attenuation due to conductor losses may be computed from the real part of the propagation constant as follows [28, 52]

R γ = α + jβ = jβ 1− j Eq. 3.37 e β e Z 0

β = ω µε ε where Z0 is the lossless microstrip characteristic impedance and e 0 e , the lossless propagation constant. In the thick strip case, the conductor impedance per unit length, R, is given by the

Wheeler’s rule [26] as the summation of Rw, the contribution from the strip large side, Rt from the lateral side and Rg from the ground plane. ∂F R = Z z = R + R + R Eq. 3.38 s ∂n w t g ∂F ∂F ∂F =  z − z  = − z with each of the items, Rw  2 Z s Rt 2Z s  ∂h ∂t  ∂w ∂F 1+ j R = z Z Z = ()1+ j R = g ∂ s s s σ δ h c s = ε η where Fz Z 0 e / , the form factor of Z0 (given by empirical formulas), and σc the

metal conductivity, δs the skin depth. Under the condition of shallow field penetration or at high frequencies, the currents flow only on the conductor surface for which Wheeler’s rule is valid to estimate the conductor loss. As frequency decreases or the conductors become thinner, the field penetrates into the conductors and current distributions become more uniform. At DC, the field penetration is maximum and the current distributions are completely uniform inside the conductors. Therefore, a modification of incremental inductance rule is necessary to approximate this effect. For a thin microstrip, the effect can be accounted by modifying

the calculation of conductor impedance and Reff replaces R in Eq. 3.38 with suitable correction factors as follows [28] R = R C + R C + R C = R + R C eff w w t t g g strip g g Eq. 3.39 2m 1 where C = coth()γ t + w c + 2 ()γ 1 m sinh ct

55 = γ w  = (γ ) Ct coth c  C g coth ct g  2  ∂F − z 1+ j ∂ γ = m 2 = t c δ ∂F ∂F s z − z ∂h ∂t For the wide strip case, i.e. W / h ≥ 1, which is the case of microstrip T-pattern resonator for thin film characterization, a practical formula can be obtained after a lengthy, but straightforward derivation (see Appendix A Derivation of Eq. 3.40 Using MathematicaTM for details). ε ∂ ∂ ∂ ∂ Z s e   Z 0 Z 0  Z 0 Z 0  Eq. 3.40 α = C  − 2  − 2C + C c η  w ∂ ∂ t ∂ g ∂  2Z 0   h t  W h  where

∂Z  W h −W h 1.25 1  Z 2 ε 0 = − e +  0 e G ∂t  t π h  η ∂ 2 ε ∂ 2 ε Z 1 Z 0 e Z W h 1.25 t  Z 0 = − G 0 =  e −  0 e G ∂W h η ∂h  h π h 2  η

1.25h  2h  ln  0.667 π t G = 1+ m 2 =   1.444 +W h 1.25  2h  e W + ()h + t ln  π  t  A comparison of the conductor loss as a function of the ratio of conductor thickness to skin depth for a typical thin film microstrip transmission line, calculated from both of Wheeler’s rule and this modified method, is plotted in Figure 3.6 (also see Appendix B MathematicaTM calculation of conductor loss in thin microstrip). It has clearly shown that as conductor thickness increases and becomes thicker than several times of the skin depth, the conductor losses estimated by these two methods are exactly the same. This is the effective range which Wheeler’s rule is applicable. However, when the conductor thickness decreases and becomes comparable to the order of skin depth or lower, the discrepancy between these methods becomes large due to the exponential increase in the conductor impedance which results from the field penetration. Figure 3.7 shows that there will be a big error in the estimate of conductor loss when the strip is thin

56 and the conventional incremental rule is still used for this evaluation. This modified method will find a lot of applications in MMIC since their metallization is normally thin.

Figure 3.6 Microstrip line conductor loss in dB/cm at 10 GHz versus t/δs (metal thickness/skin depth)

for W=80.5 µm, h=33 µm, εr=3.3 and σc=5.813x107 S/m (copper)

Figure 3.7 Conductor loss error calculated between Wheeler’s rule and its modified model

The results developed here were employed to account for the conductor loss term in the polyimide characterization. And this modification was readily extended for the conductor loss in stripline and CPW transmission lines, which are discussed in Chapter 5.

57 3.3.2. Characterization Results When the conductor loss in thin microstrip has been thoroughly investigated, it clearly shows that the Q factor due to dielectric loss leads to an inaccurate thin film loss tangent if the quality factor due to conductor loss is not accurately evaluated. A typical wideband frequency response of a quarter-wavelength T-pattern resonant structure with a lower primary resonant frequency and its harmonic resonances in higher frequency range is shown in Figure 3.8. Based on several primary-resonance structures designed and fabricated on the polyimide thin film, the wideband frequency properties, such as dielectric constant and loss tangent, can be derived from the measurements as discussed in Section 3.2.1. A typical design combination of microstrip quarter-wavelength T- pattern resonant structures with different primary resonances is tabulated in Table 3-1. In this procedure, physical dimensions of the T-pattern (which includes substrate thickness, metal strip width and thickness, and resonant structure length and width), and the metal strip conductivity (see Appendix C Four-point probe measurement of metal conductivity) and surface roughness were appropriately measured and/or evaluated. In order to accurately determine the resonant frequency and 3dB bandwidth for calculating Q factor, it was extremely important to expand the S-parameter measurements in a small frequency span range. Figure 3.9 shows how to determine the resonant frequency and the corresponding 3 dB bandwidth in a typical S-parameter measurement.

Table 3-1 A typical design of T-pattern structures at different primary resonances 2 GHz 3.33GHz 4GHz 10GHz Characteristic impedance (Ω) 50 50 50 50 Nominal dielectric constant 3.0 3.0 3.0 3.0 Electric length λ/4 λ/4 λ/4 λ/4 Substrate thickness (µm) 33 33 33 33 Metal thickness (µm) 2 2 2 2 Metal conductivity (S/m) 4.098x107 4.098x107 4.098x107 4.098x107 Strip width (µm) 80.5 80.5 80.5 80.5 Physical line length (µm) 24221 14547 12110 4844

58 0

-2

-4

-6 ) B

(d -8 1 S2 -10

-12

-14

-16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Fr e q. (GHz)

Figure 3.8 Frequency response of a quarter-wavelength T-pattern resonant structure with lower primary resonance and its harmonics

Figure 3.9 Expanded measurement of the resonance and 3dB bandwidth

59 Actually the Q factor calculated from the inverse of fractional 3dB bandwidth as in Eq. 3.34 is the so-called loaded quality factor of the resonator structure, which involves the external quality factor from the signal coupling and the unloaded quality factor from the quarter-wavelength resonator. To compute the dielectric constant, the unloaded Q has to be extracted from the measured Q, which is the loaded Q. Since this T- pattern resonator structure can be modeled as an equivalent series lumped-element

resonator coupled to the measurement ports, its unloaded Q0 and loaded QL have the following relationship [73]: Q Q = L Eq. 3.41 0 −() − ⋅ LA 10 1 2 10

where LA is the insertion loss in dB at the resonance. Eq. 3.41 shows that the unloaded Q

for a normal transmission line quarter-wave stub is nearly equal to the loaded Q since LA is normally high at the resonance. A MATLAB program was developed to compute the thin film dielectric constant and loss tangent from the measured results by incorporating into the program with the corrections of discontinuities (open end and T-junction), loaded quality factor and thin conductor loss (Refer to Appendix D MATLAB program for thin film characterization for the details.). Using various combinations of T-pattern microstrip resonator structures, a wide frequency range of relative dielectric constant from 1.8 GHz to 18.8 GHz for the polyimide PI2611 thin film were obtained. The results are summarized in Figure 3.10. These relative dielectric constant results were slightly larger than the value in the product datasheet [51], which is believed to be a low-frequency data and for bulky material other than thin films. As it has been discussed before, polyimide is an amorphous material and its dielectric constant value depends on the manufacturing process and physical conditions. Thus, it is extremely important to characterize the polyimide thin film properties when using it for 3D-MMIC integration and interconnection packaging.

60 5.0

nt 4.5 a t ns

o 4.0 c ic r t

c 3.5 e l die

e 3.0 v i t la

e 2.5 r

2.0 0 5 10 15 20 Fr e q. (GHz)

Figure 3.10 Measured dielectric constant for PI2611 thin film substrates.

In the RF circuit design, the dielectric constant value is very important because it is used to determine the characteristic impedance and phase velocity. This is the key to obtain an accurate design and an operational circuit. A specific application should also have the right power budget infrastructure which consists of certain power consuming and generating components. An accurate knowledge of the loss tangent value of substrates is of significant importance to plan the correct power budget for an applicable RF system. By appropriately separating the loss contributions from various sources in the T-pattern resonator test structures, the loss tangent which accounts for the dielectric loss in the substrates can be accurately determined from the resonance Q measurements. Figure 3.11 shows the measured loss tangent for the fully-cured PI2611 thin film in the frequency range from about 2 GHz to almost 20 GHz. It clearly shows that in the high frequency applications dielectric loss from thin films makes a significant contribution.

61 0.030

0.025

t 0.020 en g n

a 0.015 ss t

o 0.010 L

0.005

0.000 0 5 10 15 20 Freq. (GHz)

Figure 3.11 Measured loss tangent for PI2611 thin film substrates

The loss tangent measurement results obtained in this research are compared with the values in the literature and illustrated in Figure 3.12. A fairly good agreement is clearly shown. This also verifies the validation of loss tangent measurement and calculation in this study. Additionally, Figure 3.12 shows that the correction of skin- depth effect on the estimate of thin conductor loss is critical to obtain an accurate set of dielectric loss tangent results. Since the thin conductor of the order of skin-depth thickness results in higher attenuation than that from conventional calculation, if it is not differentiated from the loss of dielectric substrate, dielectric loss will end up higher than the real one. This effect is clearly shown in this plot. At lower frequency, the error for the loss calculation becomes very large if the conventional method is still used to account for conductor loss. The exponential change of the erratic loss points varying with frequency indicates a similar exponential increase in the conductor loss as conductor thickness over skin depth ratio decreases. The same effect has been plotted in Figure 3.6 as well.

62 0.20 0.18 Polyimide data from reference [67] PI2611 measured after skin-depth correction 0.16 PI2611 measured before skin-depth correction 0.14

nt 0.12 nge

a 0.10 t s s 0.08 Lo 0.06 0.04 0.02 0.00 0 5 10 15 20 Freq. (GHz)

Figure 3.12 Comparison of PI2611 polyimide thin film loss tangent results with or without conductor loss correction and those from literature [67]

Having determined the PI2611 loss tangent and compared to the literature results, these results can be used to verify the conductor loss model developed to evaluate conductor loss in the thin strip case. In the fabrication process of characterizing T-pattern structures, relatively thin metallization layers were used for both the ground plane and circuit plane. It is inevitable to have the skin-depth effect on the calculation of conductor loss term when evaluating the whole loss contributions from both dielectric and conductor losses. As discussed in the previous chapter, in order to enhance the adhesion between metal layer and polyimide substrate, a thin layer of chromium (Cr) was used to improve the adhesive strength between the copper (Cu) layer and the PI2611 thin film. 7 Due to the lower conductivity of chromium layer (pure Cr σc=3.846 x10 S/m), the copper metal layer conductivity will be much lowered from pure metal (pure Cu σc=5.813 x107 S/m). Since there is also a certain thickness of metal oxide layer formed on the metal surface, the circuit layer conductivity becomes even lower after the fabrication process. The measured metal layer conductivity from four-point probe was about 2.67

63 x107 S/m. The lower conductivity of the metal layer allows more penetration of the field into the conductor and thus the stronger skin-depth effect will result. This can be explained by the definition of skin depth δs as follows: 1 δ = Eq. 3.42 s π µσ f c

Eq. 3.42 also shows that for a metal layer with certain thickness, as the frequency is lowered in the application, field penetration increases due to increase in skin depth, thus the effect of skin depth becomes the stronger on the conductor loss. To account for the strong field penetration and thin strip, proper modification on conductor impedance as in Eq. 3.39 had to be incorporated into the evaluation of the conductor loss. Otherwise, the conventional Wheeler’s incremental inductance rule based on thick strip will gave rise to erratic results. This effect has been clearly shown in both Figure 3.13 and Figure 3.14.

0.8

0.7

m 0.6 /c B 0.5 d in

s 0.4 s 0.3 l lo a t

e 0.2 Measurements m Modified model 0.1 Wheeler's rule 0 0 5 10 15 20 freq. (GHz)

Figure 3.13 Conductor loss varying with frequency in the thin microstrip line with the strip W=76.5 µm, 7 t=1.4 µm on the PI2611 thin film h =35 µm (σc=2.67x10 S/m)

Figure 3.13 shows the conductor loss variation as a function of frequency for a thin microstrip transmission line. It is clearly shown that the skin depth becomes comparable to the strip thickness or even larger than the strip thickness at lower frequencies and only the modified model can accurately estimate this effect. As

64 frequency increases, the skin depth decreases and becomes smaller than the strip thickness. In this case both Wheeler’s rule and its modified model can produce fairly accurate evaluation of conductor loss. This phenomenon can be further illustrated in Figure 3.14 by the conductor loss varying with the ratio of strip thickness to skin depth in the frequency range of interest. It shows that as the conductor thickness becomes approximately greater than twice of the skin depth, both conventional Wheeler’s rule and the modified model will work well in the evaluation of conductor loss. Refer to Figure 3.7 for the percentage of possible error when using these methods for different situations. But, in order to reduce the conductor loss, conductor thickness should be of several times of skin depth and even higher. Figure 3.6 shows the trend of conductor loss reduction with increasing of metal thickness.

0.8

0.7

m 0.6 /c B 0.5 d in

s 0.4 s

l lo 0.3 a t Measurements

me 0.2 Modified model 0.1 Wheeler's rule 0 0 0.5 1 1.5 2 2.5 t/skin-depth

Figure 3.14 Conductor loss varying with t/skin-depth ratio in the thin microstrip line with the strip 7 W=76.5 µm, t=1.4 µm on the PI2611 thin film h =35 µm (σc=2.67x10 S/m)

3.3.3. Error Analysis for εr Measurement Now let’s consider the measurement accuracy in the relative dielectric constant characterization. To simplify the analysis, the measurement error is estimated based on h c 2 Eq. 3.3. Let r = 12 , and ε = (from Eq. 3.33), so it becomes W e 16 f 2l 2

65 ε − + 1 2 e 1 ε = 1+ r r Eq. 3.43 + 1 1 1+ r ε If at first considering these two variables ( r, e ) as independent variables, the relative error of measured dielectric constant can be expressed as ∆ε ∂ε ∆ε ∂ε ∆ r = r e + r r ε ∂ε ε ∂r ε r e r r Eq. 3.44 ∂ε ε  ∆ε  ∂ε r  ∆r  = r e  e  + r ∂ε ε  ε  ∂ ε   e r  e  r r  r  ∆ε ∆r And using the error propagation theory, e and are readily calculated as ε e r ∆ε ∆f ∆l e = 2 + 2 Eq. 3.45 ε f l e ∆r ∆h ∆W = + Eq. 3.46 r h W

Thus

∆ε ∂ε ε  ∆f ∆l  ∂ε r  ∆h ∆W  r = r e 2 + 2  + r + ε ∂ε ε   ∂ ε   r e r  f l  r r  h W  Eq. 3.47 ∆ ∆ ∆ ∆ =  f + l  +  h + W  C f ,l 2 2  Ch,W    f l   h W  In literature [74], the following relationship was assumed, which is only the special case ≈ ≈ of Eq. 3.47 with the values of C f ,l 1and Ch,W 0. ∆ε ∆ε r ≈ e Eq. 3.48 ε ε r e

Now these coefficients have to be examined before the overall error for the dielectric constant is estimated. Readily, the derivatives can be obtained from Eq. 3.43, ∂ε 2 r = Eq. 3.49 ∂ε 1 e 1+ 1+ r

66 ε − r 1 ∂ε 2 ()1+ r 3 r = Eq. 3.50 ∂r 1 1+ 1+ r

ε ε In the evaluation of C f ,l and Ch,W , the nominal measured values of r and r (or e ) can be used to determine the contribution of each term. By combining Eq. 3.43 with the derivative (Eq. 3.49), the coefficientC f ,l , which weighs the contribution of the errors from resonant structure length and frequency measurements, can be expressed as follows ∂ε ε C = r e f ,l ∂ε ε e r 2ε Eq. 3.51 = e 1 2ε −1+ e 1+ r ε >> ε >> In general, C f ,l is greater than unity. Only under the conditions of e 1(i.e. r 1) or r << 1 (very wide strip), can this coefficient approach unity. So the assumption made by Pozar et al. [74] is difficult to meet in many applications. Now let us consider as an example the T-pattern measurements made on the PI2611 with thin metal strips. For the microstrip structure, h = 35 µm and W = 76.5 µm and the primary resonance is at 1.825 GHz. The calculated values for the quarter- ε = ε = wavelength T-pattern are e 2.874 and r 3.681, then the coefficients are 2× 2.874 C = = 1.1182 f ,l 1 2× 2.874 −1+ 35 1+12 76.5

3.681−1 3  35  35 2 1+12  12  76.5  C = 76.5 = 0.0868 h,W 1 3.681 1+ 35 1+12 76.5

67 Therefore, to a first-order approximation, Pozar’s assumption significantly simplifies the error analysis. The calculation has shown that the error contributions from resonant frequency and structure length measurements are much bigger than those from substrate thickness and conductor width measurements. For the PI2611 T-pattern measurement, the error of the calculated dielectric constant can be expressed approximately as ∆ε  ∆f ∆l   ∆h ∆W  r ≈ 1.122 + 2  + 0.08 + Eq. 3.52 ε     r  f l   h W  In this process of dielectric constant characterization vector network analyzer measurement of resonance frequency and S-parameters can achieve very high accuracy as long as the frequency range and corresponding calibration are accurate enough. Because the photolithographic microfabrication process possesses very high resolution of preserving the dimensions of final structures, the error from the measurement of resonator length can be negligible. So it is concluded that the on-wafer measurement of thin film dielectric constant using microfabricated T-pattern microstrip resonator structures possesses very high accuracy. As for the measurement accuracy in determining loss tangent, we know that there is strong skin-depth effect on the conductor loss when metallization layer is thin. So the measurement error of the conductor thickness contributes mostly to the error of dielectric loss tangent. And it is a very sensitive parameter, though an analytical expression of this error contribution will be very difficult to obtain because of the complexity of conductor loss model.

3.4. Summary In conclusion, thin film dielectric substrates, such as spin-coated and thermally cured polyimide thin film for 3D-MMIC applications, can be successfully on-wafer characterized by using quarter-wavelength T-pattern microstrip resonator structures. Since the microfabrication process utilizes the photolithography fabrication technology widely used in microelectronics and the measurement method adopts sophisticated vector network analyzer, it achieves very high accuracy in the characterization of substrate dielectric constant.

68 In order to correctly evaluate the conductor loss in thin microstrip lines, a modified conductor loss model was derived from original Wheeler’s rule to account for the field penetration as strip thickness approaches the skin depth or even lower. Based on the correct estimation of conductor loss in microstrip T-pattern resonator structures, fairly accurate extraction of dielectric loss tangent for the polyimide thin film was obtained. Meanwhile, experimental results also verified the validity of the modified conductor loss model in evaluating thin microstrip lines. It is shown that as the conductor thickness becomes approximately greater than twice of the skin depth, both conventional Wheeler’s rule and its modified model agree with each other very well on the conductor loss estimation.

69 Chapter 4 FEM Simulations of 3-D MMIC Interconnects

4.1. Maxwell’s Equations Maxwell’s equations are a set of fundamental equations governing all macroscopic electromagnetic phenomena. The equations can be written in both differential and integral forms, but here only the equations in differential form will be presented since they lead to differential equations to be dealt with by the finite element method. The time-dependent Maxwell's equations in differential form for general time- varying fields can be expressed as follows:

∂B Eq. 4.1 ∇ × E = − ∂t ∂D Eq. 4.2 ∇ × H = + J ∂t ∇ ⋅ D = ρ Eq. 4.3 ∇ ⋅ B = 0 Eq. 4.4 where E = the electric field vector, in V/m. H = the magnetic field vector, in A/m. D= the electric flux density vector, in Coul/m2. B = the magnetic flux density vector, in Wb/m2. J = the electric current density, in A/m2. ρ = the electric charge density, in Coul/m3. Another fundamental equation, which is known as the equation of continuity, can be written as ∂ρ Eq. 4.5 ∇ ⋅ J + = 0 ∂t Assuming an e jϖt time dependence, Maxwell’s equations in phasor form then become

70 ∇ × E + jωB = 0 Eq. 4.6 ∇ × H = jωD + J Eq. 4.7 ∇ ⋅ J + jωρ = 0 Eq. 4.8 In linear, isotropic nondispersive materials, the associated constitutive relations are B = µH Eq. 4.9 D = εE Eq. 4.10 J = σE Eq. 4.11 where µ is the magnetic permeability in H/m, ε is the electric permittivity in F/m, and σ is the electric conductivity in S/m. Eq. 4.11 is the basic Ohm’s law. With the aid of constitutive relations, Maxwell’s equations can be simplified into the following vector wave equations, which are often used to incorporate the finite element method. Eq. 4.12 ∇ ×  1 ∇ ×  −ω 2ε = − ω  E c E j J i  µ 

 1   1  Eq. 4.13 ∇ ×  ∇ × H −ω 2 µH = ∇ ×  J   ε   ε i   c   c  σ In the above, J is an impressed or source current, and ε (ε = ε − j ) results from the i c c ω combination of the conduction current (σE ) and displacement current ( jωD ); for ε ε simplicity is still used to denote c , a complex number. Solving the differential equations given above in a domain of interest, many solutions can be obtained, but only one of them is the correct, real solution to a specific problem. The real problem should contain specific boundary conditions associated with the domain, which constrain the real solution. In other words, a complete description of an electromagnetic problem should include complete information about both differential equations and boundary conditions. Different domain of interest and different boundary conditions associated with it could define the properties of certain electromagnetic problems. In many cases, seeking an analytical solution to these problems is impossible and numerical analysis has to be performed to approximate the real solutions. The finite

71 element method is one of the most popular and efficient numerical methods, which provide full-wave solutions to the electromagnetic phenomena.

4.2. FEM Formulation for Electromagnetics The finite element method (FEM) is a numerical technique for obtaining approximate solutions to boundary-value problems. The principle of the method is to replace an entire continuous domain of interest by a number of subdomains in which the unknown function is represented by simple interpolation functions with unknown coefficients. Thus, the original boundary-value problem with an infinite number of degrees of freedom is converted into a problem with a finite number of degrees of freedom, or in other words, the solution of the whole system is approximated by a finite number of unknown coefficients. Then a set of algebraic equations or a system of equations is obtained by applying the Ritz variational or Galerkin procedure [75], and finally, solution of the boundary-value problem is achieved by solving the system of equations. Therefore, a finite element analysis of a boundary-value problem should include the following basic steps: 1. Discretization or subdivision of the problem domain of interest into a finite number of subdomains 2. Selection of interpolation functions which form the solution space 3. Formulation of the system of equations which are derived from the governing differential equations and the boundary conditions 4. Solution of the system equations Now our attention is turned to the specific application of finite element analysis in electromagnetic phenomena. Considering a source-free region V which contains homogeneous materials in any geometric shape, the following vector wave equations can be easily obtained E E Eq. 4.14 ∇ × ∇ ×   − 2   =   k   0 H H where k = 2π/λ. The time-harmonic fields are considered and therefore the numerical procedure is developed in the frequency domain. Using Fourier transform, the solution to

72 Maxwell’s equations in frequency domain can be converted to the solution in time domain. To find the fields in the solution space, the entire domain (V) is discretized into many subdomains (Ve) while the unknown E and H fields are expanded accordingly. In the approximate solution space, the vector electric and magnetic fields are represented by the expansion of edge-based vector basis functions defined in the tetrahedral subdomains. This methodology was proposed in [76] and successfully applied to the cavity and scattering problems [77-79]. The schematic diagram of a tetrahedron for the definition of the basis functions with nodes and edges is shown in Figure 4.1. Once the system of equations has been formed and solved, we can then compute the desired parameters, such as capacitance, inductance, characteristic impedance, S- parameters, and scattering or radiation patterns and display the result in forms of curves, plots, or color pictures, which are more meaningful and interpretable. The finite element method is one of the most popular and efficient numerical methods, which provide full-wave solutions to the electromagnetic phenomena. There is no single numerical method which will suffice for solving all the field problems associated with microwave engineering. Table 4-1 shows some numerical methods commonly used for solving microwave engineering problems with some indications of their strengths and weaknesses.

Figure 4.1 Tetrahedral element with denoted nodes (1 to 4) and edges (E1 to E6). ri1 and ri2 are node vectors and r is an arbitrary vector which lies in the tetrahedron.

Table 4-1 Common Numerical Methods for Microwave engineering [80].

Field Solvers Class Interior Exterior Finite difference- Differential time Well suited for Requires radiation- time domain domain; no matrix orthogonal geometry absorbing boundary (FDTD) inversion conditions

Transmission-line Differential time Well suited for Requires radiation- modeling domain; no matrix orthogonal absorbing boundary (TLM) inversion; circuit geometry; readily conditions modeling couples to circuits Method of Integral frequency Well suited to Well suited moments domain; dense homogeneous linear (MoM) matrix materials

Finite element Differential normal Well suited to Requires radiation- method frequency domain; inhomogeneous absorbing boundary (FEM) sparse matrix nonlinear materials conditions

4.3. FEM Simulations of 3-D Interconnects Basic interconnect structures were simulated using HFSS (Version 7 from Ansoft, Inc.), a FEM software package. The dimensions of stripline were calculated first at 10 GHz with nominal 50 Ω characteristic impedance using HP Libra. Initially losses introduced by the materials were ignored. Metals were treated as perfect electrical conductors (PEC) and metal layers as sheets without thickness. This was helpful to establish an equivalent circuit model for the vertical interconnects. Figure 4.2 shows a typical structure that was used. In this plot, our attention was focused on the vertical interconnect and trenches (side walls connecting ground planes along the edges of the dielectric region). The magnified region is the stripline-microstrip- CPWG transition for making measurements. To test such a structure, there were inherent difficulties in accessing the striplines at different levels. Special ports had to be designed to access these transmission lines. Special care was taken in the design of the processing steps so that these ports would be accessible for characterization purposes.

74 Gnd plane polyimide A-A' Gnd plane stripline via Gnd plane

View from A-A' cutplane

Side walls

B-B'

Stripline-microstrip-CPWG transition Side view at B-B' plane

Figure 4.2 Geometry of the post vertically connecting stripline to stripline transmission lines. Side walls (trenches) are placed along the sides. Stripline-microstrip-CPWG transitions were designed for measurement ports.

The dielectric thickness between the adjacent ground planes was chosen 44 µm.

The width of center strips was 24 µm and each strip was 1012 µm long (~λg/16, including the via). The height of via was 44 µm. Two shapes of via and thruhole were considered, for the vertical posts: a cylindrical (d x H = 24 µm x 44 µm) or a cuboid (L x W x H = 24 µm x 24 µm x 44 µm) via, and for the thruholes: a circular (d = 50µm) or square (L x W = 50 µm x 50 µm) opening were chosen. The overall simulation size was 960 µm x 2000 µm x 88 µm. For comparison, via-hole interconnects with all the same structure as others including the confining trenches were also simulated to show the sidewall effects on the signal transmission. In the following subsections, sidewall confinement effects on the viahole module, via and thruhole shapes and others will be discussed in detail. 4.3.1. Sidewall Confinement Effects A figure-of-merit advantage of using discretization techniques such as FEM in the complex high frequency structure simulation is its capability of visualizing the fields and power/energy distributions around these structures. The physical view can enhance qualitative understanding of the electrical performance of the components under study. Figure 4.3 shows the comparison of the plotted electrical field magnitude around the via connection region (a) with the confining trenches or (b) without them. The fields are not confined without the side walls as a result of possible parallel plate mode excitation between the two ground planes. For the trenched case, the conducting side walls confine

75 the fields. The effect can also be shown by a comparison of the viahole module insertion and return losses, and the power loss factor calculated from Eq. 4.15. = ( − 2 − 2 ) Ploss 10log 1 S11 S 21 Eq. 4.15

The simulated viahole modules with or without confinement walls have cylindrical via and circular thruhole openings in the center ground plane. As can be seen from Figure 4.4, insertion loss of unconfined viahole module is higher than the confined system, and the return loss differs in opposite direction. The corresponding loss factor is shown in Figure 4.5. For the confined case the loss factor looks like a noise floor (FEM accuracy limit). Absolute values were used because of possible numerical errors and precision limitations. The confined viahole module provides a significant measure in multiple chip module (MCM) design and in MMICs to prevent the signal interference between the densely integrated circuit components. For the trench or sidewall bounded circuits all the fields are confined in their own regions, therefore there is no power leak outside the area of the module and the power loss is minimized. Because of the trenches, the interference between the closely placed components is eliminated. The significance of confinement walls in high-density electronic packaging is obvious.

(a)

(b)

Figure 4.3 Effects of the confining trenches on the electrical field around via-holes: (a) with trenches, (b) without trenches.

77 0 -18 S11, cyl-cirthru, w ith sidew alls -19 S11, cyl-cirthru, w ithout sidew alls -0.01 -20 -0.02 -21 ) B B) d d -22 (

-0.03 . -23 Mag. ( -0.04 Mag -24 -25 -0.05 S21, cyl-cirthru, w ith sidew alls -26 S21, cyl-cirthru, w ithout sidew alls -0.06 -27 8 9 10 11 12 8 9 10 11 12 Fre q. (GHz) Fre q. (GHz)

(a) (b)

Figure 4.4 Sidewall confinement effects on the viahole (a) insertion loss and (b) return loss.

0 loss factor without sidewalls -20 loss factor with sidewalls

-40

-60 Mag. (dB)

-80

-100 8 9 10 11 12 Freq. (GHz)

Figure 4.5 Loss factors for the confined and unconfined viaholes.

4.3.2. Via and Thruhole Shape Effects To build a viahole for a multilayer circuit, the physical structure of the via and thruhole should be considered that best fit in the entire design and thus provide a superb circuit performance. With this in mind combinations of viahole modules with two common practical shapes of via (cylindrical or cuboid) and thruhole (circular or square) structures have been studied. The insertion and return losses of the simulated via-thruhole structures are plotted in Figure 4.6. By taking a closer look at the via shape and through hole combinations, a conclusion can be drawn that a cylindrical via and a circular

78 thruhole both provide a lower insertion loss and a better return loss. The reason may come from the geometric structures of cylindrical and circular shapes, which have lower degree of discontinuity than those of cuboid and rectangular shapes. When mixed combinations of via and through hole shapes were considered, via shapes dominated.

0 -22 S21, cyl-squthru S21, cyl-cirthru S21, cub-squthru -23 S21, cub-cirthru -0.01 ) -24 (dB g. -25 Ma -0.02 Mag. (dB) S11, cyl-squthru -26 S11, cyl-cirthru S11, cub-squthru S11, cub-cirthru -0.03 -27 8 9 10 11 12 8 9 10 11 12 Fr e q. (GHz) Fre q. (GHz)

Figure 4.6 Insertion and return losses for different via-thruhole combinations.

For a numerical comparison, the simulation results of all the interconnects with different structures at frequency of 10 GHz were summarized in Table 4-2. Via module 1 to 4 had the confining trenches and via module 5 did not. As expected, confining trenches in each case also lowered the insertion loss significantly. The typical surface current distributions on the via surface, and on the center ground plane and the strips are shown in Figure 4.7. Thus the combination of cylindrical via and circular through hole gave rise to the lowest insertion loss in this study.

Table 4-2 Results of different via-thruhole combinations

Via module Via shape Thruhole shape Insertion loss (dB) 1 Cylinder Square 0.01480 2 Cylinder Circle 0.01459 3 Cuboid Square 0.01728 4 Cuboid Circle 0.01646 5* Cylinder Circle 0.03132 * Without side walls.

(a)

(b)

Figure 4.7 Surface current distributions on (a) the via surface only, (b) besides the via, on the strips and separate ground plane.

80 4.3.3. Stripline Connecting Angle Effects In high density packaging of electronic devices, it is inevitable to have different directions of connecting the vertical interconnects other than the module shown in Figure 4.2. In this case the connecting angle between the upper and lower striplines is defined as 180°, which is the angle between the axes of transmission lines if projected to the same plane. In current study, two other connecting angles between the transmission lines have been investigated, zero and 90 degrees (shown in Figure 4.8). The 0° via module is referred to a stripline transmission line passes through a ground plane by the via and runs in the backward direction, and the 90° via module runs to the side direction. For all the cases the via modules are similar to the structure shown in Figure 4.2, but the confining sidewalls were changed correspondingly to preserve the structure shieldings. The simulation results of via modules with different connecting angles for the transmission lines are shown in Figure 4.9, for the cylinder-circle via-thruhole configuration. The plotted values of the scattering parameters have been de-embedded to the same reference planes with respect to the via in distance. It is evident that the sideway running of striplines through the via connection (90° connecting angle) is the worst case in the insertion and return losses, and the two parallel connection of the striplines through the viahole cases (0° and 180° connecting angles) have the similar lower return loss and hence lower insertion loss. It is also a good indication that the losses associated with all these three configurations are not dramatically large. Thus using different angle of connecting the transmission lines by the viahole will not provide a large difference in a circuit performance. However, this result is quite different from the reported result for the microstrip transmission lines connected by a viahole [18]. In [18], the 90 degree connecting angle is the worst case in electric performance, and produces greater loss because of the radiation effect.

Figure 4.8 The via modules with different connecting angles.

81 -26 0 S11, cyl-cirthru, 180 degree -27 S11, cyl-cirthru, 90 degree -28 S11, cyl-cirthru, 0 degree -0.002 -29 -30 -31 -0.004 -32 Mag. (dB) Mag. (dB) -33 -0.006 -34 S21, cyl-cirthru, 180 degree -35 S21, cyl-cirthru, 90 degree S21, cyl-cirthru, 0 degree -36 -0.008 8 9 10 11 12 8 9 10 11 12 Fr e q. (GHz) Fre q. (GHz)

Figure 4.9 Insertion and return losses for the via modules with different connecting angles.

4.4. Equivalent Circuits for Ideal Vias It has been shown that full-wave simulation methods like FEM provide us with the details involved in discontinuities of vertical interconnects in multilayer circuit packaging. However, in most of the cases for circuit design this information is redundant and too expensive to obtain. The equivalent circuit, which approximates the discontinuity structure, can provide intuitive insight into the interconnects instead of every detail. It is easy to be incorporated into the circuit simulator, and cheaper to implement than full- wave solution in terms of computer memory and computation time. But most important is that the equivalent circuit should have the ability of approximating the behavior of interconnect discontinuity in the design frequency range. The component values of the equivalent circuit lumped elements can be obtained in two different approaches. One approach is based on the full-wave solution and using the field solutions to derive the component values [20]. The other approach is based on the derivation of an appropriate equivalent circuit by fitting the scattering parameters obtained from full-wave solution in the frequency range of interest [19]. In this research the component values of the equivalent circuit lumped elements are derived using the second approach, in which a circuit simulation was made to match the scattering parameters of the equivalent circuit to the FEM simulation results (Refer to Appendix E

82 Procedure for extracting equivalent circuit using HP LIBRA Unix Version (v6.1) for the details). For simplicity, FEM simulations of the interconnects in the last section did not include the port transitions for measurement. Meanwhile, the materials were set as lossless and the metals as perfectly conducting and infinitely thin. Thus the vertical interconnect structure and its equivalent circuit can be illustrated in Figure 4.10. The striplines have been modeled as ideal transmission lines, and the via between the

striplines has been modeled as a π-type lumped-element circuit consisting of Ce1, Ce2 and

Le. It is easy to note that Le represents the inductance introduced by the via, and Ce1 and

Ce2 represent the capacitances between the via and the upper and lower ground planes and separated by the central ground plane, respectively. If the structure possesses high symmetry as in Figure 4.10 (a), Ce1 and Ce2 are equal, and Z01 and Z02 for the transmission lines of the same type and characteristic impedance.

(a) (b)

Figure 4.10 (a) Geometry of the post connecting vertically stripline to stripline transmission lines. (b) equivalent circuit of a vertical post.

Figure 4.11 shows the scattering parameters obtained from FEM simulation and the equivalent circuit typically for a via-hole module, with a cylindrical via and a circular thruhole. There is a good agreement between the numerical simulation and the equivalent circuit model in the frequency of interest. In Section 4.3.2, the via and thruhole shape effects have been studied by the full-wave solutions using FEM simulator. As has been pointed out that the cuboid via and square thruhole is the worst case in losses because of high degree of discontinuity in physical shapes. From the equivalent circuit components in Table 4-3, it is clear that the cuboid via shape has higher inductance than the

83 cylindrical via. If a square thruhole is also included the inductance is the highest, which explains why the via and thruhole shapes are important. In all these cases, the differences in capacitance are relatively small. Results have clearly indicated that the effect of realistic viaholes is mainly capacitive [18, 81].

Figure 4.11 Scattering parameters of cyl-cirthru via-hole from FEM simulation and equivalent circuit

Table 4-3 Equivalent circuit components for different viahole modules Via 1 Via 2 Via 3 Via 4 Equivalent Le (pH) 20.32 20.12 25.60 23.91 circuit in Ce1= Ce2 (fF) 6.013 6.236 5.295 5.798 Figure 4.10 (b) Total L (pH) 20.32 20.12 25.60 23.91 Total C (fF) 12.026 12.472 10.590 11.596 Equivalent L/2 (pH) 10.16 10.06 12.80 11.96 circuit in Cg (fF) 7.878 7.513 5.931 6.250 Figure 4.12 (a) C/2 (fF) 2.074 2.478 2.330 2.672 Total L (pH) 20.32 20.12 25.60 23.92 Total C (fF) 12.026 12.469 10.591 11.594

Also shown in Table 4-3 are the component values of another equivalent circuit model (Figure 4.12 (a)). In comparison of the total inductance and capacitances, there are no differences between these two equivalent circuit models. By doing a simple transformation between the T- and π-type lumped circuits as shown in Figure 4.12 (b), it

84 can be shown that both of the equivalent circuit models are actually the same. The difference is that the individual capacitance is referred to different portion of the viahole

geometry. Comparing the components in Table 4-3, Cg can be attributed to the capacitor between the via and the central ground plane, and C/2 is the capacitance between the via and the upper or lower ground planes.

(a)

(b)

Figure 4.12 Another equivalent circuit (a) and the transformation between T- and π-type circuits (b)

Figure 4.13 Vertical interconnect through a ground plane of finite thickness and its equivalent circuit

When the via passes through a ground plane with a finite thickness, there is a capacitor formed between the via surface and the thruhole cylindrical surface of the ground plane height. Quasi-statical studies have shown that this capacitance is not different from the capacitance of a cylindrical coaxial capacitor [81, 82]. In this case, the equivalent circuit model as shown in Figure 4.12 (b) can be employed to derive the

capacitances between the via and ground planes using the fixed Cg value (see Figure 4.13). However, there is no theoretical difference between the equivalent circuit models

85 in Figure 4.10 (b) and Figure 4.12 (a) referring only to the total lumped element values. In the case of 3D MMIS developed here, the metal thickness is generally within a few micrometers, thus this kind of effect can generally be ignored. In previous section, the effects of connecting angle of the transmission lines to the viahole were studied. It was shown that the 90° connecting angle introduced bigger loss. The difference between equivalent circuit components will now be addressed. Table 4-4 shows the component values if a combination of the inductance and capacitances associated with the viahole when the whole frequency range is considered. For the 90° connecting angle case, the values are the best curve-fitting results. They are not perfectly matched to the FEM simulation results in the 8 to 12 GHz frequency range (see Figure 4.14). However, the two parallel cases (see Figure 4.11 and Figure 4.15) have shown a very good matching between the equivalent circuit and the FEM simulations. Obviously the bigger losses as shown in Figure 4.9 are related to the higher inductance associated with this configuration compared with the others. It is also evident that the equivalent circuit components have frequency dependence since a single combination of inductance and capacitance can not fit the simulation result. The dependence of the total inductance and capacitance on frequency is plotted in Figure 4.16 for the frequency range of 8 to 12 GHz.

Figure 4.14 Scattering parameters of cyl-cirthru viahole (90° connecting angle) from FEM simulation and equivalent circuit

Figure 4.15 Scattering parameters of cyl-cirthru viahole (0° connecting angle) from FEM simulation and equivalent circuit

Table 4-4 Equivalent circuit components for different connecting angles at frequency 8-12 GHz

Connecting angle Le (pH) Ce1= Ce2 (fF) Total C (fF) 180° 20.12 6.236 12.472 90° 25.51 4.849 9.698 0° 20.44 5.796 11.592

28 11

27 10

9 Inductance (pH) 25 Capacitance (fF)

24 8 8 9 10 11 12 8 9 10 11 12 Fr e q. (GHz) Fr e q. (GHz)

Figure 4.16 Equivalent circuit components (total inductance and capacitance) of cyl-cirthru viahole (90° connecting angle) as a function of the frequency

87 4.5. Design Considerations The main purpose of studying the vertical interconnects in 3D MMICs is to understand their performance in the high-density packaging and high-speed circuit integration. As for the circuit design, this understanding enables the design engineers to incorporate the effect of interconnect into the whole system design and its implementation. For this purpose, equivalent circuits of vertical interconnects allow design engineers to approximate the performance of their discontinuities instead of resorting every detail from the full-wave solutions, which are more expensive and time- consuming. The effort has been based on the derivation of equivalent circuit lumped- element components by means of quasi-statical methods [81-86] and full wave methods [19, 21, 23, 87]. Now we consider the viahole design by making use of the equivalent circuit for the ideal case. In circuit theory representation of a lossless transmission line, the characteristic impedance of the line is based on the unit length quantities of series inductance (L) and shunt capacitance (C) [52]. Since the physical dimension of a via is usually very small with respect to wave length, the characteristic impedance of the via in Figure 4.10 (b) can be defined by the lumped-element equivalent circuit components as follows L Z = e e + Eq. 4.16 Ce1 Ce2 If a TEM wave propagates from the stripline 1 to stripline 2 through the via and if stripline 2 is terminated with a matched load (Z02), the voltage reflection coefficient at the T plane looking into the via from stripline 1 is given by

Z ()1−ω L C − Z (1−ω 2 L C )Z Z   ω 2 L C   ω 2 L C  02 e e2 01 e e1 +1− 01 02 C 1− e e2  + C 1− e e1  ω  e1  e2   j Le Le  2 2  Γ =      Eq. 4.17 Z ()1−ω L C + Z (1−ω 2 L C )Z Z   ω 2 L C   ω 2 L C  02 e e2 01 e e1 +1+ 01 02 C 1− e e2  + C 1− e e1  ω  e1  e2   j Le Le   2   2  ω = π ω 2 (+ )<< where ω is the angular frequency, 2 f . Usually, Le Ce1 Ce2 1 can be satisfied. The above expression then reduces to Z − Z + jωL − jωZ Z ()C + C Γ = 02 01 e 01 02 e1 e2 + + ω + ω ()+ Eq. 4.18 Z 02 Z 01 j Le j Z 01Z 02 Ce1 Ce2 The lowest reflection will occur when

88 = Z e Z 01Z 02 Eq. 4.19 ω << |Γ| is minimized since it is normally true that j Le 1 , and Z − Z Γ ≈ 02 01 + Eq. 4.20 Z 02 Z 01 Thus the reflection from the via is minimized. Furthermore, if the system is symmetric, there is no reflection from the via. That is, all the power from the incident wave will be transmitted through the via to the matched load. In this case, the via is called reflectionless. For the equivalent circuit model in Figure 4.13, a derivation similar to that above can be conducted to obtain the same least reflection condition. In this model when

stripline 2 is terminated with a matched load (Y02), the reflection coefficient at T-plane looking into the via from stripline 1 is

 ω2 ω4   ω2 ω4   ω2   ω2 ω4  Y 1− L()C+C + L2CC −Y 1− L()C+C + LC2C +YY jωL1− CC−jωC+C − LC()C+2C + L2C2C 01 g g 02 g g 01 02  g  g g g Eq. Γ=  2 8   2 8   4   4 16   ω2 ω4   ω2 ω4   ω2   ω2 ω4  − ()+ + 2 + − ()+ + 2 + ω  − + ω + − ()+ + 2 2 4.21 Y011 LC Cg LCCg Y021 LC Cg LCCg Y01Y02j L1 CCg j C Cg LCC 2Cg LCCg  2 8   2 8   4   4 16  Under similar conditions, a simplification gives that − + ω − ω( + ) Y01 Y02 Y01Y02 j L j C Cg Γ = + + ω + ω()+ Eq. 4.22 Y01 Y02 Y01Y02 j L j C Cg If the characteristic admittance of the via is defined as

C + C Y = g Eq. 4.23 e L The least reflection condition will occur when = Eq. 4.24 Ye Y01Y02 And the minimal reflection is Y − Y Γ ≈ 01 02 Eq. 4.25 + Y01 Y02 Similarly, if the transmission lines are symmetrical, a reflectionless via transition can be achieved by satisfying the condition of Eq. 4.24. In order to design a reflectionless via, the equivalent components of the via (inductance and capacitance) have to be known and should satisfy the least reflection

89 condition (equations Eq. 4.19 and Eq. 4.24). However, the equivalent inductance and capacitance are related to the physical structure of viahole module. That means the design is really the architecture of viahole itself. In reality, the ground plane where a via passes though has a finite thickness and an equivalent circuit model concerning the effect from this situation can be developed as shown in Figure 4.13. If in this finite thickness model, the Cg is considered to take into account the effect of the finite ground plane thickness [81, 82], the inductance L/2 and capacitance C/2 can be designed by adding different connecting pads (r3) and varying thruhole size (r2) and via size (r1). And the coaxial-cylinder’s capacitance is [88] 2πε ε t C = r 0 g g Eq. 4.26  r2  ln   r1  where r1 is the via radius, and r2 the thruhole radius which is the opening in the center

ground plane with thickness of tg. The viahole is embedded in the material with a

dielectric constant εr. In the next chapter, details of fabricating a novel vertically interconnected 3D- MMIC module using MEMS and microelectronic process technologies are presented.

90 Chapter 5 Fabrication and Characterization of Interconnected 3-D MMIC Sample Circuits

Micro-electro-mechanical systems (MEMS) technology has been developed from traditional electrical engineering fabrication and processing techniques. It is the key technology behind the development of the miniaturized devices and sensors in a broad range of applications. The use of MEMS technology for microwave applications provides a unique, comprehensive technique to integrate a very large degree of functionality on a single substrate with extremely high density and a relatively low cost. In addition, RF MEMS technology has widespread applications in phased arrays and reconfigurable apertures for defense and telecommunication systems, switching networks for satellite communications, and single-pole-N-throw switches for wireless applications (portable units and base stations) [16,17]. It promises to solve some of the most vexing problems still confronting the field of high-frequency technology for today’s wireless and mobile communications systems. Multilevel integration in 3D-MMICs is achieved by using multiple power and ground planes and with planar transmission line transitions between different layers using plated-through vertical interconnects. The nature of MEMS integration technology fits well into the development of novel fabrication techniques to build and achieve three-dimensional microwave and millimeter-wave circuits with various components connected by multilayer monolithic vertical interconnects. Among all fabrication processes, the electroplating of metal posts to form vertical interconnects between different physical levels in 3D circuit packaging is very critical in providing high quality interconnects. For this purpose, the first section discusses some issues in metal electrodeposition or electroplating.

5.1. Metal Electrodeposition Electrodeposition, or plating, is any process which deposits metal onto a substrate which provides a circuit connection function, enhances the performance and/or

91 decorative appeal of the substrate [89]. For electronic applications, metals commonly plated are gold, copper, nickel, silver and tin. Some of these metals can be deposited autocatalytically without external electrical current, which is called electroless plating. In the manufacturing process of electronic devices, plating is used to improve conductivity; to make a surface solderable, weldable, die bondable, or brazeable; to improve corrosion resistance or wear characteristics; to provide low contact resistance; to make electrical connections as in through-hole plating of printed wiring boards (PWB) and via hole connections; and to provide conductive paths, etch resist, diffusion barriers, and so on. In general, the deposition of a metal from a solution of cations, Mz+, superficially appears to take place by a simple discharge reaction of the following type of electrode reaction (cathodic reaction): Mz+ + z e- → M0 In actual fact, electrolytic deposition of metals is a highly complex process. Metal ions exist in solution not only as cations, but also as complex anions. The current density plays a key role in electroplating. Deposition thickness and structures are determined by local conditions of current density and mass transport. A schematic representation of current density versus cathode potential is shown in Figure 5.1.

I / Ilim

1.0 Powders (poorly adherent to surface)

Nodules, dendrites and whiskers

Polycrystalline

Bunched layers, ridges Spirals, layers, blocks (well formed) -E

Figure 5.1 Generalized plot of normalized current display (I/Ilim) as a function of current density. Also

shown are electrodeposit characteristics that may be encountered at different current densities. Ilim is the diffusion limiting current.

When current density varies across a substrate it may cause thickness non- uniformities on the scales of (1) the substrate, (2) the pattern, or (3) the individual feature. As shown in Figure 5.1, it is important to use a current density within a certain range for best deposit properties. Actually the critical parameter is the local current density which determines local deposit thickness. The current density distribution abides by the potential field theory. As indicated in the plot, at low current densities the surface diffusion (mass transport) is fast compared with the electron transfer (electrode reaction), and the crystal structure and defects, e.g., screw dislocations, are well formed. As current density is increased, with an accompanying increase in overpotential, the formation of additional nuclei occurs at a faster rate. Consequently, the electrodeposit structure will be less ordered, and various large-sized features become more likely. With further increases in current density, mass transport becomes a predominant factor in the deposition process.

Ultimately, when the limiting current Ilim is reached, the deposit forms as powders. This is not a desirable situation in electrodeposition, since it leads to “burnt” (gray or dark), or powdery deposits. In order to obtain plated metal of high quality, pulsed plating technology is used in this research. Pulse plating is essentially an interrupted DC plating technique. Its effect is to minimize the nonuniform depletion and replenishment of depositable metal ions at different sites on the surface. This is a large factor in the thickness nonuniformity of uninterrupted DC plating. The pulse occurs after metal replenishment in the boundary layer. This results in more uniform plating thickness with properly scheduled pulse plating. In an electroplating bath, when an electric potential (i.e., voltage) is applied between two electrodes, each point in the electrolyte assumes some potential intermediate between that of the two electrodes. The two parallel plates of anode-cathode configuration possess a potential field distribution between and around them. To maintain an acceptable uniform field distribution between the two electrodes when the cathode plate (the substrate) size is fixed, the anodic plate area is chosen several times larger than the cathode area. A ratio of about 3:1 is commonly recommended.

93 Since copper is much cheaper and possesses higher conductivity than gold, it is chosen as the major conductor in the circuit structures. But high chemical reaction activity of copper, such as easy to form oxide and lower resistance to common acids, has posed some fabrication and processing limitations. As it will be seen in the next section, metal electrodeposition through insulating materials is a key fabrication technique in the 3D vertical interconnect fabrication procedure. Copper electroplating solutions including oxalate, nitrate, cyanide, chloride, acetate, and fluosilicate salts were used in the past, but the only solutions widely used today are alkaline copper pyrophosphate and acidic copper sulfate/sulfuric acid or copper fluoborate/fluoborate acid [90]. Each bath type may be used for electrodeposition over a wide range of current densities, and deposit metallurgy may vary. The copper sulfate/sulfuric acid (acid copper) bath is perhaps the most commonly used bath. To achieve optimal current density and mass transportation for copper plating at room temperature, Cu electroplating bath has the composition of 10ml

H2O: 1 ml H2SO4: 1 g CuSO4:5H2O crystal. Pulsed constant direct current with 50% duty cycle (5 ms “ON”, 5 ms “OFF”) and peak current density lower than 5mA/cm2 were selected from a wide range of experimental trials to produce the vias having high quality electrical and mechanical properties.

5.2. Fabrication of Vertical Interconnects It is a big challenge as to how to fabricate vertical interconnects in 3D MMIC systems since normally the aspect ratio of these via connections is large when optimal size of the device is concerned. Ordinary fabrication technology is not feasible to build these interconnects and still maintain improved performance. One problem is the filling of interconnect viahole at a high yield rate by electrical plating where a conducting path is not always available. Through plating, and making of thin film transmission lines and other circuit components as planar as possible are also major concerns. When characterizing the vertical interconnects in the 3D fashion, the accessibility of the probe ports is also a major issue. There is a lack of reported research in literature about the vertical interconnect processing [91]. In this study a fabrication technique and its processing procedures are developed to meet these challenges based on the advanced

94 technology in MEMS fabrications and implementations. The principal and major fabrication steps are shown in Figure 5.2, which will be described as follows:

Figure 5.2 Fabrication procedures for 3D vertical interconnects

95 (1) Bottom ground plane metallization and CPW probe pads grounding The fabrication process starts with preparation of a clean silicon substrate and then deposition of a metal ground plane as stated in Section 3.2.2. Metal sputtering can provide the desired thickness of conducting metal plane with high quality. Normally a combination of 300 Å Cr/1~1.5 µm Cu/300 Å Cr was deposited on silicon substrates as the bottom ground plane. Cr was used as adhesion promoter between the major conductor, Cu and silicon substrate and polymeric dielectrics. Desirable thickness of polyimide thin film (fully cured PI2611 film of 22 µm thick) was obtained using the spin coating and subsequent hard curing technique as described in Chapter 2. In this test device, a CPW-to-stripline transition was employed to provide the probing ports. Grounding the CPW probe pads was necessary to optimize the subsequent measurements. This was done first by opening the via in the polyimide all

the way down to the ground plane using CF4/O2/Ar RIE etching. Aluminum was used as the mask in the RIE process, followed by metal plating through the polyimide thin film. When finishing up the RIE removal of the polyimide materials for through holes, slight overetching of the bottom ground plane metal (Cr removal) was required to expose the copper layer for later metal plating. Metal plating was done by copper electroplating to fill the through holes. This plating process was discussed in more details in the previous section section. Special cares must be taken to monitor the growth and quality of plated copper. (2) Defining first circuit plane Following the last step, the surface of the wafer had to be thoroughly cleaned and dehydrated in 120oC oven. The cleanness of the polymeric surface affected the metal deposition quality afterwards. The vacuum level and oxygen concentration in the sputtering chamber determined the final quality of metal layer sputtered since copper was easily oxidized in RF plasma if oxygen was present. In order to obtain good copper metal layer, a vacuum level of 5 x 10-6 Torr or better was preferred to lower the oxygen content in the chamber. The first circuit plane was defined on the sputtering metal plane of 300 Å Cr/1~1.5 µm Cu/300 Å Cr using photolithography.

Circuit was patterned by using an etchant of H2SO4:HNO3:H2O in 1:1:10 volumetric ratio. After the metal patterning process, the wafer was carefully cleaned and

96 dehydrated. Then a thin layer of copper, about 500 Å thick, is sputtered to cover the entire wafer and provide conducting path for plating. (3) Growing 3D via of first half height The vias were formed by plating metal through a thick insulating material. For this purpose, first a thin conducting metal layer was deposited all over the surface, followed by spin-coat deposition of a thick layer of photoresist (AZ4620) with thickness slightly greater than 22 µm (about 25 µm). To prepare the thick AZ4620 photoresist layer, photoresist was first spread at 500 rpm for 10 sec then spun at 1000 rpm for 20 sec to evenly distribute the resist across the wafer. The wafer was kept at room temperature for 4 min, then in 60oC oven for 4 min, and 100oC hotplate at 4 min, then back to 60oC oven for 4 min and finally kept at room temperature at least 4 min before UV exposure. This soft baking process is illustrated in Figure 5.3.

Figure 5.3 AZ4620 soft baking procedure

In order to obtain a good quality photoresist layer for the successful photolithography, a relative humidity greater than 50% was recommended. At this humidity level, the UV exposure of 25 µm of AZ4620 photoresist was conducted in two steps with a total exposure time of 3 minutes with 30 sec interval of idle period in between. The exposed photoresist was developed in a solution with AZ400K to DI water ratio of 1:4 (v/v) for 3 minutes. The wafer was rinsed thoroughly with plenty of DI water after development. Normally a high aspect ratio of the apertures and openings were obtained if all above processing parameters were met. The 30 sec of break time between a long time of UV exposure assured that no burnt-out of photoresist occurs. In this process, the relative humidity played an important role in

97 determining the subsequent processing parameters and finally the quality. If lower relative humidity was inevitable, corresponding total UV exposure time, development solution concentration and time were increased, For example, if relative humidity was about 35~40%, UV exposure time was increased to 4.5 minutes and development solution ratio was changed to 1:3.5 (v/v). Development time was maintained the same or in certain cases extended 1 more minutes. But, the recommendation is always to maintain a favorable relative humidity level. Following the special photolithography, the via holes with high aspect ratio were successfully obtained and were ready to be filled with metal plating to form the vertical interconnects. Since the defined via through holes had a very high aspect ratio, there was the possible problem of accessibility of plating solution to the metal surface of the small hole bottom. Therefore, before the via growth in metal plating, the wafer was immersed into a dilute water solution of a conducting surfactant agent and vacuumed to substitute the air from the holes with the conducting solution. This made almost the growth in each hole to have a similar growth rates and better quality. Figure 5.4 shows the plated via post with its first half height sitting on the metal strip. In this figure insulating photoresist AZ4620 was removed after the post plating. Obviously the “mushroom” head of post shape results from a longer plating time and this makes the growth in post height sufficient.

Figure 5.4 SEM picture of a plated copper post on strip after insulating AZ4620 is removed

(4) Coating polyimide film and chemical-mechanical polishing After growing the posts of first half height, the thick layer of photoresist was removed and the thin conducting layer was etched away, leaving the posts unattacked. Special care and cautions had to be taken to preserve the integrity of the posts and their adhesion to the strip. Then, the wafer was covered with polyimide of desired thickness following the same procedure as discussed before. However, in order to enhance the adhesion between fully cured polyimide and fresh coating of polyimide, a short time of ashing in oxygen plasma was normally adopted to roughen the wafer surface right after removing AZ4620 layer. This ashing step removed any possible photoresist residue. As usual VM-651 promoter was also used before the polyimide coating. An SEM picture indicating the posts covered by the fully cured polyimide layer is shown in Figure 5.5. Clearly shown are the bumped areas around the post “mushrooms” and post heads fully covered by polyimide.

Figure 5.5 SEM picture of plated posts covered by polyimide

Now the chemical-mechanical polishing is the required next step to planarize the wafer surface and expose the posts. This chemical-mechanical polishing was done by a LAPMASTERTM lapping machine. Before polishing, the wafer was first waxed

99 with its back to a metal chunk. The flatness of this waxing step is very critical to determine the final skew ratio and surface finishing. Then the wafer was placed with the surface to be polished against the polishing pad. A RODELTM C-1000 polishing pad was used in this process. A pad of this hardness level worked well to polish the metals such as copper and gold. Adding certain weights onto the metal chunk determined the necessary pressure between the wafer surface and the polishing pad. To assist in the polishing of polyimide and metal, a slurry solution with fine alumina particle (particle size less than 0.35µm) and silica gel was pumped to wet the pad and increase the surface tension between the polishing surfaces, thus facilitating the polishing. The slurry solution was made by adding 10g of BaikaloxTM alumina polish powder (Type CR15) to 420ml solution of 20:1 water vs. Nyacol OneTM (colloidal silica) mixture. In this process, the weight added to the chunk, the flow rate of slurry solution to the pad and the RPM of lap rotor determined the time for a desired polish depth and its surface finish. Generally speaking larger the weight on the chunk, higher the flow rate of polish assistant and higher RPM finished a certain polishing job in a shorter time. Figure 5.6 shows the top of a post after polishing away the covered polyimide and “mushroom” head.

Figure 5.6 SEM picture of an exposed post top right after polishing

100 In order to explore the parameters to assure the quality of chemical- mechanical polishing process, a deconstructive RIE process was used to expose the posts by removing the polyimide around them. Figure 5.7 shows the posts after polishing and with the polyimide removed. Shown in Figure 5.8 is the enlarged SEM picture of the polished post with “cloudy” polyimide residue. It clearly shows that the polishing process produced fairly good quality of exposed posts after excess metal and polyimide were removed.

Figure 5.7 SEM picture of polished posts after deconstructive removing of polyimide

Figure 5.8 Enlarged SEM picture of an polished post

101 (5) Defining thruholes in central ground plane This step was similar to Step 2, but defining the thruholes in the sputtered central ground plane used a different mask in the process of photolithography. Alignment of the opening in the mask to the metal pattern made sure that the top of the posts were opened for the plating of posts of second half portion. Based on the results of comparison experiments for this step, it was found out that in addition to the

cleaning of wafer surface after polishing by rinsing, a brief CF4/O2/Ar RIE etching of the polished wafer surface in 15 or 30 sec helped in defining the thruhole process and resulted in less metal residue. Like in Step 2, a thin layer of copper, about 500 Å thick, was then sputtered to cover the whole wafer and provided again a conducting path for plating the posts that formed second half portion of the vias. Figure 5.9 shows the wafer surface where a central ground plane thruhole has been defined and covered with a thin copper layer. Also shown in this plot is the relatively good alignment that has been achieved to co-centralize the features.

Figure 5.9 A photograph of the thruhole opened around the lower half of the via post

(6) Growing posts of second half height This step is similar to Step 3. After deposition of thin conducting layer a thick layer of photoresist AZ4620 was again coated following the procedure outlined in Step 3. The special photolithography was again used to define the openings with high

102 aspect ratio for growing the posts. The posts grew through the photoresist to required height by metal plating. Figure 5.10 and Figure 5.11 show the plated posts with mushroom-shaped heads sitting on their first half portion to form vias of full-size height.

Figure 5.10 A SEM picture of plated post sitting on its first half portion with square thruhole

Figure 5.11 A SEM picture of plated post sitting on its first half portion with circular thruhole

(7) Polyimide film coating and polishing

103 This step was similar to Step 4. The same wafer surface cleaning process and polyimide coating procedures were strictly followed to ensure the quality of dielectric layer. Meanwhile, the chemical-mechanical polishing process was conducted in the same manner to have the upper and lower dielectric layers almost the same thickness. Figure 5.12 and Figure 5.13 show the polished posts with “cloudy” polyimide residues after polyimide was removed during RIE process.

Figure 5.12 SEM picture of a polished post of full height with circular thruhole after deconstructive removing of polyimide

Figure 5.13 SEM picture of a polished post of full height with square thruhole after deconstructive removing of polyimide

104

(8) Second circuit plane definition and CPW probe pad grounding Using the RIE etching and metal plating processes outlined in Step 1 and the similar metal deposition and photolithographic patterning in Step 2, grounding of the CPW probe pads and the upper level circuit plane were accomplished successfully. However, as discussed in Step 5, in order to clean the wafer surface and remove possible AZ4620 residues, a short RIE process in CF4/O2/Ar plasma was performed prior to the metal deposition. This RIE process also increased the adhesion of the circuit metal to the polished polyimide surface. Meanwhile, a brief ashing in oxygen plasma after metal patterning was required before the deposition of the final layer of polyimide coating. (9) Polyimide coating and top ground plane covering, and opening probe accesses Coating the final layer of polyimide and covering it with the top ground plane accomplished the stripline-type circuit to be interconnected by the vertical via. Since up to this stage the wafer had gone through several tough processing steps and also its surface became very irregular, this last step of polyimide deposition was done with special care. It was normally done by using a vacuum chamber at an escalated temperature to eliminate possible air bubbles trapped in the polyimide precursor spin coating. The wafer was vacuumed after each layer of the precursor spinning before soft baking and final hard curing. This vacuum evacuation of trapped air on the wafer surface between coated polyimide precursors was also used in previous Step 4 and Step 7 based on the judgments of surface topography. Making openings in the top ground plane enabled RIE etching of polyimide to reach the probe ports at different thickness levels. In order to achieve the RIE masking, a layer of 1200~1500 Å aluminum was sputtered onto the top Cr/Cu/Cr metal ground plane. Then the special RIE process was done in two steps. This processing also required two steps of Al mask patterning. First, the mask openings for deep port access side were defined and polyimide was etched to the desired depth by removing required thickness of polyimide. Then the shallow side was opened again. Now both sides of the port access areas were opened to the RIE plasma. By controlling the processing parameters and taking precautions and special care, the

105 measurement ports at different polyimide thickness levels were exposed and became accessible. In Figure 5.14, the measurement port at the shallow polyimide side is shown with the CPW pads and top ground plane. Figure 5.15 shows the measurement port at the deep side. In this figure, other than the CPW pads, stripline and top ground plane, the center ground plane are clearly shown. Now the wafers are ready for making measurements to characterize the effects of vertical interconnects in 3D MMIC systems.

Figure 5.14 SEM picture of the measurement port at the shallow side

Figure 5.15 SEM picture of the measurement port at the deep side

106 The fabrication steps described above did not include the isolation sidewalls or posts connecting the ground planes. Actually they can be easily incorporated into the test device by using the polyimide RIE etching and metal plating.

5.3. Characterization of Vertical Interconnects There are fewer characterization results concerning the vertical interconnects reported in literature [18, 92, 93], especially for MMIC systems. As has been mentioned above, there is inherent difficulty in fabricating the interconnect test devices which connect stripline transmission lines and/or shielded coplanar waveguide with ground plane (SCPWG) transmission lines. There is a testing probe accessibility issue which adds complexity to the fabrication processes. Based on the novel fabrication procedure described in Section 5.2 utilizing MEMS technology, test device can be made for the on- wafer interconnect performance characterization. In 3D multilayer integration of RF and microwave components, stripline and shielded coplanar waveguide find many applications because of the nature of their structure favoring multilayer interconnection. High speed and high density integration in modern integrated circuits, especially in monolithic microwave integrated circuits, demand very thin metallization lines in the processing due to cost and other manufacturing considerations. From the fabrication process, we also know that the metallization layer for the test devices is relatively thin, and in the frequency range of interest it is on the order of the skin depth. In such thin metal lines, the accurate evaluation of conductor loss is very important to extract the properties of vertical interconnects from the experimental results. For this purpose, the modification method discussed in Section 3.3.1 is applied to derive the conductor loss models for thin stripline and SCPWG transmission lines. 5.3.1. Conductor Loss in Thin Stripline and SCPWG

• Stripline Case

Figure 5.16 shows the field penetration in the cross-section of stripline transmission line. To evaluate the conductor loss for a stripline with its metal thickness greater than several times of the skin depth, Cohn [94] has derived a set of basic formulas

107 widely used to calculate the attenuations based on the Wheeler’s incremental inductance rule. In this study, the wide strip case where W/b > 0.35 is required in the characterization. Therefore, the conductor loss of thin metal strip for this case is discussed here.

Figure 5.16 Field penetration in stripline

For the stripline with a wide strip, characteristic impedance with or without strip thickness effect can be expressed as [94, 95] 30π ()1− t b Eq. 5.1 Z = 0 ε ()+ r W b C f where

 1  tπ  1  C = 2π ln +1 − ln −1 f  −   2  1 t b  b ()1− t b  Based on Wheeler’s rule, the conductor loss can be written as follows

R ε  ∂Z  R ε  ∂Z ∂Z ∂Z  Eq. 5.2 α = s r  0  = s r  0 − 0 − 0  c η ∂ η ∂ ∂ ∂ 2 Z 0  n  Z 0  b W t  δ As shown in Figure 5.16, the change n must be considered on the inner surfaces of the two ground planes and on the four surfaces of the strip. These effects are incorporated into Eq. 5.2 to calculate the incremental inductance and translated to the change in characteristic impedance. For the strip thickness of several times of the skin depth, the α conductor loss c becomes

108 4R ε Z Eq. 5.3 α = s r 0 A Np/m, c η 2 (b − t) where 2W 1 b + t  2b − t  A = 1+ + ln  b − t π b − t  t  When the conductor becomes thin and on the order of the skin depth at the frequency considered, the correction relationships as developed in Eq. 3.39 can be applied to account for the skin effects on the metal impedance. Due to the symmetrical nature of the stripline structure compared with the microstrip structure, the correction coefficients are greatly simplified. The term which accounts for the nonsymmetrical distribution of the fields and currents around the strip becomes unity, i.e. m2=1. And the following correction coefficients corresponding to the terms in Eq. 3.39 can be used for the strip transmission lines.

= γ t  Cw coth c   2 

= γ w  Ct coth c   2  = (γ ) C g coth ct g For the wide strip case, i.e. W/b > 0.35, a closed formula to evaluate the conductor loss by accounting for the skin effect can be expressed in the following way. (The derivation process is given in Appendix F Calculating conductor loss in thin stripline using MathematicaTM).

    t   tg   t   t   W Coth  + Coth  bCoth  + tCoth g   ε    2δ   δ   δ   δ  −  4Rs r Z0  W    s   s   2 s   s   2b t  α = Coth  + + ln  c η 2 ()−  δ  ()− π ()− Eq. 5.4 b t   2 s  b t b t  t     

Since the strip width in this case is significantly greater than the skin depth at the

 W  frequency of interest, Coth  = 1 will be generally met. And the above equation can  δ   2 s  be simplified and gives

109     t   t g    t   t   W  Coth   + Coth    bCoth   + tCoth  g     δ   δ    δ   δ  4 R ε Z  2 s s 2 2b − t  α = s r 0 +       +  s   s    Eq. 5.5 c 2 1 ln    η ()b − t  ()b − t π ()b − t  t       Obviously when the metallization layer for the striplines increases and becomes

 t   t  equal to or greater than four or six times of the skin depth, Coth  and Coth g  will  δ   δ   2 s   s  also approach unity. Eq. 5.5 eventually becomes Eq. 5.3 and both methods give the same conductor loss estimates. The conductor losses of a specific stripline varying with conductor thickness and frequency range of interest are plotted in Figure 5.17 and Figure 5.18 for the conventional Wheeler’s rule and its modified method, respectively (see also Appendix F Calculating conductor loss in thin stripline using MathematicaTM). A comparison between these two figures shows that for a specific stripline structure when the conductor thickness is thin and on the order of skin depth, the conductor losses evaluated from these two methods can be significantly different. At a certain frequency, the Wheeler’s rule and its modified formula will give similar results when the thickness of conductor becomes at least four or six times the skin depth. As it has been already demonstrated in the microstrip structures in Section 3.3.1, in order to lower the conductor loss, a thick metallization layer in the transmission lines is preferred for strip transmission lines as well. And for both cases, the conductor loss increases as the frequency increases. That is why at higher frequency applications, conductor loss can become severe. The validation of the application of modified Wheeler’s rule to evaluate the conductor loss in the thin stripline structure is illustrated in Figure 5.19. In this figure stripline attenuation is interpreted as insertion loss in the S-parameter (S21) term and also includes the dielectric loss (loss tangent). It is clearly shown that the insertion loss varying with frequency along the stripline has a good agreement between the theoretical evaluation and the measured result when the conductor loss was calculated from the modified method. That is only when the skin effect of the thin metallization on the conductor loss is correctly estimated. A correct characterization of thin stripline structures used in this research is critical in characterizing vertical interconnects since the thin stripline properties have to be differentiated from that of the vias in the test structure.

110

Figure 5.17 Stripline conductor loss in dB/cm versus frequency and t (metal thickness) from Wheeler’s rule for W=24 µm, b=44 µm, εr=3.3 and σ=3x107 S/m (deposited metal)

Figure 5.18 Stripline conductor loss in dB/cm versus frequency and t (metal thickness) from modified method for W=24 µm, b=44 µm, εr=3.3 and σ=3x107 S/m (deposited metal)

111 0 -0.5 -1 -1.5

B -2 d

-2.5 in 1

2 -3 S -3.5 Stripline (measured) Stripline (modified model) -4 Stripline (Wheeler's rule) -4.5 -5 8 8.5 9 9.5 10 10.5 11 11.5 12 freq. (GHz)

Figure 5.19 Stripline attenuation expressed as S21 in dB versus frequency with conductor loss incorporated for W=22 µm, b=44 µm, εr=3.3, t=0.85 µm and σ=3x107 S/m (deposited metal)

• SCPWG Case

S W

h εr

Figure 5.20 Conventional coplanar waveguide (CPW)

Conventional coplanar transmission lines, such as conventional CPW (as shown in Figure 5.20) are shielded or stacked between extra ground planes when they are used in the 3D multilayer structures. SCPWG designates the conductor-backed coplanar waveguide transmission line with upper shielding, or simply, Shielded Co-Planar Waveguide with Ground planes. The structure of such a coplanar waveguide is shown in Figure 5.21.

112

Figure 5.21 Shielded coplanar waveguide with ground planes [96]

In this configuration, both conductor backing and upper shielding exist with the CPW structure sandwiched in the middle, as shown in Figure 5.21. The upper half-plane

is filled by dielectric material of relative permittivity εr0, and the lower half is filled by dielectric material of relative permittivity εr. Although the side lateral ground planes are always finite in practice, assumptions of infinite ground planes can still be made when they are wide enough [97].

The upper half line capacitance per unit length C1 can be found by conformal mapping outlined in Figure 5.22. The first quadrant of the Z-plane is transformed to upper half of the T-plane by means of the mapping function [53, 96]  π  = 2 z t cosh   Eq. 5.6  2h1 

Figure 5.22 Conformal transformation of the first quadrant of CPW conductor backing and upper shielding into parallel plate geometry: (a) Z-plane, (b) T-plane, and (c) W-plane [96]

113 then into the parallel plate capacitor in the W-plane through the conformal transformation

t dt w = ∫t0 ()− (− )(− ) Eq. 5.7 t 1 t t1 t t2

The capacitance is then given by K()k C = 2ε ε 4 1 0 r0 () Eq. 5.8 K' k4 where tanh()πa 2h k = 1 4 ()π Eq. 5.9 tanh b 2h1 K, and K’ are the complete elliptic integrals of the first kind and its complement, respectively. They are simply related to each other through the following equations K ' ()k = K()k ' Eq. 5.10 with

k ' = 1− k 2 Eq. 5.11

Similarly, the lower half capacitance per unit length C2 of this coplanar line can be inferred by substituting a different dielectric constant and thickness. The resulting capacitance is K()k C = 2ε ε 5 2 0 r () Eq. 5.12 K' k5 with tanh()πa 2h k = 2 5 ()π Eq. 5.13 tanh b 2h2 where h1 and h2 are the distance from coplanar line to upper shielding and conductor backing, respectively. Thus, one can obtain the effective permittivity and characteristic impedance + ε = C1 C2 = ()− ε + ε re 1 q r0 q r Eq. 5.14 C ε = + C ε = 1, r 0 1 2, r 1 with filling factor

114 K()k K'(k ) q = 5 5 () ()+ () () Eq. 5.15 K k4 K' k4 K k5 K' k5 and 60π 1 Z = 0 ε () ()+ () () Eq. 5.16 re K k4 K' k4 K k5 K' k5 = = If h1 =h2, conformal mapping yields the exact results with k4 k5 , filling factor q 1 2 , ε = ()ε + ε and effective permittivity re r r0 2 . The effect of metallized conductor thickness on the characteristic impedance of coplanar waveguides can be taken into account empirically by defining the effective

center strip width We, and the effective slot width Se. For a coplanar waveguide structure shown in Figure 5.20, we can write = + ∆ We W Eq. 5.17 and therefore, = + ∆ Se S Eq. 5.18 where ∆ = ()1.25t π []1+ ln()4πW t is obtained empirically by curve-fitting of experiment and numerically evaluated values. Accordingly, we obtain the effective values for a and b 1 1 1 1 a = W = W + ∆ = a + ∆ Eq. 5.19 e 2 e 2 2 2 1 1 1 1 b = W + S = W + ∆ + S − ∆ = b − ∆ Eq. 5.20 e 2 e e 2 2 2 When the quasi-static approximation is valid and conductor is thick enough, one can use Wheeler’s incremental inductance formula to evaluate conductor loss as discussed before. Various recessions are considered in coplanar waveguide configuration as follows: 1) δW=-2δn (due to recession of edges of center strip) 2) δS=2δn (due to recession of edges of center strip and side ground planes) 3) δt=-2δn (due to recession of top and bottom of conductors)

115 After taking into account recessions in all the conductor walls, the expression for the attenuation constant due to conductor loss for a symmetric SCPWG transmission line may be written as [53] R ∂Z a ∂Z a ∂Z a  α = 0.023 s 0 − 0 − 0 dB / m c  ∂ ∂ ∂  Eq. 5.21 Z 0  S W t 

a where Z 0 is the characteristic impedance of a coplanar line with air as dielectric. This case is similar to the modification of conductor loss evaluation in stripline and microstrip transmission lines and the same correction coefficients apply to the thin conductor situation in SCPWG lines. However, since the strip width (W) and gap size (S) are normally much greater than the skin depth of interest, this simplifies the corresponding terms in the conductor wall recessions. The correction coefficients accounting for the strip width and gap size are virtually equal to unity. The only term

 t  Coth  accounts for the skin effect from thin conductor. A closed-form to evaluate  δ   2 s  conductor loss due to this thin conductor situation can be expressed as

R ∂Z a ∂Z a  t  ∂Z a  α = 0.023 s 0 − 0 − Coth  0 dB/m c  ∂ ∂  δ  ∂  Eq. 5.22 Z 0  S W  2 s  t  Obviously, when the metallization layer of the SCPWG line increases and

 t  becomes equal to or greater than four or six times that of the skin depth, Coth   δ   2 s  becomes unity. Eq. 5.22 and Eq. 5.21 are actually the same and give the same conductor loss estimation. The conductor losses of a specific SCPWG line varying with conductor thickness and frequency range of interest are plotted in Figure 5.23 and Figure 5.24 for the conventional Wheeler’s rule and its modified method, respectively (see also Appendix G Calculating conductor loss in thin SCPWG line using MathematicaTM). Similar to the stripline case discussed above, a comparison between these two figures shows that for a specific SCPWG structure when the conductor thickness is thin and on the order of skin depth, the conductor losses evaluated from these two methods are significantly different. The Wheeler’s rule and its modified methods give similar results when the thickness of

116 conductor becomes at least four or six times the skin depth. Similarly, a thicker metallization layer in the transmission lines produces less metal loss and lower loss at lower frequencies. The validation of the application of modified Wheeler’s rule to evaluate the conductor loss in the thin SCPWG structure is illustrated in Figure 5.25. In this figure

transmission line attenuation is expressed as insertion loss in S21 term and also includes the dielectric loss (loss tangent). It is clearly shown that in order to achieve the correct evaluation of conductor loss in thin transmission lines, the skin effect modification to the conventional Wheeler’s rule is very important. Only by accurately evaluating this loss, the insertion loss varying with frequency calculated from analytical model will agree with the measured results. The correct characterization of thin SCPWG structures will play an important and integral role in characterizing the vertical interconnects when the thin SCPWG properties have to be differentiated from the vias in the test structure. This is discussed in the following sections.

Figure 5.23 SCPWG line conductor loss in dB/cm versus frequency and t (metal thickness) from 7 Wheeler’s rule for h1=h2=22 µm, εr=3.3 and σ=3x10 S/m (deposited metal)

117

Figure 5.24 SCPWG line conductor loss in dB/cm versus frequency and t (metal thickness) from modified 7 method for h1=h2=22 µm, εr=3.3 and σ=3x10 S/m (deposited metal)

0 -0.5 -1 -1.5

B -2 d

n -2.5

21 i -3 S -3.5 SCPW (measured) SCPW (modified model) -4 SCPW (Wheeler's rule) -4.5 -5 8 8.5 9 9.5 10 10.5 11 11.5 12 freq.(GHz)

Figure 5.25 SCPWG line attenuation expressed as S21 in dB versus frequency with conductor loss 7 incorporated for h1=h2=22 µm, εr=3.3, t=0.85 µm and σ=3x10 S/m (deposited metal)

118 5.3.2. Interconnect Characterization Results

• Probe Pads Grounding Effect

As it has been pointed out early in the previous chapters that the probe pads are recommended to be grounded to minimize the CPW probe pad effects on the S-parameter measurements in thin film dielectrics and interconnect characterizations. Figure 5.26 shows the CPW ports used for interconnect characterization and the probe pads in detail. Experiments results to reveal the effect of the probe pads grounding in the stripline measurements of the insertion loss in terms of S21 are shown in Figure 5.27. In this figure, the insertion loss was measured on the striplines with the same stripline structures but with and without probe grounding. Since the probe pad sizes used for grounding purpose were limited, and if they were not directly grounded by the vias to a common ground, their equivalent capacitances at low RF frequencies were not able to provide sufficient grounding. Two of the measured insertion loss curves in Figure 5.27 clearly show that at low frequencies, there are large discrepancies between the two test structure measurements with or without fully grounded probes pads. With increasing signal frequency, the grounding provided by the capacitive pads may become sufficient to provide an RF ground and the effect will be small. At RF test signal at 5 GHz or higher the grounding effect from the size of probe pads will not be important.

Figure 5.26 CPW ports for interconnect characterization and the probe pads [91]

119

-1

-2

-3 B d , 1

S2 -4

-5 Stripline & pads (measured) Stripline & gnd pads (measured) -6 Stripline & pads (simulated) Stripline & gnd pads (simulated) -7 123456789101112 Freq. (GHz)

Figure 5.27 The CPW probe pads grounding effect on thin stripline insertion loss measurements

This effect of the grounding probe pads with limited size can be modeled when the thin stripline skin effect is being properly incorporated. Figure 5.28 shows the LIBRA model for simulating CPW probe pad grounding effect in thin stripline measurements. The stripline is represented by a physical transmission line model derived from the measured characteristics and the attenuation factor including the strip skin effect. The capacitors connected between the transmission line ground wire and the real ground represents the probe pads. Their capacitance values of about 2 pF were estimated from the parallel plate model with the fringing fields neglected to a first order approximation. If the pads were directly grounded by the vias, a real ground or a capacitor with infinite value would ground the physical transmission line. The results plotted in Figure 5.27 shows that the LIBRA model simulations agree well with the measurements within the reasonable error range. Therefore, to minimize the grounding effect of the measurement probe pads especially for lower frequency measurements, the direct grounding of the pads by the vias are important to provide a real common ground for the test structure to obtain the accurate characterization of the device under test.

120

Figure 5.28 LIBRA model for simulating CPW probe pads grounding effect

• Interconnection with Single Via

Having investigated skin-depth effect on the conductor loss in thin transmission lines and the grounding effect of probe pads, characterization results of vertical interconnects will now be discussed. For simplicity, the test structures chosen were the stacked SCPWGs and striplines, which were interconnected by the vertical vias. Since the dielectric material, polyimide, and finite conductivity metal introduced losses into the test structures, they could not be modeled by the combination of lossless transmission lines and pure reactive lumped element models for the vias. The lossless model was used to extract the equivalent circuits from FEM simulations in Chapter 4. In general, the lossy test structures can be represented by a lossy model shown in Figure 5.29. In this model, the lossy transmission line networks are the physical SCPWG or stripline transmission lines which were fabricated using the novel MEMS technology described in Section 5.2. The losses consist of the dielectric loss from polyimide and the conductor loss from thin metallization layer. The block diagram in the middle of Figure 5.29 represents the lossy via interconnect. By introducing the resistive parts into the lossless model, such as the one shown in Figure 4.12, the lossy interconnect network can be represented by the lossy lumped-element equivalent circuit model shown in Figure 5.30.

121

Figure 5.29 A schematic model of the test structure for interconnect characterization

Figure 5.30 A lossy lumped-element equivalent circuit for a lossy vertical via

In this research, the test structures were built from planar striplines and SCPWG transmission lines, connected by vertical vias. The stacked transmission lines have nominal characteristic impedance of 50 ohm and their dimensions are summarized in Table 5-1. The design was based on the polyimide dielectric constant of 3.0 and metal thickness of 2 µm. The physical dimensions of a 50 ohm SCPWG line were obtained by solving Eq. 5.16. However, due to the resolution of the metal patterning process, the physical dimensions of the test structures are normally different from the design values. In the subsequent modeling, the real dimensions were obtained in each step of the fabrication process whenever they were necessary.

Table 5-1 Physical dimensions of vertical interconnect test structures TL dimensions Via diameter Thruhole (µm) (µm) diameter (µm) b = 44 Stripline W = 24 24 100 L/2= 4000 (half length) h1 = h2 = 22 S = 35 (gap width) 28 100 SCPWG W = 28 L/2= 4000 (half length) Notes: when stripline connected by two vias, an extra 7000 µm segment was inserted.

122

Figure 5.31 shows the experimental results of the insertion loss, S21, for an SCPWG test structure with vertical via interconnection. For comparison, the measured results for the same length of the SCPWG line without the vertical interconnect is also illustrated. By a simple subtraction of these two curves, the insertion loss associated with the via was found to be about 0.5 dB. The sources of this loss may include three major contributions. First, the vertical interconnect produces the transmission discontinuity in the signal path along the structure and contributes significantly to the insertion loss. Secondly, the via itself produces conductor loss and may be larger than that of pure metal since the plating metal quality is lower than pure metal. Finally, there is a possibility of loss due to the parallel plate mode.

0.0 -0.5 -1.0

-1.5 -2.0 B d , -2.5 1

S2 -3.0 SCPWG+via (measured) -3.5 SCPWG (measured) via (extracted) -4.0 SCPG (simulated) SCPWG+via (simulated) -4.5 via (model) -5.0 8 9 10 11 12 freq.(GHz)

Figure 5.31 Experimental and simulation results for the SCPWG test structure vertically connected by vias

For circuit simulation and design, a lumped-element equivalent circuit model for vertical via may be of great practical importance. In order to obtain the lumped-element equivalent circuit for the via, a lossy LIBRA transmission network model as shown in

123 Figure 5.32 was optimized to match the test structure S-parameter measurement results. In Appendix E Procedure for extracting equivalent circuit using HP LIBRA Unix Version (v6.1) details of this optimization process are given. In this model, the conductor losses for thin strip transmission lines were also incorporated. Figure 5.31 shows a fairly good match of the lossy transmission network model with the measured data. Based on this equivalent circuit extraction model, the lumped-element results agree relatively well with the results for the via through the subtraction process. From this optimization, corresponding component values for the model elements were obtained.

Figure 5.32 LIBRA model of the test structure with lumped-element equivalent circuit for the via

Figure 5.33 shows the experimental results of the insertion loss, S21, for a stripline test structure with vertical via interconnection. For comparison, the measurement result for the stripline of the same length but without the vertical interconnect is also illustrated. From a simple subtraction, the insertion loss associated with the via was found to be about 0.6 dB. The sources which contributed to the insertion loss in this case were almost identical to the SCPWG test structure since these two test structures were similar except that SCPWG line had excess ground planes on the strip level. In the same manner, a lumped-element equivalent circuit model which included the resistive loss parts was also obtained for this test structure. The values of the equivalent circuit model for both of these two test structures are summarized and tabulated in Table 5-2. For the stripline case, these values are obviously different from those obtained in the ideal FEM simulation.

124

0.0

-0.5 -1.0 -1.5

-2.0 B

d -2.5 21,

S -3.0 stripline+via (measured) -3.5 stripline (measured) -4.0 via (extracted) stripline (simulated) -4.5 stripline+via (simulated) via (model) -5.0 8 9 10 11 12 freq.(GHz)

Figure 5.33 Experimental and simulation results for the stripline test structure vertically connected by via

Table 5-2 Via equivalent circuit components for SCPWG and stripline test structures

SCPWG Stripline

L (pH) 64.40 108.2

C1 (fF) 45.53 21.40

C2 (fF) 14.62 10.05

R (ohm) 2.56 4.03

It has been shown that the insertion loss in real stripline test structure is obviously much greater than that in ideal case due to the physical realization and lossy nature of the materials. It is also found that the phase difference between these two cases is of considerable significance in the circuit design. The phases introduced by the two cases may also be important in the design of phase shifters and delay lines. The equivalent circuit model in Figure 5.34 employed to represent the via in stripline test structure is

125 compared with the lossless model in Figure 4.12 for the phase difference. The comparison of the phase difference is shown in Figure 5.35. In the ideal case, the phase change from the via is small and negligible. The phase introduced by the via can be taken care of by adding a segment of transmission line with an equivalent length equal to the via height. However, in the realistic case, the phase can be larger than that from the via length only. Additional contributions may be due to the interconnect discontinuities. Therefore, for the designs with emphasis on phase, extra phase change from discontinuities can not be neglected. Otherwise, they will contribute a fair amount of error to the design.

Figure 5.34 LIBRA model of the via lumped-element equivalent circuit with resistive loss

Figure 5.35 Phase difference for the via in ideal simulation and test structure

126 • Interconnection with Two Vias

In order to validate the equivalent circuit model for the vertical vias in circuit design applications, a stripline test structure connected by multiple vias was investigated. Figure 5.36 shows the cross-sectional view of the stripline test structure which was interconnected by two vias having identical characteristics. In this structure, three segments of striplines were stacked at two different physical levels separated by a center ground plane. These stripline segments were connected by the vias through the center ground plane. The vias were of the same physical dimensions as those in the single via interconnect discussed earlier. The corresponding LIBRA model as shown in Figure 5.37 was used to simulate this structure. In this model, two identical equivalent circuits represented the vias and had the same component values as those tabulated in Table 5-2 for the stripline test structures. Since the probe pads in this test structure were not directly grounded, their corresponding capacitances were approximately evaluated by the parallel plate capacitor model taking into account their respected sizes at each port.

Figure 5.36 A cross-section view of the stripline test structure connected by two vias

Figure 5.37 LIBRA model for the stripline test structure with two vertical vias

127

Figure 5.38 shows the insertion loss measurement results for the stripline test structure connected by two vertical vias. Also shown in this figure are the simulation results from the multiple via interconnect model in which an equivalent circuit model for the via was obtained from a single via interconnect. The fairly good agreement between these results verifies the effectiveness of the lumped-element equivalent circuit model for the vertical interconnects.

-5

-10 B d , -15 1 S2

-20

Stripline+two vias (measured) -25 Stripline+two vias (model)

-30 8 9 10 11 12 Freq. (GHz)

Figure 5.38 Experimental and simulation results for the stripline test structure with two vias

5.4. Summary A unique fabrication technology for the purpose of realizing high aspect ratio via interconnects in a 3D MMIC multilayer integration system was developed using the combination of the traditional electronic and MEMS microfabrication technologies. Based on these techniques, different test structures have been successfully fabricated to facilitate the vertical interconnect characterization. In order to accurately interpret the conductor losses associated with planar transmission lines of thin metallization layers, such as thin stripline and SCPWG lines, modifications on the conventional Wheeler’s rule were developed to account for the skin effects based on the penetration of fields into the conductor. The closed-form formulas or

128 simplified equations have been used to readily evaluate the conductor losses in thin stripline and SCPWG transmission lines with wide strips. Measurement results have confirmed the validation of these models. These results have also been incorporated into via characterization. Experimental results have shown that the size of the probe pads in RF measurement ports has significant influence on the accuracy of the data when their size is finite. At low frequencies, their capacitive effects may not provide sufficient RF signal grounding. Therefore, to minimize the effects of the measurement probe pads especially at lower frequency measurements, the direct grounding of the pads by vias provides a real common ground to the test structure. This is very important to obtain accurate characterization of the devices under test. With the accurate evaluation of the loss characteristics of each part in the test structures, lumped-element equivalent circuit models for the vias were derived from the measurement results. Experimental results revealed that at RF frequencies, the vertical interconnect discontinuities contribute significantly to the insertion loss and the phase change. The equivalent circuit for the stripline interconnects was verified by the measurements from multiple interconnect test structures. These models are of great practical importance in a complex circuit design.

129 Chapter 6 Conclusions and Recommendations

6.1. Conclusions Polyimides, through a two-step process which consists of solution spin-coating of polyimide precursor polyamic acid and subsequent high-temperature curing, can be deposited in thin film form with good film uniformity, topography and electronic properties. Desired film thickness can be precisely controlled by the processing parameters and by the number of layers. Good planarization property of spin-coated polyimide thin films provides the compatibility and possibility for interlayer conductor circuits integration, and hence three dimensional stacking of MMIC components. Fully cured polyimide thin films possess also favorable electric and mechanical properties for the 3D MMIC applications. For the patterning of fully cured polyimide, RIE is a good thin film patterning process. With controlled processing parameters for the RIE process, desired features of specific structures can be obtained. However, in order to obtain the good polyimide properties and desirable features, special cautions and procedures have to be taken. In order to correctly evaluate the conductor loss in thin microstrip lines, a modified conductor loss model was derived from original Wheeler’s rule to account for the field penetration as strip thickness approaches the skin depth or even smaller. Based on the correct estimation of conductor loss in microstrip T-pattern resonator structures, fairly accurate extraction of dielectric loss tangent for the polyimide thin film was obtained. Meanwhile, experimental results also verified the validity of the modified conductor loss model in evaluating thin microstrip lines. It was shown that as the conductor thickness becomes approximately greater than twice the skin depth, both conventional Wheeler’s rule and its modified model agreed very well with each other in the conductor loss estimation. For the wide strip case, i.e. W / h ≥ 1, which is the case of microstrip T-pattern resonator for thin film characterization, a practical formula was obtained as follows.

130 ε ∂ ∂ ∂ ∂ Z s e   Z 0 Z 0  Z 0 Z 0  Eq. 6.1 α = C  − 2  − 2C + C c η  w ∂ ∂ t ∂ g ∂  2Z 0   h t  W h  where

1.25h  2h  ln  0.667 π t G = 1+ m 2 =   1.444 +W h 1.25  2h  e W + ()h + t ln  π  t  Thin film dielectric substrates, such as spin-coated and thermally cured polyimide thin film for 3D-MMIC applications, were successfully on-wafer characterized by using quarter-wavelength T-pattern microstrip resonator structures. Since the microfabrication process utilizes the photolithography fabrication technology widely used in microelectronics and compatible with sophisticated vector network analyzer measurement methods, they provide very high accuracy in the characterization of substrate dielectric constant. The analysis showed that the error contributions from resonant frequency and structure length measurements were much bigger than those from substrate thickness and conductor width measurements. For the PI2611 T-pattern measurement, the error of the calculated dielectric constant can be expressed approximately as ∆ε  ∆f ∆l   ∆h ∆W  r ≈ 1.122 + 2  + 0.08 + Eq. 6.2 ε     r  f l   h W  As for the measurement accuracy in determining loss tangent, there was a strong skin-depth effect on the conductor loss when metallization layer was thin. The measurement error of the conductor thickness contributed mostly to the error of dielectric loss tangent. And it was a very sensitive parameter, though an analytical expression of this error contribution was difficult to obtain because of the complexity of conductor loss model.

131 The purpose of studying the vertical interconnects in 3D MMICs is to understand the performance of interconnects in the high-density packaging and high-speed circuit integration. As for the circuit design, this understanding enables design engineers to incorporate the effect of interconnects into a complete system implementation. For this purpose, equivalent circuits of vertical interconnects allow design engineers to approximate the performance of associated discontinuities instead of every detail that can be obtained from the full-wave solution, which is more expensive and time-consuming. As a starting point for understanding the characteristics and performance of the vertical interconnects study of FEM simulations of the ideal structures serve well for this purpose. Simulations have shown that the confined viahole modules provide a significant measure in multiple chip modules (MCM) and in MMIC designs to prevent the signal interference between the densely integrated circuit components. For a good design, the combination of cylindrical via and circular through hole for the via module produced lower insertion loss and better return loss, since this combination had a lower degree of physical shape discontinuity. In this research, a unique fabrication technology for the purpose of building high aspect ratio via interconnects in 3D MMIC multilayer integration was developed from traditional electronic and MEMS microfabrication technologies. Different test structures were successfully fabricated to facilitate the vertical interconnect characterization. Additional and newer novel fabrication techniques developed in this research also enriched the family of RF MEMS technology. In order to accurately interpret the conductor loss of planar transmission lines of thin metallization layers, modifications on the conventional Wheeler’s rule were developed to account for the skin effects based on the penetration of fields into the conductor. The closed-form formulas or simplified equations were derived to readily evaluate the conductor loss in thin stripline and SCPWG transmission lines with wide strip widths. Measurement results confirmed the validation of these models. These results were also been incorporated into via characterization. For the wide strip case in a stripline, i.e. W/b > 0.35, a closed formula to evaluate the conductor loss by taking into account the skin effect can be expressed as follows.

132     t   t g    t   t   W  Coth   + Coth    bCoth   + tCoth  g     δ   δ    δ   δ  4 R ε Z  2 s s 2 2b − t  α = s r 0 +       +  s   s    Eq. 6.3 c 2 1 ln    η ()b − t  ()b − t π ()b − t  t       Similarly, the modified method was obtained for evaluating the conductor loss in SCPWG line, which was also applicable to conventional coplanar waveguide (CPW) transmission lines. A closed-form to evaluate conductor loss due to this thin conductor situation can be expressed as

R ∂Z a ∂Z a  t  ∂Z a  α = 0.023 s 0 − 0 − Coth  0 dB/m c  ∂ ∂  δ  ∂  Eq. 6.4 Z 0  S W  2 s  t  Experimental results showed that the size of the probe pads in RF measurement ports had significant influence on the accuracy of the data when their physical sizes were limited and at low frequencies their capacitive effect did not provide sufficient RF signal grounding. Therefore, to minimize the grounding effect of the measurement probe pads especially for lower frequency measurements, the direct grounding by the vias to provide a real common ground to the test structure was important to obtain the accurate characterization of the device under test. With accurate evaluation of the loss characteristics of each part in test structures, lumped-element equivalent circuit models for the vias can be derived from the measurement results. Experimental results revealed that at RF frequencies, vertical interconnect discontinuities may contribute significantly to the insertion loss and the phase change. The equivalent circuit for a stripline interconnect was verified by measurements from multiple interconnect test structures. These models are of great practical importance in a complex circuit design.

6.2. Recommendations for Future Work In this research although detailed and comprehensive attempts were made to investigate as much as possible the problems of very thin film characterization for 3D MMIC packaging, there are still some important issues that need to be addressed to improve on the thoroughness of the work. As for the thin film characterization, dielectric constant and loss tangent measurements for other polyimide films such as PI1111

133 dielectric layers can be obtained in the same way as done for the PI2611 thin films. In order to validate the conductor loss models in planar transmission lines, thick strip transmission lines should be good examples to demonstrate the decrease of conductor loss due to skin effect as the conductor thickness increases. Experimental data has shown the significance of the skin effect on the conductor loss in planar transmission lines. The closed-form formulas have been derived for the wide strip cases for both the microstrip and stripline transmission lines. It would be of practical importance to extend this modification to the narrow strip case. In this study, due to the limitations of the FEM simulation package, only ideal vertical interconnection structures were theoretically modeled. In the future, it is desirable to investigate more complicated structures with realistic materials and conductors including appropriate loss terms. In this way, more correlations between the equivalent circuits and the via module physical structures can be obtained. As for the characterization of vertical via modules, only several simple test structures were fabricated and tested. It is imperative for future work to fully understand the significance of the vertical via in the high frequency applications by investigating more sophisticated structures. If possible, a library of this kind of characterization is desirable for a better circuit design.

Figure 6.1 (a) CPW-to-stripline transition and its electric field, (b) electric field of CPW with ground plane and (c) electric field of stripline

In characterization of various circuit structures, CPW-to-stripline (or microstrip) transitions are needed for providing proper measurement ports. It has been shown that a

134 straight CPW-to-stripline transition introduces some discontinuities into the overall circuit characterization. By comparing the electric fields associated within the transition with the electric fields of the stripline or CPWG transmission lines (see Figure 6.1), the wave propagation mode conversion should be considered for a true understanding of the waves traveling through the transitions. The work presented here is the foundation for the realization of monolithically processed vertically interconnected 3D microwave integrated circuitry. Foundations for the essential components of the 3D-MMIC have been investigated and design guidelines have been presented. Design guidelines for incorporating the effects of thin metal layers for both the ground planes and circuit planes have been developed. As one of the essential components of the 3D-MMICs, vertical interconnects have been thoroughly investigated, characterized and design guidelines have been established. The next step is to process multiple sub-circuits with the help of these design guidelines.

135 References

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143 Appendices

Appendix A Derivation of Eq. 3.40 Using MathematicaTM

Using the formulations developed in Eq. 3.38 and Eq. 3.39 and characteristic impedance discussed in Section 3.1.1, the following derivation can be arrived.

144

145 Appendix B MathematicaTM calculation of conductor loss in thin microstrip

Based on the inference in Section 3.3.1, the conductor loss in wide-strip thin microstrip is compared using a Mathematica program as follows.

146

147 Appendix C Four-point probe measurement of metal conductivity

Four point probe based instruments use a long established technique [1-4] to measure the average resistance of a thin layer or sheet by passing current through the outside two points of the probe and measuring the voltage across the inside two points. If the spacing between the probe points is constant, and the conducting film thickness is less than 40% of the spacing, and the edges of the film are more than 4 times the spacing distance from the measurement point, the average resistance of the film or the sheet resistance is given by: π V V Rs = ≈ 4.53 ln 2 I I The thickness of the film (in cm) and its resistivity (in ohm cm) are related to Rs by: resistivity 1 Rs = = thickness conductivity × thickness Therefore one can calculate the resistivity (conductivity) if the thickness of a film is known, or one may calculate the thickness if the resistivity (conductivity) is known.

1. Valdes, L., Resistivity Measurements on Germanium transistors, Proceedings I.R.E., 42, Feb.1954, p420. 2. Uhlir, A., The Potentials of Infinite Systems of Sources and Numerical Solutions of Problems in Semiconductors Engineering, Bell System Technical Journal, Jan 1955, p105. 3. Smits F.M., Measurement of Sheet Resistivities with the Four-Point Probe, Bell System Technical Journal, May 1958, p711. 4. Irvin, J.C., Resistivity of Bulk Silicon and Diffused Layers in Silicon, Bell System Technical Journal, 41, p387, (1962). 5. Berry, R.W., Hall, P.M., Harris, M.T., "Thin Film Technology", Van Nostrand Reinhold Company, New York, NY, 1968.

148 Appendix D MATLAB program for thin film characterization

% This program is used to characterize the polyimide substrate. % --- Programmed by George Kang, October, 2000 clear all disp ('*** MATLAB program for the polyimide characterization. ***') W= input ('- measured microstrip width in microns, W: '); h= input ('- measured microstrip substrate height in microns, h: '); t= input ('- measured microstrip conductor thickness in microns, t: '); f= input ('- measured resonant peak frequency in GHz, f: '); f1= input ('- #1 measured 3dB frequency value in GHz, f1: '); f2= input ('- #2 measured 3dB frequency value in GHz, f2: '); IL= input ('- insertion loss at resonant freq in dB, IL: '); l= input ('- measured T-pattern resonant length in microns, l: '); n= input ('- harmonic #, odd-integer of the primary resonance, n: '); mu=4*pi*10^-7; %% free space permeability eps=8.854*10^-12; %% free space permittivity c=1/sqrt(mu*eps); %% light speed in free space ita=120*pi; %% free space impedance

% preliminary calculation of effective epsre pre_epsre=(n*c/(4*l*f*10^3))^2; meas_l=l; test_epsre=0.;

% From the microstrip structures designed for the characterization, % the following W/h case is always satified. % W/h > 1 and W/h > 1/2pi case F=1/sqrt(1+12*h/W); % effect of strip thickness C=t/h/2.3/sqrt(W/h); We2h=W/h+1.25/pi*t/h*(1+log(2*h/t)); while abs(test_epsre-pre_epsre)>10^-6

test_epsre=pre_epsre;

% characteristic impedance Z0 Z0=ita/sqrt(pre_epsre)/(We2h+1.393+0.667*log(We2h+1.444));

% compensation from open end, delta1 delta1=h*0.412*(pre_epsre+0.3)/(pre_epsre- 0.258)*(W/h+0.264)/(W/h+0.8);

% compensation from T-junction, delta2 D1=ita*h/(sqrt(pre_epsre)*Z0); % parallel plate line width fp=400*Z0/h; % cutoff frequency in GHz % displacement of the reference plane for the T-arm d2=D1*(0.5-(0.05+0.7*exp(-1.6)+0.25*(f/fp)^2)); delta2=W/2+d2;

% correction on the resonant length l=meas_l + delta1 + delta2;

149

%calculation of renewal pre_epsre pre_epsre=(n*c/(4*l*f*10^3))^2; end

% output of effective dielectric constant epsre=pre_epsre % calculation of epsr, dielectric constant of the substrate epsr=(2*epsre+F-1-C)/(1+F-C)

% Q factor of the circuit, T-pattern microstrip resonator % It is proven that the measured Q (loaded) is very close to the % unloaded Q see Carrol, Li & Chang, pp. 219-222, MTT-43-1, 1995 QL= f/abs(f2-f1); %% 3dB bandwidth measurement (loaded) Q=QL/sqrt(1-2*10^(-IL/10)); %% unloaded Q factor

%% Now the dielectric material loss tangent is computed as follows: %======This was used to calculate conductor loss======% For metal thickness greater than four times of the skin depth omiga=2*pi*f*10^9; sigma=5.813*10^7*0.46; %% sputtered copper conductivity as pure Rs=sqrt(omiga*mu/2/sigma); %% surface resisitivity sdepth=sqrt(2/omiga/mu/sigma)*10^6; %% skin depth in micron at resonant frequency %%%% conductor loss for W/h>1 case % A= 1+1/We2h*(1+1.25/pi*log(2*h/t)); % alphac_old= 6.1e-5/8.686*A*Rs*Z0*epsre/(h*10^- 6)*(We2h+(0.667*We2h)/(We2h+1.444)); % This result is not used in the following calculation. When for no correction, the above is used. %======

% conductor loss calculated from modified Wheeler's rule, Stracca's paper alphac=alphacloss(W,h,t,f,epsre,Z0);

% surface roughness correction delta=0.; %% estimated surface roughness deltas= 1/sqrt(pi*f*10^9*mu*sigma)*10^6; %% skin depth alphac_pri= alphac*(1+2/pi*atan(1.4*(delta/deltas)^2));

% Q factor due to conductor loss lumda=c/(f*10^9)/sqrt(epsre); %% guide wavelength beta=2*pi/lumda; %% propagation constant Qc= beta/2/alphac_pri;

% Q factor due to radiation lumda0=c/(f*10^9); %% free space wavelength R=(epsre+1)/epsre-(epsre- 1)^2/2/(sqrt(epsre))^3*log((sqrt(epsre)+1)/(sqrt(epsre)-1)); Qr=Z0/480/pi/R/(h*10^-6/lumda0)^2; % correction for radiation, here this effect is negligible due to very big Qr Q0=Q*Qr/(Qr-Q);

150

% computing loss tangent Qd= Q0*Qc/(Qc-Q0); tand= epsre*(epsr-1)/Qd/epsr/(epsre-1)

Function and subfunctions: function result=alphacloss(W,h,t,f,epsre,Z0)

%% calculate the conductor loss for thin strip in microstrips %% using Stracca's method, Giovanni B. Stracca, "A simple evaluation of %% losses in thin microstrips," pp 281-283, MTT-45-2, 1997 mu=4*pi*10^-7; %% free space permeability eps=8.854*10^-12; %% free space permittivity c=1/sqrt(mu*eps); %% light speed in free space ita=120*pi; %% free space impedance sigma=5.813*10^7*0.46; %% sputtered copper conductivity

%% dimensions in unit of microns (inputs) to meters WW=W*10^-6; hh=h*10^-6; tt=t*10^-6; omiga=2*pi*f*10^9; %% input frequency in GHz sdepth=sqrt(2/omiga/mu/sigma); %% skin depth at resonant frequency, in m Rs=1/(sigma*sdepth); %% surface resistance, in ohm/squ Rdc=1/(sigma*WW*tt); %% DC resistance, in ohm/m

Zs=(1+j)*Rs; %% metal wave impedance gamac=(1+j)/sdepth; %% metal propagation constant beta_eff=omiga*sqrt(mu*eps*epsre); %% microstrip lossless propagation constant

% calculate m value by calling derivatives m2=(-Fzdt(WW,hh,tt))/(Fzdh(WW,hh,tt)-Fzdt(WW,hh,tt)); m=sqrt(m2);

% correction factors Fw=coth(gamac*tt)+2*m/(1+m2)/sinh(gamac*tt); Fg=coth(gamac*tt); Ft=coth(gamac*WW/2);

% incremental impedances Zw=(Fzdh(WW,hh,tt)-2*Fzdt(WW,hh,tt))*Zs; Zt=-2*FzdW(WW,hh,tt)*Zs; Zg=Fzdh(WW,hh,tt)*Zs;

% conductor impedance per unit length (ohm/meter) Z_strip=Zw*Fw+Zt*Ft; Z_eff=Z_strip+Zg*Fg;

151 % propagation constant including conductor loss gama=j*beta_eff*sqrt(1-j*Z_eff/(beta_eff*Z0)); result=real(gama); % real part corresponding to conductor loss in Np/m return

%======% For the following subfunctions, Fz is equal to % (Wetoh[W, h, t] + 1.393 + 0.667 Log[Wetoh[W, h, t] + 1.444])^(-1) % and Wetoh = (W/h + 1.25/Pi*t/h*(1 + Log[(2*h)/t])

%------subfunction------function result = FzdW(W,h,t) %% calculate derivative of Fz vs W aratio=0.397887*t*(log(2*h/t)+1)/h; afunc=W/h+aratio+1.444; result=-(0.667/(h*afunc)+1/h)/(W/h+aratio+0.667*log(afunc)+1.393)^2; return %------

%------subfunction------function result = Fzdh(W,h,t) %% calculate derivative of Fz vs h aratio=0.397887*t*(log(2*h/t)+1)/h; afunc=W/h+aratio+1.444; bfunc=-aratio/h+0.397887*t/h^2-W/h^2; result=- (bfunc+0.667*bfunc/afunc)/(W/h+aratio+0.667*log(afunc)+1.393)^2; return %------

%------subfunction------function result = Fzdt(W,h,t) %% calculate derivative of Fz vs t aratio=0.397887*t*(log(2*h/t)+1)/h; afunc=W/h+aratio+1.444; cfunc=aratio/t-0.397887/h; result=- (cfunc+0.667*cfunc/afunc)/(W/h+aratio+0.667*log(afunc)+1.393)^2; return %------% End of subfunctions %======

152 Appendix E Procedure for extracting equivalent circuit using HP LIBRA Unix Version (v6.1)

Extraction of equivalent circuit from measured data or simulated results of full- wave solution is the process which tries to match as closely as possible the available S- parameters to the scattering matrix of the equivalent circuit by adjusting the component values. There is a method (in Libra) for accomplishing this function, using a Linear Test Bench, and placing the OUT_EQN and OPTIMIZATION test items in a test lab. In this method, equations are written in the OUT_EQN item in terms of S- parameter ratios of the simulated and targeted networks. These ratios are then placed in an optimization goal (OPTIMIZATION) item, which forces the simulated networks to agree with the targeted networks. The detailed procedure can be outlined as follows: • Create two design files (through the Schematic Bench window) and store them both in the Networks subdirectory under the active project (_prj) directory. o One file (call it target.dsn, for example) represents the targeted data, normally available measurement data or simulation results from other methods. This network can be constructed using the (Linear) Data File Elements (S2P) from the library with necessary ports (or ground). When specifying the FILE for the S2P file element, a tabulated S-parameter file with extension .s2p should contain the target data, and default directory to place it is <_prj>/data of the active directory. (Check out the special style to write the .s2p file.) Note: The S2P Data File Element can be used to incorporate user-defined S- parameters into any simulation where a 2-port network can be substituted by [S] matrix. o The second file (call it model.dsn) contains the equivalent circuit model. For optimization, the (un)constrained type (other than Real or else) should be chosen from each component specification window. During optimization their values can be updated by choosing Simulate>Update Optimization Values in Test Bench window. (Do not forget to relax the components in the equivalent circuit to allow optimization.)

153 • In the Test window, create a Linear Test Bench that contains all four S- parameters. This test bench does not need a frequency plan (the FREQUENCY item from Stimulus Controls) because in the test lab a frequency plan will be required. Since this test bench will be used by the two networks designed above, a Substitute Network (_2PORT) can be employed as a dummy 2-port network. Save this design, for instance, as model_tb.dsn. (_tb.dsn is added automatically.) • Create a test lab (a collection of test benches) and place the model_tb test bench in it twice (actually two test benches, B1 and B2 by default, will be used.) o To create a test lab, select File>New or click on the New Design icon on the toolbar from the Test window. Enter the Design Name in the New Design dialog box, select Test Lab for Design Type, then click OK. (The dimensional units can be declared in the Defaults window or include them here.) o To be consistent with the design names used so far, for the DUT of each linear bench (which of same test function) they call the previous design networks data and model (no extension .dsn in the string.). • In the test lab, place an OUT_EQN item that contains the following statements: Ratio_S11 = B1\S11 / B2\S11 Ratio_ S12 = B1\S12 / B2\S12 Ratio_ S21 = B1\S21 / B2\S21 Ratio_ S22 = B1\S22 / B2\S22 where B1 and B2 refer to the tag names assigned to the two test benches. S- parameters are transferred through the IDs so make sure in the equations the IDs match the measurement names in test benches (i.e., model_tb.dsn). • After specifying the equations above, place an optimization goal item (OPTIMIZATION from Optimization/DOE/Yield Controls) in the test lab. The following optimization goal statements should be specified in the OPTIMIZATION item: goal Ratio_S11 mag 1 1 goal Ratio_S11 ang 0 1 goal Ratio_S12 mag 1 1

154 goal Ratio_S12 ang 0 1 goal Ratio_S21 mag 1 1 goal Ratio_S21 ang 0 1 goal Ratio_S22 mag 1 1 goal Ratio_S22 ang 0 1 • Place a frequency plane Stimulus Control item (FREQUENCY) in the test lab that corresponds to the frequency range in the data file. Select Simulate> Optimization or click Optimization icon, choose a suitable optimizer (check the details on the methods), specify the Design Trials/Iterations and error, then run it.

A typical setup in the LIBRA test window for obtaining the equivalent circuit by matching two circuit performances is plotted as follows:

155 Appendix F Calculating conductor loss in thin stripline using MathematicaTM

Based on the inference in Section 3.3.1 and Section 5.3.1, the conductor loss in wide-strip thin stripline is compared using a Mathematica program as follows.

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159 Appendix G Calculating conductor loss in thin SCPWG line using MathematicaTM

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