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Design of Spin-Torque Transfer Magnetoresistive RAM and CAM 66 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 1, JANUARY 2010 Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed Wei Xu, Tong Zhang, Senior Member, IEEE, and Yiran Chen, Member, IEEE Abstract—With a great scalability potential, nonvolatile magne- of using magnetic fields, a new technique called spin-torque toresistive memory with spin-torque transfer (STT) programming transfer (STT) uses current of spin-aligned electrons (i.e., has become a topic of great current interest. This paper addresses spin-polarized current) to switch the state of MTJs. Because cell structure design for STT magnetoresistive RAM, content ad- dressable memory (CAM) and ternary CAM (TCAM). We propose of its greater scalability potential than conventional MRAM, a new RAM cell structure design that can realize high speed and STT MRAM has received a growing interest [9]–[12]. The reliable sensing operations in the presence of relatively poor mag- resistance state of MTJs can be detected by sensing the current netoresistive ratio, while maintaining low sensing current through steered through MTJs. Because of the relatively small MTJ re- magnetic tunneling junctions (MTJs). We further apply the same sistance values (e.g., a few kiloohms) and low magnetoresistive basic design principle to develop new cell structures for nonvolatile CAM, and TCAM. The effectiveness of the proposed RAM, CAM ratio (typically less than 100%), how to achieve high-speed and TCAM cell structures has been demonstrated by circuit simu- read without incurring large through-MTJ sensing current is lation at 0.18 m CMOS technology. a nontrivial task. More importantly, since both writing and Index Terms—Content addressable memory (CAM), mag- read operations in STT MRAM steer current through MTJs, netic tunneling junction (MTJ), magnetoresistive random access the through-MTJ sensing current must be sufficiently less than memory (MRAM), spin-torque transfer (STT) magnetoresistive the writing current to avoid read disturb. This makes it more memory, ternary CAM (TCAM). challenging to achieve high-speed read in STT MRAM. Most prior work on MRAM circuit design employs a com- pact 1 MTJ per cell structure, and the read operation is realized I. INTRODUCTION by direct current sensing, i.e., by clamping a voltage to the bit line (BL) through a current source, the through-MTJ sensing RIVEN by the ever exploding demands for higher ca- current is converted to a sensing voltage that is compared to D pacity nonvolatile solid-state data storage in numerous a reference voltage, as illustrated in Fig. 1(a). As pointed out pervasive computing and communication devices, flash mem- in [8] and [13], such direct current sensing strategy tends to ories have been the fastest growing segment in global semi- result in relatively complex and large peripheral circuits. Due conductor industry [1]. Nevertheless, besides several drawbacks to the more severe constraint on through-MTJ current in STT including low speed, limited endurance, and difficulty of inte- MRAM, it can be more challenging to apply this direct sensing gration in system-on-chip (SoC), flash memories face signifi- strategy to realize high-speed read in STT MRAM. A 2-MTJ cant scaling problems at the 32 nm node and beyond [2]–[4]. per cell structure [8], [13], as illustrated in Fig. 1(b), has been Hence, it has been a topic of great current interest to search for used to improve the read speed at the cost of cell size. Each new nanoscale nonvolatile digital memories that have greater cell contains a pair of differential MTJs ((i.e., 1 MTJ has high scalability potentials and achieve better performance in terms resistance and another has low resistance) that forms a voltage of speed, endurance, and/or SoC integration. Magnetoresistive divider, which may greatly simplify the peripheral sensing cir- random access memory (MRAM) is one of the most promising cuits and improve the sensing speed and reliability. Clearly, the candidates that have recently attracted a lot of attentions. sensing speed and reliability of such 2 MTJ per cell structures The basic building block in MRAM is magnetic tunneling are also subject to the magnetoresistive ratio and through-MTJ junction (MTJ), and the data storage is realized by configuring sensing current constraints, particularly in STT MRAM. To fur- the resistance of MTJs into one of two possible states (i.e., ther push the sensing speed limit, sakimura et al. [8] proposed high-resistance state and low-resistance state). In conventional to add a two-transistor common-source amplifier in each cell to MRAM design practice, magnetic fields are explicitly gen- amplify the output of the 2-MTJ voltage divider. Nevertheless, erated and used to switch the state of MTJs [5]–[8]. In stead in spite of the much higher sensing speed and reliability, the 2-MTJ per cell design strategies presented in [8], [13] result in Manuscript received April 07, 2008; revised July 31, 2008. First published much larger cell area than a simple 1 MTJ per cell structure. March 27, 2009; current version published December 23, 2009. In this paper, we develop a new STT MRAM structure that W. Xu and T. Zhang are with the Department of Electrical, Computer, and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY 12180 USA applies the same voltage-divide-based sensing strategy in [8] (e-mail: [email protected]; [email protected]). and [13] to improve the sensing speed and reliability, while Y. Chen is with Alternative Technology Group, Seagate Technology, Bloom- using only 1 MTJ and one transistor in each cell. In the pro- ington, MN 55435 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/TVLSI.2008.2007735 posed STT MRAM structure, each BL has one reference cell 1063-8210/$26.00 © 2009 IEEE XU et al.: DESIGN OF SPIN-TORQUE TRANSFER MAGNETORESISTIVE RAM AND CAM/TCAM 67 Fig. 2. Two configurations of MTJ. (a) Parallel (low resistance). (b) Anti- parallel (high resistance). Fig. 1. Conventional sensing strategy when using (a) 1 MTJ per cell and hundred microamperes [9], [10], which directly enables a sig- (b) 2 MTJ per cell. nificant reduction of memory write energy compared with tra- ditional magnetoresistive memories. Let and denote the high and low MTJ resistance, respectively, we define tunneling that is used to form a voltage divider with the selected cell magnetoresistance ratio (TMR) as . A larger TMR during the sensing operation. Both the transistors and MTJs in makes it easier to distinguish the two resistance states and hence the reference cell and selected cell participate the voltage di- is highly desirable. As shown in [9], for an MTJ with MgO bar- vide, and the voltage-modulated resistance of transistors rier layer and a dimension of 125 nm 220 nm, the high and can largely amplify the overall resistance ratio. As a result, a low resistance are about 5.5 and 2.5 K , respectively, leading significant improvement of sensing voltage margin, and hence, to a typical TMR of 155%. Since both write and read involve sensing speed/reliability can be achieved. We evaluate this pro- through-MTJ current, the sensing current has to be (much) lower posed design strategy through simulations at 0.18 m CMOS than the write current threshold in order to avoid read disturb technology node. We consider different BL sizes, ranging from (e.g., sensing current has to be 100 A and below). 64 up to 256 cells per BL. For 256 cells per BL, we show that the access time of only 7.5 ns is possible while the through-MTJ III. PROPOSED STT MRAM STRUCTURE sensing current is only about 70 A, assuming that the high and low MTJ resistance fall into the range of 5–6 K and 2–3 K , In this paper, we propose an STT MRAM structure that re- respectively. alizes high-speed sensing by forming an MTJ-based voltage di- Using the same design principle, we further develop vider with the same principle, as illustrated in Fig. 1(b). Besides MTJ-based cell structures for nonvolatile content addressable the significant cell size penalty, the straightforward 2-MTJ per memory (CAM) and ternary CAM (TCAM). Accessed by the cell structure shown in Fig. 1(b) may not be able to realize suffi- content other than address, CAM and TCAM are ideally suited ciently large sensing voltage margin for STT MRAM. This can for any systems that require a large amount of data search, e.g., be illustrated as follows. Let and denote the high and low Ethernet address lookup, cache tags, data compression, etc. supply voltages of the 2-MTJ voltage divider. Hence, the output We develop 2-MTJ per cell CAM structure and 3-MTJ per cell voltage of the voltage divider can be either TCAM structure that can achieve high search speed at small through-MTJ search current. As a test vehicle, we designed match-lines of 144 CAM cells and 144 TCAM cells at 0.18 m CMOS technology. The worst case search time is about 5 ns for CAM at sensing current of 55 A and 8 ns for TCAM at sensing current of 87 A, where the search noise margin is over which leads to a voltage margin of 500 mV. The paper is organized as follows. Section II provides the fundamental concept of STT MRAM. Section III describes the Because cannot be too large in order to avoid read dis- proposed MRAM cell structure. Section IV describes the MTJ- turb and TMR is typically small, the voltage margin may not be based CAM cell structures. Finally, a summary of this paper is sufficiently large. For example, let us consider MTJs whose provided in Section V.
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