1 Computer Hardware Engineering (IS1200) Computer Organization and Components (IS1500)

Fall 2017 Lecture 8: Optional for IS1200, compulsory for IS1500

Fredrik Lundevall Slides by David Broman and Fredrik Lundevall

Part I Part II Part II David Broman Bistability and Flip-Flops, Registers, Synchronous Sequential Circuits [email protected] Latches and Register Files and Finite State MachinesSlides version 2.0

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Course Structure

Module 1: C and Assembly Module 4: Design Programming LE1 LE2 LE3 EX1 LAB1 LE9 LE10 EX4 S2 LAB4

LE4 S1 LAB2

Module 2: I/O Systems Module 5:

LE5 LE6 EX2 LAB3 LE11 EX5 S3

Module 3: Logic Design PROJ Module 6: Parallel Processors (IS1500 only) START and Programs LE7 LE8 EX3 LD-LAB LE12 LE13 EX6 S4

Proj. Expo LE14

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Agenda

Part I Part II Bistability and Latches Flip-Flops, Registers, and Register Files

Photo by Daniel Max. License: CC-BY-2.0. http://www.publicdomainpictures.net/view- Edited by F Lundevall. Original at: image.php?image=8284&picture=staplade- https://www.flickr.com/photos/35080385@N08/33255487236 stenar&large=1

Part III Synchronous Sequential Circuits and Finite State Machines

Part I Part II Part II Bistability and Flip-Flops, Registers, Synchronous Sequential Circuits Latches and Register Files and Finite State Machines

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Part I Bistability and Latches

http://www.publicdomainpictures.net/view-image.php? image=8284&picture=staplade-stenar&large=1

Acknowledgement: The structure and several of the good examples are derived from the book “Digital Design and ” (2013) by D. M. Harris and S. L. Harris.

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Combinational vs. Sequential Logic

Combinational Logic Design (previous lecture) • Output depends only on the input. S1 S0 • There is no memory.

N N D0 00 A D1 01 Y D2 10 Cout + C Circuit without memory B in D3 11 N

Sequential Logic Design (this lecture) • Output depends on current and prior input values. • As a consequence, sequential logic has memory. • Today, we will learn about:

Latches Flip-Flops Registers

Circuit with memory We will discuss other kinds of memories in course module 5: Memory hierarchy.

Part I Part II Part II Bistability and Flip-Flops, Registers, Synchronous Sequential Circuits Latches and Register Files and Finite State Machines

6 E Bistability

What is the difference Notation convention: between these two circuits? T-connections Q connect, four way Q Q Answer: None, but connections do not. both circuits contain a cycle. Q What is the value of Q?

Analysis by considering two cases: This circuit has 2 0 1 stable states. Hence, 1 0 Q Q it is a memory that Case I: Case II: can store 1 bit of Q = 0 Q = 1 information. 0 1 1 0 Q Q Problem: We cannot Both cases are stable. decide what to store The circuit is bistable. (there is no input) Part I Part II Part II Bistability and Flip-Flops, Registers, Synchronous Sequential Circuits Latches and Register Files and Finite State Machines

7 E SR Latch If S and R are zero, the What is the behavior of this An SR latch can be circuit “remembers” the circuit? Analyze the 4 cases built with different previous Q value, called for inputs S and R. gates. This is the Q . We have a memory pre abstract symbol for an R SR latch. Q S R Q Q R Q 0 0 Qpre Qpre 0 1 0 1 1 0 S Q Q 1 0 S 1 1 0 0 S is the SET signal and R Problem 1. The awkward case S=1, R=1 is the RESET signal. results in that both Q and Q are zero. Problem 2. Mixes the issues of what and when updates are made. It is hard to design large circuits this way. Part I Part II Part II Bistability and Flip-Flops, Registers, Synchronous Sequential Circuits Latches and Register Files and Finite State Machines

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D Latch

The D latch is an improvement over the SR latch. Symbol describing a D latch: It has a data input D, and a clock input CLK. CLK CLK R Q Q Q D Q S Q Q D Also called a transparent latch or level-sensitive latch. CLK D Q Q • CLK = 1, the latch is 0 ? Qpre Qpre transparent (D flows 1 0 0 1 through to Q). 1 1 1 0 • CLK = 0, the latch is The symbol "?" means "don’t care". It is used to opaque (the latch simplify truth tables (we can skip one row in this case). blocks data from flowing Sometimes X, D, or a dash "–" is used for "don’t care". through).

Part I Part II Part II Bistability and Flip-Flops, Registers, Synchronous Sequential Circuits Latches and Register Files and Finite State Machines

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Part II Flip-Flops, Registers, and Register Files

Photo by Daniel Max. License: CC-BY-2.0. Edited by F Lundevall. Original at: https://www.flickr.com/photos/35080385@N08/33255487236 Acknowledgement: The structure and several of the good examples are derived from the book "Digital Design and Computer Architecture" (2013) by D. M. Harris and S. L. Harris.

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D Flip-Flop

A flip-flop is edge-triggered and These symbols describe D Flip-Flops. not level-triggered. Condensed CLK symbol

Q D Q CLK CLK N D D Q D Q in Qout The D flip-flop (the standard flip-flop) Q Q Qout copies D to Q on the rising edge, and master slave remembers its state all other times.

Case I: CLK = 0 Case II: CLK = 1 The master is transparent and the The slave is transparent and the slave is opaque. D flows to N. in master is opaque. N flows to Qout.

Part I Part II Part II Bistability and Flip-Flops, Registers, Synchronous Sequential Circuits Latches and Register Files and Finite State Machines

11 E Resettable and Enabled Flip-Flops

A resettable flip-flop resets the flip-flop The line above the signal to 0 when a reset signal is active. name shows that the reset CLK signal is active low: The reset is active on 0. D Q D True or False? D Q Q RESET RESET "This resettable flip-flop is synchronously resettable, An enabled flip-flop has an input EN. Its state changes meaning that it resets on a only when EN = 1 and there is a raising clock edge rising clock edge. It is is not (Called WR EN CLK asynchronously in the exercise). resettable where the reset is independent of the clock." 0 D Q Q D Q D 1 Answer: True EN

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Register

An N-bit register consists of N flip- that share the same clock input. CLK CLK 4 4 D 3:0 Q3:0 D3 Q3

D 2 Q2 Abstract form of a 4-bit register built out of D 4-bit register. D flip-flops (using condensed 1 Q1 symbol notation). Note that registers can also have enable signals, reset D signals etc. 0 Q0

Part I Part II Part II Bistability and Flip-Flops, Registers, Synchronous Sequential Circuits Latches and Register Files and Finite State Machines

13 E Output Enable Register

Exercise: Create a 2-bit register that has an output enable (OE) input signal. If OE = 0 then Q is floating, else it outputs the Recall the tristate buffer registers’ state. with floating output (Z)

Answer: E A Y CLK OE E 0 0 Z 0 1 Z A Y D Q 1 0 0 1 1 1 1 1 D Q

D OE 0 Q0

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Register File (1/2)

A register file can be used to read and write data using an address. Writing M bits is done by giving write data to WD3, write address to A3, and setting write enable CLK WE3 to 1. WE3 A1 RD1 N M A2 RD2 N M A3 Reading M bits from read N data port RD1 is done by WD3 M giving an N-bit read address to A1. Same for the second This is a multi-ported register file. Two read port (RD2 and A2). read ports and one write port. Reads and writes can be done in parallel.

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Register File (2/2)

WE3 WD3 CLK A1 8 8 00 EN Decoder 01 RD1 2 00 10 8 A3 11 01 8 8 10 A2 11 EN 00 8 8 01 RD2 10 8 EN 11

Example: Register file with 8 8 address depth N = 2 EN (4 different addresses) and 8-bit words (M = 8). Part I Part II Part II Bistability and Flip-Flops, Registers, Synchronous Sequential Circuits Latches and Register Files and Finite State Machines

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Part III Synchronous Sequential Circuits and Finite State Machines

Acknowledgement: The structure and several of the good examples are derived from the book “Digital Design and Computer Architecture” (2013) by D. M. Harris and S. L. Harris.

Part I Part II Part II Bistability and Flip-Flops, Registers, Synchronous Sequential Circuits Latches and Register Files and Finite State Machines

17 Register-Transfer Level - E Synchronous Sequential Circuits

It is hard to analyze large asynchronous circuits that contain cycles. Solution: Design synchronous sequential circuits, also called designing at the register-transfer level (RTL), which means that • is combined with registers • states are only updated on clock edges

Which of the following circuits are using RTL design / sequential synchronous logic?

CLK CLK

Combinational Combinational Combinational Logic Circuit Logic Circuit Logic Circuit

Yes, with no feedback No, because of latch. No, has a cycle without register in the path

Part I Part II Part II Bistability and Flip-Flops, Registers, Synchronous Sequential Circuits Latches and Register Files and Finite State Machines

18 E Finite State Machines (FSMs)

Synchronous Sequential Logics can be defined as Finite State Machines Moore Machine (M inputs, N outputs, k states)

CLK next M state N Next State k state k inputs Output Logic Logic outputs

Mealy Machine (M inputs, N outputs, k states) Outputs can be directly dependent on the inputs CLK next M k state k state inputs Next State N Logic Output Logic outputs

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A Simple Mealy Machine Example

A test-run, using input values chosen by random. CLK A D Q clock A B C Q D Y EN Y init 1 1 0 1 0 1 1st 1 1 1 0 1 1 B 2nd 1 0 0 1 0 1 C

After 1st, 2nd etc. positive clock edge.

CLK next M k state k state inputs Next State N Logic Output Logic outputs

Part I Part II Part II Bistability and Flip-Flops, Registers, Synchronous Sequential Circuits Latches and Register Files and Finite State Machines

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Edge-Triggered Timing Methodology

How fast can we run a circuit? A race condition is when the The clock period must be longer than the values of state variables depend worst-case delay in the circuit. on the relative speed of logic CLK elements in the circuit. next M k state k state inputs Next State N Logic Output Logic outputs

The worst-case delay is computed

delay = tprop + tcombinational + tsetup + tskew for the feedback loop through the next state logic. Time to propagate Necessary time before through the flip-flops the rising clock edge. or registers. Compensate for clock skew: The longest delay in the clock signals reach state combinational logic. elements at different time.

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21 Reading Guidelines

Module 3: Logic Design

Lecture 7: Combinational Logic Design • H&H Chapters 1.5, 2.1-2.4, 2.6, 2.8-2.9

Lecture 8: Sequential Logic Design • H&H Chapters 3.1-3.3 (not 3.2.7), 3.4.1-3.4.3, 5.2.1-5.2.2, 5.5.5

Reading Guidelines See the course webpage for more information.

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Summary

Some key take away points: • Combinational Logic vs. Sequential Logic: Combinational logic has no memory, whereas sequential logic includes memory. • Latches vs. Flip-Flops vs. Registers vs. Register File Flip-flops are edge triggered, registers combine flip-flops, and register files uses addresses to access data. • Synchronous vs. Asynchronous Logic Design Synchronous Design makes design work easier.

• Mealy vs. Moore Machines Both are finite state machines (FSMs). Outputs from Moore machines depend only on the state, outputs from Mealy machines depend on state and input.

Thanks for listening!

Part I Part II Part II Bistability and Flip-Flops, Registers, Synchronous Sequential Circuits Latches and Register Files and Finite State Machines