HW1: (Page 71: 2, 3)

n 2. For each of the following circuits, identify CS100: Introduction to the input combinations that produce an Computer Science output of 1.

Lecture 6: Data Manipulation -- computer n 3. In each circuit below, the rectangles architecture, machine language & program represent the same type of gate. Based on execution the input and output information given, identify whether the gate involved is an AND, OR, or XOR.

HW1: (Page 72: 5) Review:

n Data compression Address Contents After step1 After step2 After step3 q Lossless 00 AB 02 02 02 n Run-length encoding n Frequency-dependent encoding 01 53 53 53 53 n Dictionary encoding 02 D6 D6 01 01 q Lossy n GIF 03 02 02 02 53 n JPEG n TIFF n MPEG Step 1: Move the contents of the cell whose address is 03 to the cell at n MP3 address 00. n Communication errors Step 2: Move the value 01 into the cell at address 02. q Parity bits (even versus odd) Step 3: Move the value stored at address 01 into the cell at address 03. q Checkbytes q Error correcting codes

Chapter 2: Data Manipulation Figure 2.1 CPU and main memory connected via a bus n 2.1 Computer Architecture n 2.2 Machine Language n 2.3 Program Execution

1 Computer Architecture Stored Program Concept n Central Processing Unit (CPU) or processor A program can be encoded as bit patterns q Arithmetic/Logic unit versus Control unit and stored in main memory. From there, the n Perform operations on data n Coordinate the machine’s activities CPU can then extract the instructions and q Registers : execute them. In turn, the program to be n for temporary storage of info. executed can be altered easily. n General purpose n Special purpose n Bus q Wires connect CPU to main memory n Motherboard q Main circuit board

Terminology Machine Language Philosophies n Machine instruction: An instruction (or n Reduced Instruction Set Computing (RISC) command) encoded as a bit pattern q Few, simple, efficient, and fast instructions recognizable by the CPU q Example: PowerPC from Apple/IBM/Motorola n Machine language: The set of all n Complex Instruction Set Computing (CISC) instructions recognized by a machine q Many, convenient, and powerful instructions n Easy to program n A simple instruction in a CISC design may require a multi-instruction sequence in a RISC design. q Example: Pentium from Intel

Machine Instruction Types Figure 2.2 Adding values stored in memory n Data Transfer: copy data from one location to another q LOAD: fill general-purpose register with the contents of a memory cell q STORE: transfer the contents of a register to a memory cell n Arithmetic/Logic: use existing bit patterns to compute a new bit patterns q Basic arithmetic operations: ADDITION, DIVISION q Boolean operations: AND, OR, XOR q Other operations: SHIFT, ROTATE n Control: direct the execution of the program q Direct the execution of the program q JUMP:

2 Figure 2.3 Dividing values stored in Figure 2.4 The architecture of the memory machine described in Appendix C (16 general- purpose registers and 256 memory cells)

Parts of a Machine Instruction Figure 2.5 The composition of an instruction for the machine in n Op-code: Specifies which operation to Appendix C (2 bytes for each instruction) execute n Operand: Gives more detailed information about the operation

q Interpretation of operand varies depending on op- code

Figure 2.6 Decoding the instruction Figure 2.7 An encoded version of 35A7 the instructions in Figure 2.2

3 Questions: Questions: n 1. The following are instructions written in the n 1. The following are instructions written in the machine language described in Appendix C. machine language described in Appendix C. Rewrite Rewrite them in English them in English q 368A: STORE the contents of register 6 in memory cell q 368A number 8A q BADE q BADE: JUMP to location DE if the contents of register A equals to that of the register 0. n 2. Translate some instructions in English into machine language of Appendix C. n 2. Translate some instructions in English into machine language of Appendix C. q Load register number 3 with the hexadecimal q LOAD register number 3 with the hexadecimal value 56: value 56 2356 q Move the contents of register F to register 4. q MOVE the contents of register F to register 4: 40F4

Program Execution Figure 2.8 The machine cycle n Controlled by two special-purpose registers q Program counter: address of next instruction q Instruction register: current instruction n Machine Cycle q Fetch q Decode q Execute

Figure 2.9 Decoding the instruction Figure 2.10 The program from Figure 2.7 B258 stored in main memory ready for execution

4 Figure 2.11 Performing the fetch step Figure 2.11 Performing the fetch step of the machine cycle of the machine cycle (cont’d)

Questions: Questions:

n 1. Suppose the memory cells from address 00 to 05 in the n 1. Suppose the memory cells from address 00 to 05 in the machine described in Appendix C contain the (hexadecimal) bit machine described in Appendix C contain the (hexadecimal) bit patterns given in the following table: patterns given in the following table: Address Contents Address Contents 00 14 Instructions: Instructions: 00 14 Instructions: Instructions: 01 02 1402 1402(LOAD) 01 02 1402 1402(LOAD) 02 34 02 34 03 17 3417 3417(STORE) 03 17 3417 3417(STORE) 04 C0 04 C0 C000 C000(HALT) C000 C000(HALT) 05 00 05 00 If we start the machine with is program counter containing 00, If we start the machine with is program counter containing 00, what bit pattern is in the memory cell whose address is what bit pattern is in the memory cell whose address is hexadecimal 17 when the machine halts. hexadecimal 17 when the machine halts. (34)

Questions: Questions:

n 2. Suppose the memory cells from address B0 to B8 in the machine n 2. Suppose the memory cells from address B0 to B8 in the machine described in Appendix C contain the (hexadecimal) bit patterns given in the described in Appendix C contain the (hexadecimal) bit patterns given in the following table: following table: Address Contents Instructions: Instructions: Address Contents Instructions: Instructions: B0 13 B0 13 B1 B8 13B8 13B8(LOAD) B1 B8 13B8 13B8(LOAD) B2 A3 B2 A3 B3 02 A302 A302(ROTATE) B3 02 A302 A302(ROTATE) B4 33 B4 33 B5 B8 33B8 33B8(STORE) B5 B8 33B8 33B8(STORE) B6 C0 B6 C0 B7 00 C000 C000(HALT) B7 00 C000 C000(HALT) B8 0F B8 0F a. If the program counter starts at B0, what bit pattern is in register a. If the program counter starts at B0, what bit pattern is in register number 3 after the first instruction has been executed? number 3 after the first instruction has been executed? (0F) b. What bit pattern is in memory cell B8 when the halt instruction is b. What bit pattern is in memory cell B8 when the halt instruction is executed. executed. (C3)

5 Next Lecture: n Instructions, communicating & other Architectures n Reading assignments: Chapter 2.4, 2.5,2.6 n The 3rd homework assignment will be announced

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