The Delta-Sigma Modulator

A Circuit for All Seasons

Behzad Razavi

Delta-Sigma modulators (DSMs) are a Figure 1(b) depicts a simple implemen- tor, a multibit quantizer (an ADC), class of oversampling analog-to-dig- tation where the integrator is approxi- and a multibit digital-to-analog con- Dital converters (ADCs) that perform mated by a low-pass filter. verter (DAC). “quantization noise shaping,” thus The principal difficulty with the In the 1970s, the potential of DSMs achieving a high signal-to-noise ratio delta modulator is was further explored. (SNR). An efficient solution for resolu- that the output digital Candy proposed the tions above approximately 12 b, DSMs representation in fact Delta-Sigma use of the structure are extensively used in analog and RF contains only the de- modulators are a for robust analog-to- applications. In this article, we study rivative of the input, as class of oversampling digital conversion in the fundamentals of this vast field. can be seen by noting analog-to-digital 1974 [3] and, along that VDF = # out dt in converters with Ching and Al- The Delta Modulator Figure 1(a). This dif- that perform exander, in 1976 It is helpful to first study the prede- ferentiation alters the “quantization demonstrated a reso- cessor of DSMs, namely, the delta signal spectrum, at- noise shaping,” lution of 13 b with a modulator. Shown in Figure 1(a), the tenuates the low-fre- thus achieving a 1-b quantizer in the high signal-to- latter consists of a 1-b quantizer (e.g., quency content of the loop [4]. These two noise ratio. a single comparator) and an integra- signal, and amplifies papers pointed out tor, both placed in a negative-feedback high-frequency noise. that the overall reso- loop. The high loop gain ensures that lution increases as

VVF . in and hence the digital output Brief History the quantizer is clocked faster and its is a representation of the analog input. To avoid the differentiation effect output circulates around the loop more in Figure 1(a), Inose et al. [1] clev- frequently. An important observation erly moved, in 1962, the integra- made by Candy was that the overall out- tor from the feedback path to the put noise is the “first difference” of the 1−Bit forward path, introducing the “3R quantizer’s additive noise, exhibiting a Quantizer 2 TCK + modulator” shown in Figure 2. Here, spectrum of the form sin (/~ 2), V D in out the high-loop gain forces the run- where TCK is the quantizer clock period – ning average of Dout to follow Vin. Of [3]. That is, the noise is suppressed at low VF course, Dout also contains the quan- frequencies. Candy also recognized that (a) tization noise created by the quan- the performance negligibly degrades tizer, but with certain interesting with the imperfections of the analog CK and useful alterations. components within the loop. Vin The 3R modulator structure actu- The first integrated DSM was evi- Dout ally predates the work by Inose et al. dently reported by van de Plassche VF In a patent filed in 1961 [2], Brahm in 1977 [5]. Using a continuous-time c1 discloses the system shown in Figure 3, (CT) integrator, the ADC achieved R1 where the loop contains an integra- a resolution of about 17 b in bipo (b) lar technology. In 1978, Tewksbury and Hallock described higher-order DSMs, present- Figure 1: (a) A delta modulator and (b) its + simple implementation. Vin D ing the architecture shown in Figure 4 – out (but attributing it to G.R. Ritchie) [6].

Digital Object Identifier 10.1109/MSSC.2016.2543061 They also showed that the quantiza- Date of publication: 21 June 2016 Figure 2: A DSM. tion noise spectrum is attenuated

10 SPRING 2016 IEEE SOLID-STATE CIRCUITS MAGAZINE 22 62 20 26 10 18 4 24 Analog 2 to 1 Digital 12 16 14 28 5 8 7 6 S F G Digital 1 F G to F Analog 2 G 2 4 F G 40 42 50 d 110 KC 4 M S OSC. d G 1 1 F d G 2 2 F d G 4 4 F Addition d G 8 8 F or Subtraction d G 16 16 F

60 56 54 52 58

Figure 3: The DSM proposed by Brahm in 1961. according to the shaping function ()1 - z-1 N , where N denotes the order + + ∗ sn . . . A/D sn (the number of integrators). – – In 1981, an n-type metal-oxide-semi- . . . D/A conductor (NMOS) implementation using a single passive discrete-time integra- Figure 4: A high-order DSM attributed to Ritchie. tor was reported [7], and in 1982, a patent was filed disclosing a loop with two active switched-capacitor integrators [8]. CMOS realizations followed in 1986 ADC [9] and 1988 [10]. Vin It is interesting that some authors Dout use the term “3R modulator” and others use the term “R 3 modulator” to refer to the circuit. One argument in favor of the former is that the loop first subtracts and t1 ta tb tc t2 t then accumulates. Figure 5: Oversampling to create correlation between consecutive samples. Basic Operation

Suppose we wish to digitize the ana- twice the signal bandwidth. In this Vin at ta, tb, and tc, we create corre- log waveform shown in Figure 5. case, the samples at t1 and t2 exhibit lated quantization errors between A Nyquist-rate ADC would sample little correlation, and so do their quan- consecutive samples. From another and quantize Vin at t1 and t2, with tization errors. On the other hand, if perspective, if the signal changes fts =-1/( 21t ) slightly greater than we additionally sample and digitize slowly enough from t1 to ta, then

IEEE SOLID-STATE CIRCUITS MAGAZINE SPRING 2016 11 tees that Y(s) tracks X(s)—and that Q(s) is suppressed—so long as H(s) pro- Vin ADC DAC VDAC Q(s) vides a high loop gain. For Hs()= 1/,s q(t) + this occurs at low frequencies. X(s) H(s) Y(s) The foregoing observations lead – V in VDAC to the first-order 3R modulator (a) (b) shown in Figure 7(a), where the ADC is realized as a 1-b quantizer (a sin- + gle comparator) and the DAC as two X(s) H(s) ADC DAC Y(s) – switches producing ±VREF. By virtue of its high gain, the comparator (c) enforces a virtual ground at node X, but due to the discrete-time nature Figure 6: (a) A negative-feedback system with noise injected near the output, (b) an ADC/ of the loop, only the average value DAC cascade modeled in terms of additive noise, and (c) the rejection of quantization noise by negative feedback. of VX remains close to zero. This in turn means that the average differ-

ence between Vin and VDAC, and hence the quantization errors incurred by is an integrator, then Hs# ()= 1/s between Vin and Dout, is nulled. For these two samples are almost equal. and hence YQ//=+ss()1 . We say example, if VX crosses from negative We then surmise that subtracting the the spectrum of Q is “shaped” by to positive, the comparator and the quantization error of one sample the feedback loop, an effect also DAC apply a pulse to the integrator from the next can reduce the overall observed for the phase noise of oscil- so as to return VX toward zero. Fig- quantization noise. lators in phase-locked loops. ure 7(b) illustrates how the running This method of noise suppression In the next step, consider the ADC– average of the digital output tracks can also be explained in the frequency DAC cascade depicted in Figure 6(b), the analog input [10]. domain, culminating in noting that VDAC is equal The 1-b quantizer in Figure 7(a) the concept of noise to the ideal analog in- suffers from enormous quantiza- shaping. First, consider This method put plus the ADC’s tion noise, q(t). One might won- the negative-feedback of noise quantization noise, q(t), der, then, whether a more resolute system shown in Fig- suppression can if the DAC is ideal. It is quantizer can be used instead. This also be explained ure 6(a), where an therefore expected that question leads to two different archi- in the frequency unwanted signal Q(s) placing this cascade tectures, namely, loops containing a domain. is injected “near” the within the feedback loop multibit quantizer or a greater num- output but inside the of Figure 6(a) can reduce ber of integrators. Before describing loop. The transfer function from Q the overall quantization noise for some these solutions, we need to derive the to Y can be chosen to provide a high- frequency range [11]. Illustrated in Fig- noise-shaping properties of the first- pass behavior. For example, if H(s) ure 6(c), such an arrangement guaran- order modulator.

0.6 CK 0.4 X Vin Dout 0.2

+VREF 0

–0.2 VDAC –0.4

Modulator Input, Quantizer Output –0.6 050 100 150 200 250 –VREF Time (t/T) (a) (b)

Figure 7: (a) A simple first-order DSM with a 1-b quantizer, and (b) input and output waveforms.

12 SPRING 2016 IEEE SOLID-STATE CIRCUITS MAGAZINE Formulation of Noise Shaping Let us examine how the quantiza- 2 1 – z –1 tion noise introduced by the quan- + gu tizer in Figure 8(a) propagates to the x ADC y 4 output. We assume a discrete-time – integrator and express its output as DAC 0 f f f uk()Tuss=-[(kT11)]+-gk[( )]Ts , B S 2 where gk[( -=11)]Txss[(kT--)] (a) (b) yk[( - 1)]Ts . The quantizer output is given by yk()Tuss=+()kT qk()Ts , Figure 8: (a) First-order DSM for noise shaping calculations and (b) its noise-shaping function. and reaches the DAC output un- changed if the DAC is ideal. Substituting for gk[( - 1)]Ts and for yk[( - 1)]Ts , 3 we obtain zero to fB is proportional to 1/,M The problem of DAC nonlinear- revealing the strong dependence of ity proves serious because DSMs the performance upon the oversam- typically target high resolutions, at yk()Tuss=-[(kT11)]+-xk[( )]Ts pling ratio. which the “raw” device mismatches --yk[( 1)]Tqss+ ()kT . (1) In addition to noise shaping, DSMs produce considerable distortion. For provide two other advantages over this reason, loops containing multi-

Since uk[( --11)]Tyss[(kT-=)]-q Nyquist-rate ADCs. First, for a given bit DACs employ “dynamic element

[(kT- 1)]s , we have amount of kT/C noise, the sampling matching” techniques to reduce this capacitors in the former can be smaller nonlinearity [5]. than those in the latter by a factor of yk()Txss=-[(kT1)]+ qk()Ts M. This can be intuitively explained Higher-Order DSMs --qk[( 1)]Ts . (2) by noting that the extra samples taken Another approach to reducing the in Figure 5 are eventually combined noise of the quantizer is to replace

As expected, the output quantiza- with those at t1 and t2 (by means of it with another 3R modulator [Fig- tion noise is equal to the difference a “decimator”), benefiting from kT/C ure 9(a)]. Here, the outer loop fur- between the quantization errors noise (and op amp noise) averaging. ther shapes the quantization noise incurred by two consecutive sam- Second, the antialiasing filter in the of the inner loop, yielding a shaping ples. Taking the z transform of both former has a more relaxed selectivity function of the form ()1 - z-12 for sides yields than in the latter. the 1-b quantizer’s noise. The area -12 under ||1 - z from zero to fB is Yz()=+zX--11()zz()1 - Qz(). (3) DSMs with Multibit Quantizers now proportional to 1/M5, a marked In the spirit of Brahm’s patent (Fig- reduction compared to that of the The output thus contains the input ure 3) and to lower the quantization first-order loop. with no change but just a delay. noise, we can digitize the integra- Providing identical outputs, the two The quantization noise experiences tor output with more than one bit DACs in Figure 9(a) can be merged, a 1 - z-1 transfer function. We say of resolution and feed the result to resulting in the more compact architec- the system provides a “signal trans- a multibit DAC. Typically realized as ture shown in Figure 9(b). Exemplified fer function” (STF) equal to z-1 and a a flash stage, the quantizer injects by the implementation in Figure 9(c) “noise transfer function” (NTF) equal proportionally less noise as its reso- [10], this simple, robust topology is to 1 - z-1 . lution increases. The performance the most commonly used DSM for To determine the output noise of the system, however, is limited moderate-performance applications. It spectrum, we replace z in 1 - z-1 by the DAC nonlinearity, as pointed can be shown that such imperfections with exp()jT~ s and multiply the out by van de Plassche in 1979 [5]. as capacitor mismatch, op amp offset, spectrum of q(t), SfQ (), by |e1 - xp In contrast to the two-level DAC op amp gain error, and comparator off- 22 ()-=jT~rss|(2 sin fT ). Figure 8(b) in Figure 7(a), a multibit DAC exhib- set have much less impact here than plots this noise-shaping function, its nonlinearity in its input–output in, for example, pipelined ADCs. The revealing that integrated quantiza- characteristic if its constituent com- order of the loop can be increased tion noise can be small if the input ponents (resistors, capacitors, or cur- further by adding more integrators, signal bandwidth ffBs% /.2 The rent sources) have mismatches. This but instability becomes problematic, quantity Mf= (/sB2)/f is called the phenomenon can be viewed in Figure requiring other measures. “oversampling ratio” (OSR) and sig- 8(a) as an undesirable term subtract- nifies how far above the Nyquist ed by the DAC from x and hence indis- Problem of Tones rate the system operates. The area tinguishable from nonlinearity in the As explained earlier, the average under the curve in Figure 8(b) from input path. output of a DSM tracks the input signal.

IEEE SOLID-STATE CIRCUITS MAGAZINE SPRING 2016 13 designs, those by Brahm and Inose et al., for example, employed continu- + + X (s) Y (s) ous-time integrators, but, as switched- – – capacitor techniques matured in CMOS technology, discrete-time integrators DAC became more common. In the late 1990s, it was recognized that continuous-time integrators offer certain DAC advantages, and continuous-time DSMs (a) (CTDSMs) rapidly rose as a formidable contender. It is important to note, how- + + X (s) Y (s) ever, that even CTDSMs are discrete- – – time feedback loops, still facing tone and stability issues. DAC Depicted in Figure 10 is a simple (b) CTDSM realization of a second-order VREF+ loop, where the current sources act as VREF– 1-b DACs. This arrangement provides C2C2 C2 S2 SS3 three advantages over its discrete-time C1 S3 S22 SS11 S44 S1 C1C SS44 counterparts: 1) the sampling is per- – + – + Inn Out formed by the comparator, obviating + – + – SS44 the need for highly linear front-end S2 C1 S1 C1 SS44 S3 SS33 (bootstrapped) samplers, 2) the DSM S2 S2 C2C2 C2 VREF– presents less input capacitance and VREF+ (c) kickback noise, easing the demand on the preceding circuit, and 3) the two integrators naturally provide antialias- Figure 9: (a) A second-order DSM, (b) the simplified architecture, and (c) a discrete-time ing filtering, simplifying the other fil- implementation. ter stages in the signal path. CTDSMs entail their own draw- backs. First, the jitter in the comparator clock modulates the amount C of charge delivered by the feed- 1 C 2 back DACs to the integrators. This R CK issue has been addressed by vari- 1 R Vin – 2 ous techniques, e.g., the use of – + + switched-capacitor DACs [12]. Sec- ond, the integrator op amps must have enough bandwidth to avoid I2 I1 slewing, a difficult issue because the comparator quantization noise trav- eling through the DACs and arriv- ing at the integrators presents fast Figure 10: A simple second-order CTDSM. changes. This translates to a greater power consumption than that of op amps in discrete-time DSMs. Third,

What happens if Vin in Figure 2 is within the signal band. These “tones” the signal-dependent delay of the constant? Since the loop is periodi- corrupt the digitized signal. The tones comparator, each time it approaches cally clocked and Vin does not change tend to be smaller in magnitude in metastability, also modulates the with time, we surmise that the out- higher-order loops or at higher overs- DACs’ outputs, leading to distortion. put is also periodic. For example, if ampling ratios, but one must often The comparator must therefore be

VVin = 00.,01 REF then Dout consists of incorporate “dithering” to break their designed for a short regeneration one ONE and another 999 ZEROs so as periodicity and convert them to noise. time so that metastable states occur to produce such an average. Repeat- infrequently enough to negligibly af- ing with a period of 1000Ts, the output Continuous-Time DSMs fect the signal. Fourth, the thermal therefore exhibits harmonics given The evolution of DSMs has made a noise of R1 and I1 in Figure 10 limits by mfs/1000, many of which can fall 360° turn over the years. The earliest the performance.

14 SPRING 2016 IEEE SOLID-STATE CIRCUITS MAGAZINE branches that are driven by 25%- A duty-cycle local oscillator phases? + No, it does not. The steady-state LO LO X Y swing remains the same. I in V R AB 1 C1 C2 – References [1] H. Inose, Y. Yasuda, and J. Muraka- B mi, “A telemetering system by code modulation—Δ-Σ modulation,” IEEE Trans. LO Space Electron. Telemetry, vol. 3, pp. 204– 209, Sept. 1962. [2] C. B. Brahm, “Feedback integrated system,” U.S. Patent 3,192,371, Sept. 1961. [3] J. C. Candy, “A use of limit cycle oscil- lations to obtain robust analog-to-dig- Iin ital conversion,” IEEE Trans. Commun., vol. COM-22, pp. 298–305, Mar. 1974. [4] J. C. Candy, C. Y. Ching, and D. S. Al- exander, “Using triangularly weighted interpolation to get 13-bit PCM from V1 a sigma-delta modulator,” IEEE Trans. V Commun., vol. COM-24, pp. 1268–1275, AB Nov. 1976. [5] R. van de Plassche, “A five-digit analog- digital converter,” IEEE J. Solid-State Circuits, vol. SSC-12, pp. 656–662, Dec. 1977. t [6] S. K. Tewksbury and R. W. Hallock, “Overs- ampled, linear and predictive noise-shaping coders of order N > 1,” IEEE Trans. Cir- cuits Syst., vol. CAS-25, pp. 436–447, July 1978. [7] T. Misawa, J. E. Iwersen, L. J. Loporcaro, and J. G. Ruch, “Single-chip per channel F i g u r e 11: Steady-state waveforms in a commutated circuit. codec with filters utilizing Δ-Σ modulation,” IEEE J. Solid-State Circuits, vol. 16, pp. 333–342, Aug. 1981. [8] K. Shenoi and B. Agrawal, “Delta-sigma modulator with switch capacitor imple- Note on StrongArm Latch port of a Global System for Mobile mentation,” U.S. Patent 4,439,756, Jan. In my article on the StrongArm latch Communication (GSM) receiver so 1982. [9] T. Hayashi, Y. Inabe, K. Uchimura, and T. [13], I had traced the circuit to a 1992 as to attenuate by 20 dB a 0-dBm Kimura, “A multistage delta-sigma modu- paper by Kobayashi et al. The idea was blocker at 20-MHz offset. What is- lator without double integration loop,” in ISSCC Dig. Tech. Papers, Feb. 1986, pp. in fact filed for a patent by Madden sues does such a circuit face? 182–183. and Bowhill on 27 June 1988 in the Such an approach faces three [10] B. Boser and B. A. Wooley, “The design of sigma-delta modulation analog-to- United States and by Kobayashi’s coau- issues. First, from Smith’s equa- digital converters,” IEEE J. Solid-State thor, Nogami, in Japan on 13 July 1988. tion, the array must employ a large Circuits, vol. 23, pp. 1298–1308, Dec. 1988. capacitance to provide a small [11] H. A. Spang and P. M. Schultheiss, “Reduc- Questions for the Reader bandwidth with a 50-Ω source re- tion of quantizing noise by use of feedback,” IRE Trans. Commun. Syst., vol. 10, 1) Explain in the time domain why sistance. Second, the on-resistance pp. 373–380, Dec. 1962. 1-z-1 represents a high-pass function. of the switches must be about 5 Ω, [12] M. Ortmann, F. Gerfers, and Y. Manoli, “Jitter insensitive feedback DAC for con- 2) Explain why the comparator clock demanding a high power in the LO tinuous-time ΣΔ modulators,” in Proc. Int. jitter in a discrete-time SDM such drive circuitry. Third, the switches Conf. Electronics, Circuits, and Systems, 2001, pp. 1049–1052. as that in Figure 9(c) is not critical. experience a large voltage swing in [13] B. Razavi, “The StrongArm latch,” IEEE the presence of a 0-dBm blocker, ex- Solid-State Circuits Mag., vol. 7, no. 2, pp. 12–17, Spring 2015. Answers to Last Issue’s Questions hibiting considerable nonlinearity.

1) The commutated capacitors of Fig- 2) Does V1 in Figure 11 change if the ure 11 are placed at the antenna circuit contains four capacitive

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