Outline EECS 373 Design of Microprocessor-Based Systems • Context and review • Memory • PCB design

Robert Dick University of Michigan

Lecture 12: Memory and PCBs

16 February 2017

Slides inherited from Mark Brehob. 1 2

Context and review Outline

• ADC and DAC operation and error •  Speed / accuracy / monotonicity trade-offs. Context and review • • Prototyping Memory •  Breadboards. PCB design  Soldering.  Wire wrap. • Memory  Flash  Speed, functionality, reliability trade-offs.

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Memory: why? Memory array types

• You'll be dealing with this a lot in your projects. Memory Arrays • A little review now can save you trouble later. Random Access Memory Serial Access Memory Content Addressable Memory (CAM)

Read/Write Memory Read Only Memory Shift Registers Queues (RAM) (ROM) (Volatile) (Nonvolatile)

Serial In Parallel In First In Last In Static RAM Dynamic RAM Parallel Out Serial Out First Out First Out (SRAM) (DRAM) (SIPO) (PISO) (FIFO) (LIFO)

Mask ROM Programmable Erasable Electrically Flash ROM ROM Programmable Erasable (PROM) ROM Programmable (EPROM) ROM (EEPROM)

5 6 Nonvolatile memory types Floating gates

• Ferroelectric RAM: polarization changed by electric field.  Write: hot- injection or Fowler-Nordheim tunneling. DRAM/flash-like. Electical − High voltage on control gate >> operating voltage polarization instead of floating gate. − are trapped in the floating gate. Reading → current pulse on write? − Will not discharge for many years. 150 ns. 1012 cycles.  Erase? Fowler-Nordheim tunneling. • Phase change memory: amorphous (off) vs. crystalline (on). 5ns to 100 ns control gate write. ns read. 108 cycles. floating gate • Magnetoresistive RAM. ns read. Slightly more for write. Many cycles. source drain • Programmable metallization cell: redox filament. 10s of ns read, write. 1010 cycles. • Flash: ns read, ms write.  Read by seeing whether it acts like a or a wall. • EEPROM: ns read, ms write.  Tend to self-destruct after 105 write/erase cycles. • SRAM/DRAM: ns read and write.

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Outline PCBs: why?

• Context and review • Memory • Even if you aren't making one for your project, need to • PCB design understand how they work for debugging / reverse engineering.

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Printed circuit board design Basic terminology • Interconnects: traces. • Physical support. • Inside of a given “layer” • Electrical connecions. traces which cross are – Traces have restricted electrically connected. dimensionality. • Can have muliple conducive – Very thin, high layers by stacking/bonding resistance. boards. – Holes/vias and pads. • Through-hole: Having holes in – Rework is hard. the PCB designed to have pins put through the holes. – Contrast with surface mount where device goes on top.

htp://www.linkwitzlab.com/Pluto/supplies-subw.htm, • Surface mount. htp://www.musicfromouterspace.com/analogsynth/SINGLEBUSSKEYBOARD2007/SINGLEBUSSKEYBOARD2007.php Parts of a PCB Copper Vias (pads & traces) Silkscreen Soldermask (white) (green) • Someimes you need to connect traces on layers. – Use a via: a plated through hole • Generally smaller than a through hole for a pin.

Via Bottom side Drill holes 13

The layered construcion of a PCB: Clearances a six layer board • There will be space between the traces, other traces, and plated holes. – You need to meet the requirement of the manufacturer.

16 Figure from alium.com

What do do with layers? How to design PCB

• Mostly orthogonal rouing layers. 1. Create schemaic • Ground planes to increase local power supply 2. Place parts capacitance and minimize resistance. • Power plane for similar reason. 3. Route interconnect • More layers → higher cost. 4. Generate iles Step 1: Create schemaic Example schemaic

• The irst thing you want is something that looks like a textbook circuit diagram. It just shows the devices and how they are connected. – Someimes you will worry about pinouts here (say when working with a microprocessor maybe). – But usually you don’t. • No noion of layout belongs here, although the schemaic connecivity will inluence layout.

Why a schemaic? Step 2: Place parts

• Communicaion and formalizaion are main • You need to place the paterns on the board. goals. – You need to not overlap them to that the components can actually it on the board. – This is probably what your sketch on would – You want to leave room for the traces to connect look like. everything. – You can ind and ix bugs more easily here than • This is very much an art form. the PCB layout. – In fact you will ind people who rant about “sloppy” or “unprofessional” placements. • Some tools will do this for you. • Someimes they screw up.

Paterns Step 3: Route interconnect

• Once you know what it is you • A route is a connecion between devices. want to build, you need to igure out how to lay it out on – It may consist of muliple traces the board. • There are design rules which include: – You need to know how big each piece is, and where the holes – Minimum trace width need to be placed. – Minimum spacing between traces and holes • Each device has a patern. – You will occasionally need to – Minimum spacing between holes and holes. create a patern. • Rules vary by manufacturer. • Units vary my manufacturer. Issues of measure Trace width

• PCB designers use odd terminology. • In general most PCB manufactures seem to have • trace-width minimums of 6-10 thous. A “thou” is a thousandth of an inch. – Most are willing to go smaller for a price. • A “mm” is a millimeter • A rule of thumb is to use a 50 thou minimum for • A “mil” is a thousandth of an inch. power/ground and 25 for everything else. – Thou is generally preferred over mil to avoid confusion, but – This is to drop the resistance of the traces. – In general you are worried about heat dissipaion most tools/vendors use mil. • There are lots of guidelines for width/power but in general you are looking at: – A 10cm trace needs to be 10 thou wide if it will carry 1 amp. – 5 amps at 10cm would require 110 thou.

Trace width coninued Rat’s nest.

• The problem with wide traces is that they are • Rat’s nest shows device hard to route. placements and connecions but not rouing. – In paricular you might wish to go between pins of – Automaically generated a device. for you. • One soluion is to be wide normally and “neck – Someimes before down” when you have to. placement, someimes – This is more reasonable than you think. ater. • Think resistors in series. – Varies by tool.

Rouing for real Rouing quality • You can use an autorouter to route your traces – Some people hate these as the design will be “ugly”. – Saves a lot of ime. – Oddly, not always as good as a person can do. • But much faster. • Sill generally need to do some (or all) of the rouing by hand – Very, very tedious. The schemaic captures the logical circuit design Step 4: Generate iles

• Once the design is done, a set of iles are generated. – Each ile describes something diferent. • Copper on a given layer. • Silkscreen. • Solder mask. – Most iles are in “Gerber” format. • Human-readable (barely) ASCII format. • Has commands like draw and ill. – Drill iles are a diferent format called Excellon. • Human-readable (barely) ASCII with locaions and diameters for the holes. • Generally you zip all these iles up and ship them as a single ile to the PCB manufacturer. – Oten a good idea to include the design ile(s) too.

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Floorplanning captures part locaions The auto-router places tracks on the board, saving ime

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Another design, all the way to producion Another simple design, all the way to producion

 Simple design that solved a hard problem.  Deployed at many sites around U.S.

35 36 Not a simple design The layered construcion of a PCB: A six layer board

 Note component density  Can mount components on each side.  Relationship between PCB layout, pinouts, and external components important.  LED.  Battery.  Others, e.g., big inductors.  Form (and board shape) follows function.  RF subsystem physical design tricky.

37 38 Figure from alium.com

Doesn't need to be expensive / complex

 Can CAD/CAM mill away solid Cu layer.  Can use lithography. − Photoresist. − Mask (can print with laser printer). − Projector. − Etchant (many are dangerous to breathe and touch). − Safe way to dispose of Cu-containing soluion.