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D5.5 Innovative HPC Trends and the Hidalgo Benchmarks HiDALGO D5.5 Innovative HPC Trends and the HiDALGO Benchmarks Document Identification Status Final Due Date 31/05/2020 Version 1.0 Submission Date 19/06/2020 Related WP WP5 Document Reference D5.5 Related D3.1, D3.2, D5.1, Dissemination Level (*) PU Deliverable(s) D5.2, D5.3 Lead Participant PSNC Lead Author Marcin Lawenda Contributors PSNC Reviewers Konstantinos Nikas USTUTT (ICCS) ECMWF Nabil Ben Said ICCS (MOON) Keywords: New promising technologies, HPC, benchmarks, scalability, efficiency, Exascale, Global Challenges, Global Systems Science This document is issued within the frame and for the purpose of the HiDALGO project. This project has received funding from the European Union’s Horizon2020 Framework Programme under Grant Agreement No. 824115. The opinions expressed and arguments employed herein do not necessarily reflect the official views of the European Commission. The dissemination of this document reflects only the author’s view and the European Commission is not responsible for any use that may be made of the information it contains. This deliverable is subject to final acceptance by the European Commission. This document and its content are the property of the HiDALGO Consortium. The content of all or parts of this document can be used and distributed provided that the HiDALGO project and the document are properly referenced. Each HiDALGO Partner may use this document in conformity with the HiDALGO Consortium Grant Agreement provisions. (*) Dissemination level: PU: Public, fully open, e.g. web; CO: Confidential, restricted under conditions set out in Model Grant Agreement; CI: Classified, Int = Internal Working Document, information as referred to in Commission Decision 2001/844/EC. Document Information List of Contributors Name Partner Dineshkumar Rajagopal USTUTT Sergiy Gogolenko USTUTT Dennis Hoppe USTUTT Natalie Lewandowski USTUTT Krzesimir Samborski PSNC John Hanley ECMWF Milana Vuckovic ECMWF Nikela Papadopoulou ICCS Petros Anastasiadis ICCS Document History Version Date Change editors Changes 0.1 20/05/2020 Marcin Lawenda TOC, Introduction 0.2 04/05/2020 Krzesimir Chapter 1 and 4 Samborski, Marcin Lawenda 0.3 04/05/2020 Nikela Chapter 6 Papadopoulou, Petros Anastasiadis 0.35 05/05/2020 Dineshkumar Chapter 2 and 3 Rajagopal, Sergiy Gogolenko, Dennis Hoppe, Natalie Lewandowski 0.36 05/05/2020 John Hanley, Annex 1 Milana Vuckovic 0.4 20/05/2020 Marcin Lawenda Chapter 2, 3 and 4, conclusion, executive summary, Document name: D5.5 Innovative HPC Trends and the HiDALGO Benchmarks Page: 2 of 66 Reference: D5.5 Dissemination: PU Version: 1.0 Status: Final Document History Version Date Change editors Changes 0.7 30/05/2020 Konstantinos First review Nikas, Nabil Ben Said 0.8 05/06/2020 Marcin Lawenda Addressing project review comments. Final version to be submitted. 0.9 17/06/2020 Marcin Lawenda Review and approve it. 1.0 19/06/2020 F. Javier Nieto Final approval Quality Control Role Who (Partner short name) Approval Date Deliverable Leader Marcin Lawenda (PSNC) 17/06/2020 Quality Manager Marcin Lawenda (PSNC) 19/06/2020 Project Coordinator Francisco Javier Nieto de Santos (ATOS) 19/06/2020 Document name: D5.5 Innovative HPC Trends and the HiDALGO Benchmarks Page: 3 of 66 Reference: D5.5 Dissemination: PU Version: 1.0 Status: Final Table of Contents Document Information .............................................................................................................. 2 Table of Contents ....................................................................................................................... 4 List of Tables .............................................................................................................................. 7 List of Figures ............................................................................................................................. 7 List of Acronyms ......................................................................................................................... 8 Executive Summary .................................................................................................................. 10 1 Introduction....................................................................................................................... 12 1.1 Purpose of the document ........................................................................................ 12 1.2 Relation to other project work ................................................................................ 12 1.3 Structure of the document ...................................................................................... 13 2 System components .......................................................................................................... 14 2.1 General-purpose CPUs ............................................................................................. 14 2.1.1 Intel x86 ............................................................................................................. 14 2.1.2 AMD x86 ............................................................................................................. 17 2.1.3 ARM .................................................................................................................... 20 2.1.4 POWER – OpenPOWER ...................................................................................... 22 2.1.5 SPARC ................................................................................................................. 24 2.2 Accelerators ............................................................................................................. 26 2.2.1 FPGA ................................................................................................................... 26 2.2.2 GPGPU ................................................................................................................ 27 2.2.3 Vector Co-Processor .......................................................................................... 29 2.3 Memory Technologies ............................................................................................. 29 2.3.1 DDR-SDRAM ....................................................................................................... 30 2.3.2 NVRAM ............................................................................................................... 30 2.4 Exascale architectures and technologies ................................................................. 32 2.4.1 Quantum Computing ......................................................................................... 32 2.4.2 Massively Parallel Processor Arrays ................................................................... 33 2.4.3 ARM-based Microservers with UNIMEM ........................................................... 33 Document name: D5.5 Innovative HPC Trends and the HiDALGO Benchmarks Page: 4 of 66 Reference: D5.5 Dissemination: PU Version: 1.0 Status: Final 2.4.4 FPGA based Microservers with UNILOGIC ......................................................... 35 3 Tools and libraries ............................................................................................................. 38 3.1 Performance tools.................................................................................................... 38 3.1.1 Exa-PAPI ............................................................................................................. 38 3.1.2 HPCToolkit .......................................................................................................... 38 3.1.3 TAU ..................................................................................................................... 39 3.1.4 Score-P ............................................................................................................... 39 3.1.5 VampirServer ..................................................................................................... 39 3.1.6 Darshan .............................................................................................................. 40 3.1.7 Relevance to HiDALGO ....................................................................................... 40 3.2 Mathematical libraries ............................................................................................. 40 3.2.1 NumPy ................................................................................................................ 40 3.2.2 SuperLU .............................................................................................................. 41 3.2.3 PetSc ................................................................................................................... 41 3.2.4 SLATE ................................................................................................................ 41 3.2.5 Relevance to HiDALGO ....................................................................................... 42 3.3 Open standards and programming libraries ............................................................ 42 3.3.1 MPI ..................................................................................................................... 42 3.3.2 OpenMP ............................................................................................................. 42 3.3.3 CUDA/OpenCL .................................................................................................... 43 3.3.4 Relevance to HiDALGO ......................................................................................
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