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A Morphological Array Image Processor Controller Chip Set Rochester Institute of Technology RIT Scholar Works Theses 2-1-1997 A Morphological array image processor controller chip set Christopher Insalaco Follow this and additional works at: https://scholarworks.rit.edu/theses Recommended Citation Insalaco, Christopher, "A Morphological array image processor controller chip set" (1997). Thesis. Rochester Institute of Technology. Accessed from This Thesis is brought to you for free and open access by RIT Scholar Works. It has been accepted for inclusion in Theses by an authorized administrator of RIT Scholar Works. For more information, please contact [email protected]. A MORPHOLOGICAL ARRAY IMAGE PROCESSOR CONTROLLER CHIP SET by Christopher J. Insalaco A thesis submitted In partial fulfillment ofthe requirements for the degree of Master ofScience In Computer Engineering Approved by: Prof. _ George A. Brown, Thesis Advisor Prof. _ Robert E. Pearson Prof. _ Roy S. Czernikowski, Department Head Department of Computer Engineering College ofEngineering Rochester Institute ofTechnology Rochester, New York February, 1997 A MORPHOLOGICAL ARRAY IMAGE PROCESSOR CONTROLLER CHIP SET I Christopher J. Insalaco hereby grant permission to the Wallace Library of the Rochester Institute of Technology to reproduce my thesis in whole or in part. Any reproduction will not be for commercial use or profit. Date Christopher J. Insalaco A Morphological Array Image Processor Controller Chip Set Christopher J. Insalaco 11 Rochester Institute of Technology Abstract A MORPHOLOGICAL ARRAY IMAGE PROCESSOR CONTROLLER CHIP SET by Christopher J. Insalaco The design, simulation and layout of a controller chip set for a morphological array image processor shall be discussed. These VLSI chips in conjunction with the Morphological Array Processor (MAP) and Arithmetic Logic Unit (ALU) chip sets perform the morphological image processing operations of erosion and dilation on 512x512 pixel, 8-bit gray scale images using a 7x7 windowing matrix in real time (60 frames per second). The controller chip set design allows for pipelining of successive MAP's as well as operation on 1024x1024 pixel, 8-bit gray scale images. To facilitate the design, additional scaleable CMOS standard library cells and corresponding parameterized schematic library components were designed and integrated with the RIT CMOS standard cell library designed by Computer Engineering graduate student Larry Rubin as part of his Masters thesis1. In particular, additional D flip-flops with both Q and Q bar outputs, and-or- inverts, or-and-inverts, CMUXes, and MOSIS 64 and 84 pin pad rings were created. The cells were designed to be fabricated using the Metal Oxide Semiconductor Implementation System (MOSIS) scaleable CMOS 2.0 pm N- well (SCN) process. A complete set of Cadence design rule verification tools were also integrated with the existing CAE tool set to perform design rule checking (DRC), electrical rule checking (ERC), layout versus schematic checking (LVS), and layout parameter extraction (LPE) for the MOSIS SCN 2.0 pm N-well dense rule set. To verify the CMOS standard cell designs, test A Morphological Array Image Processor Controller Chip Set Christopher J. Insalaco jii chips were designed and sent to MOSIS for fabrication. The layout and design rule verification of the final two test chips, test chips five and six, was performed by the author. Test chip four contains a variety of MUXes and D flip-flops, test chip five contains a variety of transfer gates and inverters. The controller chip set consists of a 64 pin control chip (Controller) and an 84 pin memory controller chip (Mem_Control). The controller chips provide the ability to selectively process 512x512 or 1024x1024 image sizes by modifying "size" the pullup or pulldown of a bit. A selectable delay was implemented, through the pullup or pulldown setup of three delay bits, in the Controller to allow the Controller to be used with the single chip VLSI MAP design, the seven chip VLSI MAP design, and the Actel gate array MAP. The controller chip set allows successive MAPs to be pipelined by connecting the next Controllers pipeline start pin to the previous stages pipeline start next pin. A Morphological Array Image Processor Controller Chip Set Christopher J. Insalaco iv TABLE OF CONTENTS ABSTRACT iii LIST OF FIGURES vii LIST OF TABLES ix L INTRODUCTION 1 EL HISTORICAL REVIEW 2 A. Design Before theLibrary 2 B. Test Chips 3 C. The Commission ofaMorphological Chip Set 5 DI. THEORY 7 A. Morphology 7 1. EUCLIDEANMORPHOLOGY 8 2. DIGITAL MORPHOLOGY. 12 3. GRAYSCALE MORPHOLOGY 14 B. Design Rule Checking 16 IV. MATERIALS AND APPARATUS 23 A. Mentorand Cadence Tools 23 B. TektrontxLogic Verifier 27 V. METHOD OF PROCEDURE 27 A. Cadence DraculaH Layout Verification Tools Setup 29 B. Additional Standard Cells 31 C Test Chips 5 and 6 37 D. MorphologicalArray Processor Controller Design 40 1. The Functional Design Architecture ofthe MAP Controller Chip 40 2. The Top Level Design ofthe MAP Controller Chip Set 66 3. The Logic Design ofthe Controller andMemjOontrol 75 4. The Logic Simulation ofthe Controller andMemControl. 91 5. The Circuit Design ofthe Controller andMemControl 93 6. The Circuit Simulation ofthe Controller andMemControl 93 7. The MorphologicalArray Processor Top Level Simulation 94 8. The Layout ofthe Controller andMemControl 95 9. Suggested Testing Methodologyfor the Controller andMemControl 98 VL RESULTS 98 VH. DISCUSSION 101 Image Processor Controller A Morphological Array Chip Set Christopher J. Insalaco v VHL CONCLUSIONS 102 A. Future Work 103 APPENDIX A 105 DRC.COM File 105 APPENDIX B 109 LVS.COM File 109 APPENDIX C Ill LPE.COMFile Ill APPENDIX D 114 Simulation Files 114 1. Start Blank Physical Simulation File 114 2. Start Blank Physical Simulation Results 117 3. Start Blank Logical Simulation File 118 4. StartBlank Logical Simulation Results 120 APPENDIX E 121 Layout Plots 121 REFERENCES 125 BD3LIOGRAPHY 127 Image Processor J. A Morphological Array Controller Chip Set Christopher Insalaco vi LIST OF FIGURES Number Page Figure 1 SpacingCheck 19 Figure 2 Enclosure Check. 19 Figure 3 Transistor Overlap Check 20 Figure 4 Transistor Spacing Check 20 Figure 5 CMUX4 Schematic 32 Figure6 DLAT Schematic 33 Figure 7 DLATAR Schematic 34 Figure 8 ND3_2 Schematic 35 Figure9 NR3_2 Schematic 36 Figure 10 Test_Chip_5 Schematic 38 Figure 11 Test_Chip_6 Schematic 39 Figure 12 Image and WindowMatrices 43 Figure 13 MorphologicalArrayProcessorArchitecture 44 Figure 14 Blanking Bits 48 Figure 15 Blankingpart 1 53 Figure 16 Blankingpart 2 54 Figure 17 Blankingpart 3 55 Figure 18 Blanking part 4 56 Figure 19 Blankingpart 5 57 Figure 20 Blankingpart 6 58 Figure21 Blankingpart 7 59 Figure 22 Blankingpart 8 60 Figure 23 Blankingpart 9 61 Figure24 Blankingpart 10 62 Figure 25 Blankingpart 11 63 Figure 26 Blankingpart 12 64 Figure 27 Image_Processor Schematic 67 Figure 28 Controller_Chtp Schematic 79 Figure 29 Controller Schematic 80 Figure 30 VarJDelay Schematic 81 Figure 3 1 Bus_Select Schematic 82 Figure 32 Mem_Select Schematic 83 Figure 33 StartBlank Schematic 84 Figure 34 BlankCounter Schematic 85 Figure 35 Mem_Control_Chip Schematic 86 Figure 36 Mem_Control2 Schematic 87 Figure 37 Mem_Control Schematic 88 Figure 38 Mem_Counter Schematic 89 Figure 39 MUX2xl0 Schematic 90 Figure 40 Control Timing Diagram 92 Figure41 PowerRouting Architecture 97 Figure 42 Start BlankPhysical Simulation Output 117 Processor ControEer Set A Morphological Array Image Chip Christopher J. Insalaco vii Figure43 Start_Blank Logical Simulation Output 120 Figure 44 SCCCB Layout 121 Figure 45 SCCCBA Layout 122 Figure 46 SCCCBNA Layout 123 Figure 47 SCCCBNO Layout 124 A Morphological Image Processor Controller Array Chip Set Christopher J. Insalaco viii LIST OF TABLES Number Page Table 1 Binary Plxel Values and Their Decimal Equivalents 41 Table 2 Blanking Control Values ForAll IndexValues 48 Table 3 Blanking Control Values 50 Table 4 Blanking Control Values (cont'd) 51 Table 5 Controller Inputs / Outputs 69 Table 6 MemControl Inputs / Outputs 73 Table 7 WriteEnable Truth Table 77 Table 8 RIT CMOS Standard Cell Library Components 99 A Morphological Array Image Processor Controller Chip Set Christopher J. Insalaco jx ACKNOWLEDGMENTS To Linda and Michelle, who make it all worthwhile. The author wishes to thankJeff Correll for his help with the cell library and the incorporation of the REMEDI design rule checker into the Chipgraph macros, Shishir Ghate for his help with the cell library and ALU design and the integration of the library with Cellstation, Jeff Hanzlik for his help with the logical definition of the MAP, Jens Rodenberg for the MAP Architecture section and the logical design of the Controller, and Larry Rubin for his work in designing the cell library, enhancing the design automation tools and the design of the MAP. A Morphological Array Image Processor Controller Chip Set Christopher J. Insalaco x LIST OF ABBREVIATIONS ALU Arithmetic Logic Unit CAD Computer Aided Design CIF Caltech Intermediate Form CPF Circuit Path Finder DRC Design Rule Checker ERC Electrical Rule Checker HDL Hardware Description Language IBM International Business Machines Inc. LPE Layout Parameter Extractor LVS Layout Versus Schematic LSI Large Scale Integration MAP Morphological Array Processor MOSIS Metal Oxide Semiconductor Implementation System MSI Medium Scale Integration NSA National Security Agency RIT Rochester Institute of Technology SSI Small Scale Integration VLSI Very Large Scale Integration Morphological Image Processor Controller A Array
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