ENCM 501 Winter 2014 Tutorial for Week 4 Goals for Today (And A

ENCM 501 Tutorial 29Jan2014 slide 2/12 Goals for today (and a note) ENCM 501 Winter 2014 Tutorial for Week 4 Goals: I Explore tradeoffs in instruction encoding. Steve Norman, PhD, PEng I Review conventions for describing memory capacity, in preparation for lectures on memory hierarchies. Electrical & Computer Engineering Schulich School of Engineering University of Calgary Note: You are not expected to memorize all of the technical details that get used today—for example, you won’t be 29 January, 2014 expected to memorize exactly how a MIPS BEQ instruction is encoded and processed. ENCM 501 Tutorial 29Jan2014 slide 3/12 ENCM 501 Tutorial 29Jan2014 slide 4/12 32-bit constants and immediate mode instructions 64-bit constants and immediate mode instructions Suppose we are designing a new 32-bit ISA, and we have Suppose instead we’re designing a new 64-bit ISA, again with already decided that every instruction will be 32 bits in size. fixed-width 32-bit instructions. The C long and unsigned The C int and unsigned types will be 32 bits wide. long types will be 64 bits wide. Suppose that our ISA is going to use immediate mode Our new ISA is going to use immediate mode operands to operands to implement this sort of thing, where constant is implement assignment like this, in which constant is any one any one of all 232 possible constants: of all 264 possible constants: unsigned x; // x is in a GPR. unsigned long y; // y is in a GPR. // ... // ... x = constant ; y = constant ; In general, how many instructions will be needed for the In general, how many instructions will be needed for this kind assignment statement? of assignment statement? ENCM 501 Tutorial 29Jan2014 slide 5/12 ENCM 501 Tutorial 29Jan2014 slide 6/12 64-bit constants, continued More about 64-bit constants Suppose we are trying to design our ISA to be similar to In MIPS64, in the worst case, using immediate mode to get a MIPS, in which there are 32 GPRs, and instructions all have 64-bit constant into a GPR would take four instructions, each 6-bit opcodes. with a 16-bit piece of the constant, plus two extra instructions to shift or DADDU or OR bits into the correct places in the Consider the statement y = constant ; from the previous GPR. slide. This seems expensive . six or more instructions are needed Using immediate mode operands, is it possible to implement to perform a simple operation. any such statement using only three instructions? Think of two reasons why this is not really a serious problem. ENCM 501 Tutorial 29Jan2014 slide 7/12 ENCM 501 Tutorial 29Jan2014 slide 8/12 Describing Capacity: kilobytes, megabytes, Memory capacity definitions gigabytes, kilobits, megabits, gigabits (Slides 7–9 are based on slides that have been used in 10 ENCM 369 for a few years.) 1 KB = 1 kilobyte = 2 bytes = 1,024 bytes. 20 B means byte (8 bits). b means bit. 1 MB = 1 megabyte = 2 bytes = 1,048,576 bytes. 30 But often B and b get mixed up, so watch out for mistakes! 1 GB = 1 gigabyte = 2 bytes = 1,073,741,824 bytes. When describing memory size, powers of two are always So, how many one-bit memory cells does it take to make a used (e.g., 1 KB = 1024 bytes, 1 MB = 1,048,576 bytes). 256 MB memory circuit? When describing disk capacity or data transfer rate, powers of ten are more frequently used (e.g, 160 GB = 160,000,000,000 bytes). ENCM 501 Tutorial 29Jan2014 slide 9/12 ENCM 501 Tutorial 29Jan2014 slide 10/12 Does it bother you that 1 Mb might or might not MIPS J and JAL instructions be exactly 1,000,000 bits? Here is how the PC update works in MIPS32 (in MIPS64, bits 63–28 are copied from old to new PC): old PC It should! Engineers should try to avoid ambiguity and 31 28 27 2 10 imprecision in technical communication! 00 IEEE standard 1541—unfortunately not in wide use—proposes 3102625 new prefixes and symbols: kibi- (Ki), mebi- (Mi), gibi- (Gi), copy opcode J or JAL etc., for powers of two. copy instruction 20 Example: 1 Mib = 1 mebibit = 2 bits. These prefixes are 00 nice, but won’t be used in ENCM 501—we will stick with the 31 28 27 210 more commonly used prefixes and symbols. new PC If all jumps and procedure calls are done with J and JAL, how much memory, in MB, can program instructions occupy? ENCM 501 Tutorial 29Jan2014 slide 11/12 ENCM 501 Tutorial 29Jan2014 slide 12/12 ARM call instruction: BL (branch and link) MIPS branch instructions Here is an example BNE instruction: 000101_01000_00000_1111111111110110 This instruction will add 4 times the offset to the PC, and write a return address into register r14: Suppose the address of the branch instruction is 0x0040015c. 1110_1011_ 24-bit signed offset What is the branch target address? Let’s follow the steps a MIPS processor would take to find the target address. If all procedure calls are done with BL, how much memory, in MB, can program instructions occupy? Compilers for MIPS often generate loops that look like this . label: [first instruction in loop] For both MIPS and ARM, how is it possible to get around the . code size limits we have found on this slide and the previous . one? BNE gpr1, gpr2, label [delay slot instruction] What is the maximum number of instructions in such a loop?.

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