Section 1. Programmer's Model

M Programmer’s Model Section 1. Programmer’s Model

HIGHLIGHTS

This section of the manual contains overview information about the dsPIC30F. It contains the following major topics:

1.1 dsPIC30F Overview...... 1-2 1.2 Programmer’s Model...... 1-3 1.2.1 Working Register Array...... 1-3 1.2.2 Default Working Register Selection ...... 1-3 1.2.3 Software Stack Frame Pointer ...... 1-3 1.2.4 Software Stack Pointer...... 1-5 1.2.5 Accumulator A, Accumulator B ...... 1-6 1.2.6 Program Counter ...... 1-6 1.2.7 STATUS Register...... 1-7 1.2.8 Core Configuration Register ...... 1-9 1.2.9 Shadow Registers...... 1-11

Note: For detailed information about the dsPIC30F architecture and core, refer to the dsPIC30F Data Sheet.

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1.1 dsPIC30F Overview The dsPIC30F core is a 16-bit (data) modified Harvard architecture with an enhanced instruction set including significant support for DSP. The core has a 24-bit instruction word, with a vari- able length opcode field. The program counter (PC) is 24-bits wide and addresses up to 4M x 24 bits of user program memory space. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. The majority of instructions execute in a single cycle and overhead free program loop constructs are supported using the DO and REPEAT instructions, both of which are interruptible at any point. The dsPIC30F has sixteen 16-bit working registers. Each of the working registers can act as a data, address or offset register. The 16th working register (W15) operates as a software stack pointer for interrupts and calls. The dsPIC30F instruction set has two classes of instructions; the MCU class of instructions and the DSP class of instructions. These two instruction classes are seamlessly integrated into the architecture and execute from a single execution unit. The instruction set includes many addressing modes and was designed for optimum C-compiler efficiency. The data space can be addressed as 32 Kwords or 64 Kbytes and is split into two blocks referred to as X and Y data memory. Each memory block has its own independent Address Generation Unit (AGU). The MCU class of instructions operate solely through the X memory AGU, which accesses the entire memory map as one linear data space. The DSP class of instructions operates through the X and Y AGUs, which splits the data address space into two parts. The X and Y data space boundary is arbitrary and device-specific. The upper 32K bytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Data Space Program PAGe (DSPPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space. Furthermore, RAM may be connected to the program memory bus and used to extend the internal data RAM. Overhead free circular buffers (modulo addressing) are supported in both X and Y address spaces. The modulo addressing removes the software boundary checking overhead for DSP algorithms. Furthermore, the X AGU circular addressing can be used with any of the MCU class of instructions. The X AGU also supports bit reverse addressing to greatly simplify input or out- put data reordering for radix-2 FFT algorithms. The core supports inherent (no operand), relative, literal, memory direct, register direct, and register indirect addressing modes. Each instruction is associated with a predefined addressing mode group depending upon its functional requirements. As many as 6 addressing modes are supported for each instruction. For most instructions, the dsPIC30F is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, 3 operand instructions can be supported, allowing A+B=C operations to be executed in a single cycle. The DSP engine features a high speed 16-bit by 16-bit multiplier, a 40-bit ALU, two 40-bit satu- rating accumulators and a 40-bit bidirectional barrel shifter. The barrel shifter is capable of shifting a 40-bit value up to 15 bits right or up to 16-bits left in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal real-time per- formance. The MAC instruction and other associated instructions can concurrently fetch two data operands from memory while multiplying two W registers. This requires that the data space be split for these instructions and linear for all others. This is achieved in a transparent and flex- ible manner through dedicating certain working registers to each address space. The dsPIC30F has a vectored exception scheme with 15 individually prioritized vectors. The exceptions consist of reset, 7 traps and 8 interrupts.

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1.2 Programmer’s Model 1 The programmer’s model for the dsPIC30F is shown in Figure 1-1. Programmer All registers in the programmer’s model are memory mapped and can be manipulated directly by instructions. A description of each register is provided in Table 1-1. Model TABLE 1-1: PROGRAMMER’S MODEL REGISTER DESCRIPTIONS Register Description W0 through W15 Working register array ’

ACCA, ACCB 40-bit DSP accumulators s PC 24-bit program counter SPLIM Stack pointer limit value register TABPAG Table memory page address register DSPPAG Data space program memory page address register RCOUNT REPEAT loop count register DCOUNT DO loop count register CORCON Contains DSP engine control bits STATUS ALU and DSP engine status register

1.2.1 Working Register Array

The 16 working (W) registers can function as data, address or offset registers. The function of a W register is determined by the instruction that accesses it. Byte instructions which target the working register array only effect the least significant byte of the target register. Since the working registers are memory mapped, the least and most significant bytes can be manipulated through byte wide data memory space accesses.

1.2.2 Default Working Register Selection

The dsPIC30F instruction set can be divided into two instruction types: working register instructions and file register instructions. The working register instructions use the working register array as data values or as addresses that point to a memory location. In contrast, file register instructions operate on a specific memory address contained in the instruction opcode. File register instructions do not encode the W that is to be used for the instruction in the opcode. The default working register (WREG) for all file register instructions is defined by the WD field, CORCON<11:8>. This field is reset to 0x0, corresponding to register W0.

1.2.3 Software Stack Frame Pointer

W14 has been assigned for use as a stack frame pointer with the link (LNK) and unlink (ULNK) instructions. However, W14 can be used by any instruction in the same manner as all other W registers.

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FIGURE 1-1: PROGRAMMER’S MODEL

D15 D0 Legend W0 PUSH.S Shadow DSP Operand W1 Registers DO Shadow W2

W3 REPEAT Shadow W4 W5 DSP Address Registers W6 W7 Working Registers W8 W9 W10 W11 W12 W13 Frame Pointer/W14 Stack Pointer/W15* 0 * W15[0] & SPLIM[0] always = 0 W15 & SPLIM not shadowed

SPLIM* 0 Stack Pointer Limit Register

AD39AD31 AD15 AD0 DSP AccA Accumulators AccB

PC23 PC0 0 0 Program Counter

7 0 TABPAG Data Table Page Address

7 0 DSPPAG Data Space Prog Page Address

15 0 RCOUNT REPEAT Loop Counter

15 0 DCOUNT DO Loop Counter

21 0 DOSTART DO Loop Start Address

21 0 DOEND DO Loop End Address

15 0 CORCON Core Configuration Register

OA OB SA SB OAB SAB DA RA SZ NOVZDC C STATUS Register

SRL

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1.2.4 Software Stack Pointer 1

W15 serves as a dedicated software stack pointer, and will be automatically modified by excep- Programmer tion processing, subroutine calls and returns. However, W15 can be referenced by any instruction in the same manner as all other W registers. This simplifies reading, writing and manipulating the stack pointer (e.g. creating stack frames). Model

Note: In order to protect against misaligned stack accesses, W15[0] is always clear. ’ s

W15 is initialized to 0x0200 during a reset. This address ensures that the stack pointer will point to valid RAM in all dsPIC30F devices and permits stack availability for non-maskable trap exceptions or priority level 7 interrupts, which may occur before the SP is set by the user software. The user may reprogram the SP during initialization to any location within data space. The stack pointer always points to the first available free word and fills the software stack working from lower towards higher addresses. It pre-decrements for a stack pop (read) and post increments for a stack push (write) as shown in Figure 1-2. When the PC is pushed onto the stack, PC[15:0] is pushed onto the first available stack word, then PC[23:16]. For a PC push during any CALL instruction, the MS-byte of the PC is zero extended before the push as shown in Figure 1-2. During exception processing, the MS-byte of the PC is concatenated with the lower 8-bits of the STATUS register. This allows the STATUS register contents to be automatically preserved during interrupts.

Note: A PC push during exception processing will concatenate the SRL register to the MS-byte of the PC prior to the push.

FIGURE 1-2: STACK OPERATION FOR CALL INSTRUCTION

0x0000

15 0

PC[15:0] W15 (before CALL) 0x0 PC[23:16] W15 (after CALL) Higher Address Higher Stack Grows Towards Grows Stack

Note: For interrupts, the upper byte of the second pushed word contains the SRL.

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1.2.5 Accumulator A, Accumulator B

Accumulator A (AccA) and Accumulator B (AccB) are 40-bit wide registers utilized by DSP instructions to perform mathematical and shifting operations. Each accumulator is composed of 3 memory mapped registers: • ACCxU (bits 39 - 32) • ACCxH (bits 31 - 16) • ACCxL (bits 15 - 0) Refer to Section2.10 for details on using AccA and AccB.

1.2.6 Program Counter

The Program Counter (PC) increments by 2 with the LSb set to 0 to provide compatibility with data space addressing. Instructions are addressed in the 4M x 24-bit program memory space by PC[22:1]. PC[23] allows access to user configuration space and device ID locations. PC[23] is always cleared such that the PC does not increment into the configuration space through normal software operation. PC[0] is used as a byte select bit for program memory accesses from data space.

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1.2.7 STATUS Register 1

The 16-bit STATUS register, shown in Register 1-1, maintains status information about instruc- Programmer tions which have most recently been executed by the processor. The low byte of the STATUS register (SRL) contains the MCU ALU operation status flags (Carry, Digit Carry, Zero, Overflow, Negative and Sticky Zero (C, DC, Z, OV, N, SZ)) and the loop active flags (Repeat Active and Model Data Active (RA, DA)). The MCU ALU operation status flags are either affected or used by the majority of instructions in the instruction set. Most of the Math, Rotate/Shift and Bit instructions modify the SRL after execution, and the conditional Branch instructions use the state of individual SRL bits to determine ’ the flow of program execution. All conditional Branch instructions are listed in Section2.7. s The C, DC, Z, OV and N bits are used to flag the immediate status of the MCU ALU. They indicate when an operation has resulted in a carry, digit carry, zero, overflow and negative result, respec- tively. When a subtract operation is performed, the C flag is used as a Borrow flag. The SZ status bit is a special zero status bit that is useful for extended precision arithmetic. The SZ bit functions identically to the Z bit for all instructions except ADDC and SUBB and a few other instructions, which affect Z specifically. If the result of an ADDC or a SUBB instruction is non-zero, the SZ bit will be cleared and will remain cleared regardless of the result of subsequent ADDC or SUBB operations. The function of the SZ bit will be re-synchronized to the Z bit by any function other than ADDC or SUBB that affects it. This allows the SZ bit to be used for performing a simple zero check on the entire result of an extended precision addition or subtraction. The RA status bit indicates that a repeat instruction is being executed, and it is only affected by the REPEAT instructions. The RA bit is set to “1” when the instruction being repeated begins execution. The RA bit is set to “0” when the instruction being repeated completes execution for the last time. Likewise, the DO instructions affect the DA status bit, which indicates that a DO loop is active. The DA bit is set to “1” when the first instruction of the loop is executed. The DA bit is set to “0” when the last instruction of the DO loop completes its final execution. The high byte of the STATUS register (SRH) is used by the DSP class of instructions, and it is modified when data passes through one of the adders. The SRH provides status information about overflow and saturation for both accumulators. The Saturate A, Saturate B, Overflow A and Overflow B (SA, SB, OA, OB) flags provide individual accumulator status, while the Saturate AB and Overflow AB (SAB, OAB) flags provide combined accumulator status. The SAB and OAB flags provide the software developer efficiency in checking the register for saturation or overflow. The OA and OB bits are used to indicate when an operation has generated an overflow into the guard bits (bits 32 through 39) of the respective accumulator. This condition can only occur when the processor is in super saturation mode or if it has saturation disabled. It indicates that the operation has generated a number which can not be represented with the lower 32 bits of the accumulator. The SA and SB bits are used to indicate when an operation has generated an overflow out of the most significant bit of the respective accumulator, and saturated that accumulator. The SA and SB status bits are active regardless of the saturation mode (normal, super or none). Namely, once that the SA or SB is set to “1”, it can only be cleared manually by software. When required, it is recommended that the SA and SB bits be cleared with the BCLR instruction. For convenience, the OA and OB bits are logically ORed together to form the OAB status bit, and the SA and SB bits are logically ORed to form the SAB status bit. These cumulative status bits provide efficient overflow and saturation checking when an algorithm is implemented which uti- lizes both accumulators. Instead of interrogating the OA and the OB bits independently for arithmetic overflows, a single check of the OAB bit may be performed. Likewise, when checking for saturation, the SAB bit may be examined instead of checking both the SA and SB bits. Note that the SAB bit itself does not have to be cleared in software. SAB will be “0” if both SA and SB are “0”.

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Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U U OA OB SA SB OAB SAB - - bit 15 bit 8

Lower Byte: R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DA RA SZ N OV Z DC C bit 7 bit 0 bit 15 OA: Accumulator A Overflow Status 1 = Accumulator A overflowed 0 = Accumulator A not overflowed bit 14 OB: Accumulator B Overflow Status 1 = Accumulator B overflowed 0 = Accumulator B not overflowed bit 13 SA: Accumulator A Saturation ‘Sticky’ Status 1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not saturated bit 12 SB: Accumulator B Saturation ‘Sticky’ Status 1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not saturated bit 11 OAB: OA || OB Combined Accumulator Overflow Status 1 = Accumulators A or B have overflowed 0 = Neither Accumulators A or B have overflowed bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status 1 = Accumulators A or B are saturated or have been saturated at some time in the past 0 = Neither Accumulator A or B are saturated bit 9-8 Unused bit 7 DA: DO Loop Active 1 = DO loop in progress 0 = DO loop not in progress bit 6 RA: REPEAT Loop Active 1 = REPEAT loop in progress 0 = REPEAT loop not in progress bit 5 SZ: MCU ALU ‘sticky’ Zero bit 1 = An operation which effects the Z bit has set it at some time in the past 0 = The most recent operation which effects the Z bit has cleared it (i.e. a non-zero result) bit 4 N: MCU ALU Negative bit bit 3 OV: MCU ALU Overflow bit bit 2 Z: MCU ALU Zero bit bit 1 DC: MCU ALU Half Carry bit 0 C: MCU ALU Carry/Borrow bit

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown

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1.2.8 Core Configuration Register 1

The 16-bit Core Configuration Register (CORCON), shown in Register 1-2, is used to set the Programmer configuration of the dsPIC30F CPU. This register provides the ability to: • map program space into data space Model • set the default working register (WREG) • set the AccA and AccB saturation enable • set the data space write saturation mode • set the accumulator saturation and rounding modes ’ • set the multiplier mode for DSP operations s

On device reset, the CORCON is set to 0x0000, which sets the following mode: • program space NOT mapped to data space (PSV = 0) • WREG set to W0 (WD<3:0>=0) • AccA and AccB saturation disabled (SATA = 0, SATB = 0) • data space write saturation disabled (SATDW = 0) • accumulator saturation mode set to normal (ACCSAT = 0) • accumulator rounding mode set to unbiased (RND = 0) • DSP multiplier mode set to fractional (IF = 0)

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Upper Half: U U U R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 - - - PSV WD3 WD2 WD1 WD0 bit 15 bit 8

Lower Half: R/W-0 R/W-0 R/W-0 U R/W-0 U R/W-0 R/W-0 SATA SATB SATDW - ACCSAT - RND IF bit 7 bit 0 bit 15 Unused bit 14 Unused bit 13 Unused bit 12 PSV: Program Space Visibility in Data Space Enable 1 = Program Space Visible in Data Space 0 = Program Space Not Visible in Data Space bit 11-8 WD3:WD0: Default W for File Register Instructions 1111 = W15 0000 = W0 Note: Do not use W15 (stack pointer). Use W14 with caution (frame pointer). bit 7 SATA: AccA Saturation Enable 1 = Accumulator A saturation enabled 0 = Accumulator A saturation disabled bit 6 SATB: AccB Saturation Enable 1 = Accumulator B saturation enabled 0 = Accumulator B saturation disabled bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable 1 = Data Space write saturation enabled 0 = Data Space write saturation disabled bit 4 Unused bit 3 ACCSAT: Accumulator Saturation Mode Select 1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) bit 2 Unused bit 1 RND: Rounding Mode Select 1 = Biased (conventional) rounding enabled 0 = Unbiased (convergent) rounding enabled bit 0 IF: Integer or Fractional Multiplier Mode Select 1 = Integer mode enabled for DSP ops 0 = Fractional mode enabled for DSP ops

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown

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1.2.9 Shadow Registers 1

Most of the registers in the programmer’s model have a shadow register associated with them Programmer as shown in Table 1-2. A shadow register is used as temporary holding register and can transfer its contents to or from its host register upon some event. None of the shadow registers are acces- sible directly. Model

TABLE 1-2: AUTOMATIC SHADOW REGISTER USAGE Register/Bit Description PUSH.S / POP.S REPEAT DO

W0 through W14 Yes - - ’ s PC --- ALU Status (STATUS[5:0]) Yes - - RA bit (STATUS[6]) Yes Yes - DA bit (STATUS[7]) Yes - - RCOUNT -Yes- DOSTART --Yes DOEND --Yes DCOUNT --Yes

Note: All shadow registers are one register deep. Additional shadowing may be performed in software using the software stack.

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NOTES:

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