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Natalie Enright Jerger Natalie Enright Jerger Contact The Edward S. Rogers Department of Electrical Voice: (416) 978-5056 Information and Computer Engineering Fax: (416) 971-2326 10 King's College Rd E-mail: [email protected] University of Toronto Webpage: www.eecg.toronto.edu/~enright Toronto, ON M5S 3G4 Canada Education University of Wisconsin, Madison, Wisconsin USA Ph.D., Electrical Engineering, December 2008 • Dissertation: \Chip Multiprocessor Coherence and Interconnect System Design" • Advisors: Mikko H. Lipasti and Li-Shiuan Peh (Princeton) M.S., Electrical and Computer Engineering, May 2004 Purdue University, West Lafayette, Indiana USA B.S., Computer Engineering, May 2002 Appointment University of Toronto, Electrical and Computer Engineering, Toronto, Ontario, Canada Assistant Professor January 2009 - present Research Computer architecture, many-core architectures, on-chip networks, cache coherence protocols, inter- Interests connection networks, emerging applications for many-core architectures. Honors and IBM Ph.D. Fellowship, 2008 Awards IBM Ph.D. Fellowship, 2007 Peter R. Schneider Distinguished Graduate Fellowship, University of Wisconsin-Madison, 2002 University of Wisconsin Teaching Academy Future Faculty Partner, 2004-2008 Publications [B1] Natalie Enright Jerger and Li-Shiuan Peh. \On-Chip Networks", Synthesis Lecture in Book Computer Architecture. (Editor: Mark Hill). Morgan & Claypool Publishers. July 2009, 141 pages. (downloaded over 1100 times as of April 2011). Citations 41. Publications [J1] Radu Marculescu, Umit Ogras, Li-Shiuan Peh, Natalie Enright Jerger and Yatin Hoskote. Journal Outstanding Research Problems in NoC Design: Circuit-, Microarchitecture- and System-Level Perspective. In IEEE Transactions on Computer-Aided Design, Jan 2009. (Most downloaded article in Transactions on Computer-Aided Design of 2009.) Citations: 76. [J2] Natalie Enright Jerger, Mikko Lipasti and Li-Shiuan Peh. Circuit-Switched Coherence. IEEE Computer Architecture Letters, vol. 6, no 1, Mar. 2007. Citations: 7. [J3] Elizabeth M. OCallaghan and Natalie Enright Jerger. Women and Girls in Science and Engineering: Understanding the Barriers to Recruitment, Retention and Persistence across the Educational Trajectory. Journal of Women and Minorities in Science and Engineering. Dec. 2006. Citation: 1. 1Citations reported from Google Scholar 1 Publications [C1] Sheng Ma, Natalie Enright Jerger, and Zhiying Wang. DBAR: An Efficient Routing Al- Conference gorithm to Support Multiple Concurrent Applications in Networks-on-Chip. In Proceedings of the International Symposium on Computer Architecture. June 2011 (40 out of 208 accepted). [C2] Danyao Wang, Natalie Enright Jerger, and J. Gregory Steffan. DART: A Programmable Architecture for NoC Simulation on FPGAs. In Proceedings of the 5th IEEE Network on Chip Symposium. May 2011 (acceptance rate: 25%). [C3] Natalie Enright Jerger. SigNet: Network-on-Chip Filtering for Coarse Vector Directories. In Proceedings of Design Automation and Test in Europe (DATE). Munich, Germany. March 2010. [C4] Mitch Hayenga, Natalie Enright Jerger and Mikko Lipasti. SCARAB: A Single Cycle Adaptive Routing and Bufferless Network. In Proceedings of the 42nd International Symposium on Microarchitecture. New York, New York. December 2009 (52 out of 210 accepted). Citations: 11. [C5] Dennis Abts, Natalie Enright Jerger, John Kim, Mikko Lipasti and Dan Gibson. Achieving Predictable Performance through Better Memory Controller Placement in Many-Core CMPs. In Proceedings of the 36th International Symposium on Computer Architecture. Austin, Texas. June 2009 (43 out of 210 accepted). Citations: 22. [C6] Natalie Enright Jerger, Li-Shiuan Peh and Mikko H. Lipasti. Virtual Tree Coherence: Leveraging Regions and In-Network Multicast Trees for Scalable Cache Coherence. In Proceedings of the 41th International Symposium on Microarchitecture. Lake Como, Italy. November 2008. (40 out of 210 accepted). Citations: 29. [C7] Natalie Enright Jerger, Li-Shiuan Peh and Mikko H. Lipasti. Virtual Circuit Tree Multi- casting: A Case for On-Chip Hardware Multicast Support. In Proceedings of the 35th International Symposium on Computer Architecture. Beijing, China. June 2008. (37 out of 259 accepted). Citations: 51. [C8] Natalie Enright Jerger, Li-Shiuan Peh and Mikko H. Lipasti. Circuit-Switched Coherence. In Proceedings of the 2nd Annual IEEE Network on Chip Symposium. Newcastle-Upon-Tyne, UK. April 2008. (19 out of 60 accepted). Citations: 33. [C9] Natalie Enright Jerger, Dana Vantrease and Mikko Lipasti. An Evaluation of Server Con- solidation Workloads for Multi-Core Designs. In Proceedings of IEEE International Symposium on Workload Characterization. Sept. 2007. (21 out of 53 accepted). Citations: 21. [C10] Natalie Enright Jerger, Eric Hill, and Mikko Lipasti. Friendly Fire: Understanding the Effects of Multiprocessor Prefetches. Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software. March 2006. (24 out of 81 accepted). Citations: 8. Publications [W1] Danyao Wang, Natalie Enright Jerger, and J. Gregory Steffan. DART: Fast and Flexible Workshop NoC Simulation using FPGAs. In the 5th Annual Workshop on Architectural Research Prototyping (WARP), held in conjunction with ISCA-37. June 2010. Citations: 2. Publications Matthew Misler and Natalie Enright Jerger. Moths: Mobile Threads for On-Chip Networks. In Poster Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (Poster Session). September 2010. Publications Natalie D. Enright, Jamison Collins, Perry Wang, Hong Wang, Xinmin Tran, John Shen, Gad Patent Sheaffer, Per Hammarlund. Mechanism to exploit synchronization overhead to improve multithread performance. Patent no: 7487502. Sept 2009. 2 Funding and Fujitsu Corporation, co-PI, PI: Ali Sheikholeslami, \Next Generation FPGA Platforms,", $130,000. Support Natural Sciences and Engineering Research Council, Engage Program, PI, Co-PI: Jason Ander- son, \Applications Exploiting Heterogeneous Processor Architectures for Improved Throughput and Energy-Efficiency," 2011, $24,940. Intel Corporation, PI, \Early-Stage Coherence Modeling for On-Chip Network Performance and Power Analysis", 2011, $57,000. AMD Corporation, PI, Co-PI: Jason Anderson: \Heterogeneous Multi-Core Architectures," 2010, $20,000 and In-kind contribution: 2 ATI Graphics Cards. Intel Corporation, Many-core Application Research Community (MARC), PI, Co-PI: Greg Steffan, \Exploiting efficient communication in the SCC," 2010, In-kind contribution: access to the Intel Single-Chip Cloud Computer (consists of 48 IA-32 cores on a single die, with 4 memory controllers, and a 4×6 mesh on-chip network). Natural Sciences and Engineering Research Council, Engage Program, PI, \Hybrid NoC/Crossbar Designs for SoC Fabrics," 2010, $23,580. Natural Sciences and Engineering Research Council, Strategic Project Grant, co-PI, PI: Joyce Poon, Other Co-PIs: Andreas Moshovos and Al Leon-Garcia, \Integrated Photonics for Energy-Efficient Multi-Core Processors," 2010-2013, $533,100. Natural Sciences and Engineering Research Council, Discovery Grant, PI, \Semantically Rich Net- works for Many-Core Architectures," 2009-2014, $125,000. Connaught Fund, University of Toronto, PI, \Communication-centric Many-Core Computing Archi- tectures," 2009, $10,000. Professional Guest Co-Editor (with Mikko Lipasti, University of Wisconsin-Madison) Service IEEE MICRO Special Issue on Systems for Very Large Scale Computing, May/June 2011 CRA-W/CDC Distinguished Lecture Series Organizer for University of Toronto, 2010 Speakers: Margaret Martonosi (Princeton) and Jaime Moreno (IBM) Co-Chair 9th Annual Workshop on Duplicating, Deconstructing and Debunking (held in conjunction with ISCA-38) 8th Annual Workshop on Duplicating, Deconstructing and Debunking (held in conjunction with ISCA-36) Publicity Chair CGO 2010: International Symposium on Code Generation and Optimization External Reviewer NSERC Discovery Grants, Electrical and Computer Engineering Committee Program Committee (Conferences) International Symposium on High Performance Computer Architecture (HPCA) 2012 International Conference on Computer Design (ICCD) 2011 International Symposium on Microarchitecture (MICRO) 2011 International Conference on Supercomputing (ICS) 2011 3 International Symposium on Performance Analysis of Systems and Software (ISPASS) 2011 International Parallel and Distributed Processing Symposium (IPDPS) 2011 Canadian Conference on Electrical and Computer Engineering 2011 International Conference on Computer Design (ICCD), 2010 International Conference on Computer Aided Design (ICCAD), 2010 International Conference on Parallel Architectures and Compilation Techniques (PACT) 2010 International Conference on Parallel Processing (ICPP) 2010 International Conference on Design Automation and Test in Europe (DATE), 2010 International Conference on Computer Design (ICCD), 2009 International Conference on Computer Aided Design (ICCAD), 2009 Program Committee (Workshops) Workshop on Communication Architecture for Scalable Systems (CASS) (held in conjunction with IPDPS), 2011 5th Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip (held in conjunc- tion with HiPEAC), 2011 3rd Workshop on Network on Chip Architectures (held in conjunction with MICRO 43), 2010 4th Workshop on Chip Multiprocessor Memory Systems and Interconnects (held in conjunction with HPCA), 2010 2nd Workshop on Network on Chip Architectures (held in conjunction with MICRO 42), 2009 3rd Workshop on Chip
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