Natalie Enright Jerger

Contact The Edward S. Rogers Department of Electrical Voice: (416) 978-5056 Information and Computer Engineering Fax: (416) 971-2326 10 King’s College Rd E-mail: [email protected] University of Toronto Webpage: www.eecg.toronto.edu/~enright Toronto, ON M5S 3G4 Canada

Education University of Wisconsin, Madison, Wisconsin USA Ph.D., Electrical Engineering, December 2008 • Dissertation: “Chip Multiprocessor Coherence and Interconnect System Design” • Advisors: Mikko H. Lipasti and Li-Shiuan Peh (Princeton) M.S., Electrical and Computer Engineering, May 2004

Purdue University, West Lafayette, Indiana USA B.S., Computer Engineering, May 2002

Appointment University of Toronto, Electrical and Computer Engineering, Toronto, Ontario, Canada Assistant Professor January 2009 - present

Research Computer architecture, many-core architectures, on-chip networks, cache coherence protocols, inter- Interests connection networks, emerging applications for many-core architectures.

Honors and IBM Ph.D. Fellowship, 2008 Awards IBM Ph.D. Fellowship, 2007 Peter R. Schneider Distinguished Graduate Fellowship, University of Wisconsin-Madison, 2002 University of Wisconsin Teaching Academy Future Faculty Partner, 2004-2008

Publications [B1] Natalie Enright Jerger and Li-Shiuan Peh. “On-Chip Networks”, Synthesis Lecture in Book Computer Architecture. (Editor: Mark Hill). Morgan & Claypool Publishers. July 2009, 141 pages. (downloaded over 1100 times as of April 2011). Citations 41.

Publications [J1] Radu Marculescu, Umit Ogras, Li-Shiuan Peh, Natalie Enright Jerger and Yatin Hoskote. Journal Outstanding Research Problems in NoC Design: Circuit-, Microarchitecture- and System-Level Perspective. In IEEE Transactions on Computer-Aided Design, Jan 2009. (Most downloaded article in Transactions on Computer-Aided Design of 2009.) Citations: 76.

[J2] Natalie Enright Jerger, Mikko Lipasti and Li-Shiuan Peh. Circuit-Switched Coherence. IEEE Computer Architecture Letters, vol. 6, no 1, Mar. 2007. Citations: 7.

[J3] Elizabeth M. OCallaghan and Natalie Enright Jerger. Women and Girls in Science and Engineering: Understanding the Barriers to Recruitment, Retention and Persistence across the Educational Trajectory. Journal of Women and Minorities in Science and Engineering. Dec. 2006. Citation: 1. 1Citations reported from Google Scholar

1 Publications [C1] Sheng Ma, Natalie Enright Jerger, and Zhiying Wang. DBAR: An Eﬃcient Routing Al- Conference gorithm to Support Multiple Concurrent Applications in Networks-on-Chip. In Proceedings of the International Symposium on Computer Architecture. June 2011 (40 out of 208 accepted).

[C2] Danyao Wang, Natalie Enright Jerger, and J. Gregory Steﬀan. DART: A Programmable Architecture for NoC Simulation on FPGAs. In Proceedings of the 5th IEEE Network on Chip Symposium. May 2011 (acceptance rate: 25%).

[C3] Natalie Enright Jerger. SigNet: Network-on-Chip Filtering for Coarse Vector Directories. In Proceedings of Design Automation and Test in Europe (DATE). Munich, Germany. March 2010.

[C4] Mitch Hayenga, Natalie Enright Jerger and Mikko Lipasti. SCARAB: A Single Cycle Adaptive Routing and Buﬀerless Network. In Proceedings of the 42nd International Symposium on Microarchitecture. New York, New York. December 2009 (52 out of 210 accepted). Citations: 11.

[C5] Dennis Abts, Natalie Enright Jerger, John Kim, Mikko Lipasti and Dan Gibson. Achieving Predictable Performance through Better Memory Controller Placement in Many-Core CMPs. In Proceedings of the 36th International Symposium on Computer Architecture. Austin, Texas. June 2009 (43 out of 210 accepted). Citations: 22.

[C6] Natalie Enright Jerger, Li-Shiuan Peh and Mikko H. Lipasti. Virtual Tree Coherence: Leveraging Regions and In-Network Multicast Trees for Scalable Cache Coherence. In Proceedings of the 41th International Symposium on Microarchitecture. Lake Como, Italy. November 2008. (40 out of 210 accepted). Citations: 29.

[C7] Natalie Enright Jerger, Li-Shiuan Peh and Mikko H. Lipasti. Virtual Circuit Tree Multi- casting: A Case for On-Chip Hardware Multicast Support. In Proceedings of the 35th International Symposium on Computer Architecture. Beijing, China. June 2008. (37 out of 259 accepted). Citations: 51.

[C8] Natalie Enright Jerger, Li-Shiuan Peh and Mikko H. Lipasti. Circuit-Switched Coherence. In Proceedings of the 2nd Annual IEEE Network on Chip Symposium. Newcastle-Upon-Tyne, UK. April 2008. (19 out of 60 accepted). Citations: 33.

[C9] Natalie Enright Jerger, Dana Vantrease and Mikko Lipasti. An Evaluation of Server Con- solidation Workloads for Multi-Core Designs. In Proceedings of IEEE International Symposium on Workload Characterization. Sept. 2007. (21 out of 53 accepted). Citations: 21.

[C10] Natalie Enright Jerger, Eric Hill, and Mikko Lipasti. Friendly Fire: Understanding the Eﬀects of Multiprocessor Prefetches. Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software. March 2006. (24 out of 81 accepted). Citations: 8.

Publications [W1] Danyao Wang, Natalie Enright Jerger, and J. Gregory Steﬀan. DART: Fast and Flexible Workshop NoC Simulation using FPGAs. In the 5th Annual Workshop on Architectural Research Prototyping (WARP), held in conjunction with ISCA-37. June 2010. Citations: 2.

Publications Matthew Misler and Natalie Enright Jerger. Moths: Mobile Threads for On-Chip Networks. In Poster Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (Poster Session). September 2010.

Publications Natalie D. Enright, Jamison Collins, Perry Wang, Hong Wang, Xinmin Tran, John Shen, Gad Patent Sheaﬀer, Per Hammarlund. Mechanism to exploit synchronization overhead to improve multithread performance. Patent no: 7487502. Sept 2009.

2 Funding and Fujitsu Corporation, co-PI, PI: Ali Sheikholeslami, “Next Generation FPGA Platforms,”, $130,000. Support Natural Sciences and Engineering Research Council, Engage Program, PI, Co-PI: Jason Ander- son, “Applications Exploiting Heterogeneous Processor Architectures for Improved Throughput and Energy-Eﬃciency,” 2011, $24,940.

Intel Corporation, PI, “Early-Stage Coherence Modeling for On-Chip Network Performance and Power Analysis”, 2011, $57,000.

AMD Corporation, PI, Co-PI: Jason Anderson: “Heterogeneous Multi-Core Architectures,” 2010, $20,000 and In-kind contribution: 2 ATI Graphics Cards.

Intel Corporation, Many-core Application Research Community (MARC), PI, Co-PI: Greg Steﬀan, “Exploiting eﬃcient communication in the SCC,” 2010, In-kind contribution: access to the Intel Single-Chip Cloud Computer (consists of 48 IA-32 cores on a single die, with 4 memory controllers, and a 4×6 mesh on-chip network).

Natural Sciences and Engineering Research Council, Engage Program, PI, “Hybrid NoC/Crossbar Designs for SoC Fabrics,” 2010, $23,580.

Natural Sciences and Engineering Research Council, Strategic Project Grant, co-PI, PI: Joyce Poon, Other Co-PIs: Andreas Moshovos and Al Leon-Garcia, “Integrated Photonics for Energy-Eﬃcient Multi-Core Processors,” 2010-2013, $533,100.

Natural Sciences and Engineering Research Council, Discovery Grant, PI, “Semantically Rich Net- works for Many-Core Architectures,” 2009-2014, $125,000.

Connaught Fund, University of Toronto, PI, “Communication-centric Many-Core Computing Archi- tectures,” 2009, $10,000.

Professional Guest Co-Editor (with Mikko Lipasti, University of Wisconsin-Madison) Service IEEE MICRO Special Issue on Systems for Very Large Scale Computing, May/June 2011

CRA-W/CDC Distinguished Lecture Series Organizer for University of Toronto, 2010 Speakers: Margaret Martonosi (Princeton) and Jaime Moreno (IBM)

Co-Chair 9th Annual Workshop on Duplicating, Deconstructing and Debunking (held in conjunction with ISCA-38) 8th Annual Workshop on Duplicating, Deconstructing and Debunking (held in conjunction with ISCA-36)

Publicity Chair CGO 2010: International Symposium on Code Generation and Optimization

External Reviewer NSERC Discovery Grants, Electrical and Computer Engineering Committee

Program Committee (Conferences) International Symposium on High Performance Computer Architecture (HPCA) 2012 International Conference on Computer Design (ICCD) 2011 International Symposium on Microarchitecture (MICRO) 2011 International Conference on Supercomputing (ICS) 2011

3 International Symposium on Performance Analysis of Systems and Software (ISPASS) 2011 International Parallel and Distributed Processing Symposium (IPDPS) 2011 Canadian Conference on Electrical and Computer Engineering 2011 International Conference on Computer Design (ICCD), 2010 International Conference on Computer Aided Design (ICCAD), 2010 International Conference on Parallel Architectures and Compilation Techniques (PACT) 2010 International Conference on Parallel Processing (ICPP) 2010 International Conference on Design Automation and Test in Europe (DATE), 2010 International Conference on Computer Design (ICCD), 2009 International Conference on Computer Aided Design (ICCAD), 2009

Program Committee (Workshops) Workshop on Communication Architecture for Scalable Systems (CASS) (held in conjunction with IPDPS), 2011 5th Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip (held in conjunction with HiPEAC), 2011 3rd Workshop on Network on Chip Architectures (held in conjunction with MICRO 43), 2010 4th Workshop on Chip Multiprocessor Memory Systems and Interconnects (held in conjunction with HPCA), 2010 2nd Workshop on Network on Chip Architectures (held in conjunction with MICRO 42), 2009 3rd Workshop on Chip Multiprocessor Memory Systems and Interconnects (held in conjunction with ISCA), 2009

External Review Committee International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2010

Reviewer for Conference and Journals IEEE Micro: 2011 International Symposium on Microarchitecture: 2007, 2009, 2010 International Symposium on Computer Architecture: 2008, 2010 International Conference on Architectural Support for Programming Languages and Operating Systems: 2008 International Conference on Supercomputing: 2009 International Symposium on Parallel Algorithms and Architectures: 2009 International Conference on Parallel Processing: 2009 IEEE Computer Architecture Letters: 2008, 2009, 2010, 2011 IEEE Transactions on VLSI: 2008, 2009, 2011 ACM Transactions on Computers: 2009 International Conference on Computer Design: 2006 International Conference on Computer Aided Design: 2008 International Symposium on High Performance Computer Architecture: 2009, 2010, 2011 International Symposium on Performance Analysis of Systems and Software: 2008 International Symposium on Circuits and Systems: 2010 ACM Transactions on Embedded Computing Systems: 2009, 2011 ACM Transactions on Architecture and Code Optimization: 2011 Grace Hopper Celebration Scholarship Reviewer: 2011

4 Invited Talks Towards Application-Aware Network-on-Chip Architectures • Waterloo University, ECE Department, March 2011 On-Chip Network Research: Opportunities to Leverage Platform 2012 • Research Workshop on STMicroelectronics Platform 2012 (organized by CMC Microsys- tems), November 2010 Outstanding Research Challenges in On-Chip Networks • Altera Corporation, Toronto ON, June 2009. Virtual Tree Coherence: Leveraging Regions and In-Network Multicast Trees for Scalable Cache Coherence • International Symposium on Microarchitecture, November 2008. • 12th Annual Wisconsin Architecture Industrial Affiliates Meeting, October 2008. • Gigascale Systems Research Center Quarterly Concurrent Theme Meeting, June 2008. Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support • International Symposium on Computer Architecture, June 2008 Harnessing Computing Power through Communication • Computer Engineering Group, University of Toronto, March 2008 • Computer Science and Engineering Colloquium, Washington University in St. Louis, April 2008 Virtual Proximity: Interconnect Support for Flexible Scheduling of Server Consolidation Work- loads in CMPs • IBM Research Triangle Park, October 2007 • 11th Annual Wisconsin Architecture Industrial Affiliates Meeting, October 2007 An Evaluation of Server Consolidation Workloads for Multi-Core Designs • IEEE International Symposium on Workload Characterization, Boston MA, September 2007 Circuit-Switched Coherence • 2nd Annual IEEE Network on Chip Symposium, April 2008 • 10th Annual Wisconsin Architecture Industrial Affiliates Meeting, October 2006 • IBM Austin Research Lab, October 2006 Friendly Fire: Understanding the Effects of Multiprocessor Prefetches • 8th Annual Wisconsin Architecture Industrial Affiliates Meeting, October 2004 • IEEE Symposium on Performance Analysis of Systems and Software, March 2006

Professional Memberships IEEE, IEEE Computer Society ACM, SIGARCH

University Vice-Chair Service Community Aﬀairs and Gender Issues Committee, Faculty of Applied Science and Engineering, 2010-2011

Panelist: “Campus visit, interview and more” Positioning Yourself for a Career in Academia. Hosted by the Status of Women Oﬃce at the University of Toronto, April 2010.

High School Outreach Bishop Strachan School: Presentation on ECE to Grade 11 Physics class, January 2011.

Teaching Fall 2011: ECE 552 Computer Architecture ECE 1749H Interconnection Networks for Parallel Computer Architectures

5 Spring 2011: ECE 243 Computer Organization ECE 1749H Interconnection Networks for Parallel Computer Architectures

Fall 2010: ECE 452/ECE 1718H F1 Computer Architecture

Spring 2010: ECE 1749H Interconnection Networks for Parallel Computer Architectures (new course)

Fall 2009: ECE 452 Computer Architecture

Graduated M.A.Sc. Students Matthew Misler, Jan 2009-June 2010 • Thesis: An Exploration of On-Chip Network Based Thread Migration • First Employment: IT Analyst, TD Bank Financial Group Danyao Wang, Jan 2009-September 2010 (Co-supervisor: Prof. J. G. Steﬀan) • Thesis: DART: An FPGA-based Accelerator Platform for Network-On-Chip Simulation • First Employment: Software Engineer, Google

Current Ph.D. Students Robert Hesse, August 2009-Present

Current M.A.Sc. Students Kai Feng, September 2010-Present Steven Gurﬁnkel 2011-Present Sam Vafaee, August 2009-Present

Visiting International Ph.D. Students Parisa Khadem Hamedani, January 2011-Present (PhD student at Sharif University) Sheng Ma, September 2010-Present (PhD student at National University of Defense Technology)

Undergraduate Students Daniel Lee, 2011 Jeﬀ Nicholls (received NSERC Undergraduate Summer Research Award), 2011 Jyoti Tripathi, 2011 Camille Wingson, 2011 Tian Fang Yu, 2011 Victor Feng (received NSERC Undergraduate Summer Research Award), 2010 Ruolong Lian (received NSERC Undergraduate Summer Research Award), 2010 Thierry Moreau (received NSERC Undergraduate Summer Research Award), 2009

M.A.Sc. Defense Committee Member Adrian Popescu, August 2009 (Supervisor: Prof. C. Amza) Eric Tran, January 2010 (Supervisor: Prof. S. Mann) Nazmul Islam, August 2010 (Supervisor: R. Adve) Arghavan Arjmand, September 2010 (Supervisor: A. Helmy) Benedict Lau, September 2010 (Supervisor: A. Helmy) Vincent Mirian, September 2010 (Supervisor: P. Chow) Amirhassan Asgari, December 2010 (Supervisor: Z. Tate) Elias Ferzli, January 2011 (Supervisor: A. Moshovos) Mark Aldham, April 2011 (Supervisors: J. Anderson and S. Brown)

6 Nick Ni, May 2011 (Supervisor: J. Zhu)

Ph.D. Defense Committee Member Peter Yiannacouras, August 2009 (Supervisors: Profs. J. Rose and G. Steﬀan) Utku Aydonat, May 2011 (Supervisor: T. Abdelrahman)

Ph.D. Qualifying Exam Committee Member (6 students)

4th year design project supervisor (ECE496) 2010-2011: 11 students, 4 projects • 2 projects recognized as ECE496 Outstanding Projects 2009-2010: 6 students, 2 projects • 1 project ranked in top 4: recognized as an ECE496 Outstanding Project