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System Design for a Computational-RAM Logic-In-Memory Parailel-Processing Machine
System Design for a Computational-RAM Logic-In-Memory ParaIlel-Processing Machine Peter M. Nyasulu, B .Sc., M.Eng. A thesis submitted to the Faculty of Graduate Studies and Research in partial fulfillment of the requirements for the degree of Doctor of Philosophy Ottaw a-Carleton Ins titute for Eleceical and Computer Engineering, Department of Electronics, Faculty of Engineering, Carleton University, Ottawa, Ontario, Canada May, 1999 O Peter M. Nyasulu, 1999 National Library Biôiiothkque nationale du Canada Acquisitions and Acquisitions et Bibliographie Services services bibliographiques 39S Weiiington Street 395. nie WeUingtm OnawaON KlAW Ottawa ON K1A ON4 Canada Canada The author has granted a non- L'auteur a accordé une licence non exclusive licence allowing the exclusive permettant à la National Library of Canada to Bibliothèque nationale du Canada de reproduce, ban, distribute or seU reproduire, prêter, distribuer ou copies of this thesis in microform, vendre des copies de cette thèse sous paper or electronic formats. la forme de microficbe/nlm, de reproduction sur papier ou sur format électronique. The author retains ownership of the L'auteur conserve la propriété du copyright in this thesis. Neither the droit d'auteur qui protège cette thèse. thesis nor substantial extracts fkom it Ni la thèse ni des extraits substantiels may be printed or otherwise de celle-ci ne doivent être imprimés reproduced without the author's ou autrement reproduits sans son permission. autorisation. Abstract Integrating several 1-bit processing elements at the sense amplifiers of a standard RAM improves the performance of massively-paralle1 applications because of the inherent parallelism and high data bandwidth inside the memory chip. -
Dop – a Cpu Core for Teaching Basics of Computer Architecture
DOP – A CPU CORE FOR TEACHING BASICS OF COMPUTER ARCHITECTURE Milos Becvar, Alois Pluhacek and Jiri Danecek Department of Computer Science and Engineering Faculty of Electrical Engineering Czech Technical University in Prague, Abstract: A simple 16-bit processor core called DOP and its teaching environment is presented. The DOP processor illustrates the basic principles of computer organization and is therefore used in the introductory hardware course. Its major features are simplicity, availability of an FPGA implementation and a C compiler. This paper presents the description of the core, HW and SW tools and teaching methodology. computing performance. The DOP processor core was 1. INTRODUCTION developed at our department together with various SW and HW visualization tools (Danecek et al., 1994a). An introductory computer hardware course should teach students to the fundamental principles of computer The goal of this paper is to describe this processor core internal functionality. Students, who are familiar with and its learning environment for teaching basics of programming in high-level languages, are required to computer organization. The paper is organized as understand the interaction between a processor, a follows - section 2 outlines the introductory course and memory and I/O devices, an internal organization of characterizes the students, section 3 describes the DOP processor, computer arithmetic and basics of digital processor core, section 4 describes the SW and HW design. Our experience has shown that it is not an easy tools supporting this processor and finally section 5 task for most of them. The functionality of the processor outlines the use of the DOP in our introductory course. -
10. Assembly Language, Models of Computation
10. Assembly Language, Models of Computation 6.004x Computation Structures Part 2 – Computer Architecture Copyright © 2015 MIT EECS 6.004 Computation Structures L10: Assembly Language, Models of Computation, Slide #1 Beta ISA Summary • Storage: – Processor: 32 registers (r31 hardwired to 0) and PC – Main memory: Up to 4 GB, 32-bit words, 32-bit byte addresses, 4-byte-aligned accesses OPCODE rc ra rb unused • Instruction formats: OPCODE rc ra 16-bit signed constant 32 bits • Instruction classes: – ALU: Two input registers, or register and constant – Loads and stores: access memory – Branches, Jumps: change program counter 6.004 Computation Structures L10: Assembly Language, Models of Computation, Slide #2 Programming Languages 32-bit (4-byte) ADD instruction: 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 opcode rc ra rb (unused) Means, to the BETA, Reg[4] ß Reg[2] + Reg[3] We’d rather write in assembly language: Today ADD(R2, R3, R4) or better yet a high-level language: Coming up a = b + c; 6.004 Computation Structures L10: Assembly Language, Models of Computation, Slide #3 Assembly Language Symbolic 01101101 11000110 Array of bytes representation Assembler 00101111 to be loaded of stream of bytes 10110001 into memory ..... Source Binary text file machine language • Abstracts bit-level representation of instructions and addresses • We’ll learn UASM (“microassembler”), built into BSim • Main elements: – Values – Symbols – Labels (symbols for addresses) – Macros 6.004 Computation Structures L10: Assembly Language, Models -
Programmable Digital Microcircuits - a Survey with Examples of Use
- 237 - PROGRAMMABLE DIGITAL MICROCIRCUITS - A SURVEY WITH EXAMPLES OF USE C. Verkerk CERN, Geneva, Switzerland 1. Introduction For most readers the title of these lecture notes will evoke microprocessors. The fixed instruction set microprocessors are however not the only programmable digital mi• crocircuits and, although a number of pages will be dedicated to them, the aim of these notes is also to draw attention to other useful microcircuits. A complete survey of programmable circuits would fill several books and a selection had therefore to be made. The choice has rather been to treat a variety of devices than to give an in- depth treatment of a particular circuit. The selected devices have all found useful ap• plications in high-energy physics, or hold promise for future use. The microprocessor is very young : just over eleven years. An advertisement, an• nouncing a new era of integrated electronics, and which appeared in the November 15, 1971 issue of Electronics News, is generally considered its birth-certificate. The adver• tisement was for the Intel 4004 and its three support chips. The history leading to this announcement merits to be recalled. Intel, then a very young company, was working on the design of a chip-set for a high-performance calculator, for and in collaboration with a Japanese firm, Busicom. One of the Intel engineers found the Busicom design of 9 different chips too complicated and tried to find a more general and programmable solu• tion. His design, the 4004 microprocessor, was finally adapted by Busicom, and after further négociation, Intel acquired marketing rights for its new invention. -
The Hpc C Compiler 2.1 Introduction
™ MICROCONTROLLER DEVELOPMENT SUPPORT ( MOLE HPC™ C COMPILER USER'S MANUAL ( ( ( ( ~ National Semiconductor Corporation Customer Order Number 424410883-001 NSC Publication Number 424410883-001C October 1988 HPC™ C Compiler User's Manual @l 1988 National Semiconductor Corporation 2900 Semiconductor Drive P.O. Box 58090 Santa Clara. California 95052-8090 CONTENTS Chapter 1 OVERVIEW 1.1 INTRODUCTION............................. 1-1 1.2 MANUAL ORGANIZATION. .. 1-2 1.3 DOCUMENTATION CONVENTIONS. .. 1-2 1.3.1 General Conventions . .. 1-2 1.3.2 Conventions in Syntax Descriptions ............. 1-2 1.3.3 Example Conventions. .. 1-3 1.3.4 Additional Conventions .................... 1-3 Chapter 2 THE HPC C COMPILER 2.1 INTRODUCTION............................. 2-1 2.2 COMPILER COMMAND SYNTAX 2-1 Chapter 3 BASIC DEFINITIONS 3.1 INTRODUCTION............................. 3-1 3.2 NAMES.................................. 3-1 3.3 CONSTANTS............................... 3-1 3.4 ESCAPE SEQUENCES . .. 3-2 3.5 COMMENTS............................... 3-3 3.6 DATA TYPES. .. 3-3 3.7 PREPROCESSOR DIRECTIVES . .. 3-4 3.8 PROGRAM ORGANIZATION. .. 3-4 3.9 INITIALIZATION OF VARIABLES . .. 3-4 3.10 OPERATORS . .. 3-5 3.11 IN-LINE MICROASSEMBLER CODE . .. 3-5 Chapter 4 IMPLEMENTATION-DEPENDENT CONSIDERATIONS 4.1 INTRODUCTION............................. 4-1 4.2 MEMORy................................. 4-1 4.3 STORAGE CLASSES . .. 4-1 4.3.1 Storage Class Modifiers. .. 4-1 4.4 C STACK FORMAT . .. 4-3 4.5 USING IN-LINE MICROASSEMBLER CODE. .. 4-4 4.6 EFFICIENCY CONSIDERATIONS . .. 4-6 4.6.1 Declaration Syntax . .. 4-9 4.7 STATEMENTS AND IMPLEMENTATION .............. 4-10 4.8 RUN-TIME NOTES ........................... 4-11 v Appendix A CCHPC SPECIFICATIONS Appendix B CONVERTING BETWEEN STANDARD C AND CCHPC Appendix C INVOCATION LINE SYNTAX C.l INTRODUCTION............................ -
THE INVARIANCE THESIS 1. Introduction in 1936, Turing [47
THE INVARIANCE THESIS NACHUM DERSHOWITZ AND EVGENIA FALKOVICH-DERZHAVETZ School of Computer Science, Tel Aviv University, Ramat Aviv, Israel e-mail address:[email protected] School of Computer Science, Tel Aviv University, Ramat Aviv, Israel e-mail address:[email protected] Abstract. We demonstrate that the programs of any classical (sequential, non-interactive) computation model or programming language that satisfies natural postulates of effective- ness (which specialize Gurevich’s Sequential Postulates)—regardless of the data structures it employs—can be simulated by a random access machine (RAM) with only constant factor overhead. In essence, the postulates of algorithmicity and effectiveness assert the following: states can be represented as logical structures; transitions depend on a fixed finite set of terms (those referred to in the algorithm); all atomic operations can be pro- grammed from constructors; and transitions commute with isomorphisms. Complexity for any domain is measured in terms of constructor operations. It follows that any algorithmic lower bounds found for the RAM model also hold (up to a constant factor determined by the algorithm in question) for any and all effective classical models of computation, what- ever their control structures and data structures. This substantiates the Invariance Thesis of van Emde Boas, namely that every effective classical algorithm can be polynomially simulated by a RAM. Specifically, we show that the overhead is only a linear factor in either time or space (and a constant factor in the other dimension). The enormous number of animals in the world depends of their varied structure & complexity: — hence as the forms became complicated, they opened fresh means of adding to their complexity. -
WCAE 2003 Workshop on Computer Architecture Education
WCAE 2003 Proceedings of the Workshop on Computer Architecture Education in conjunction with The 30th International Symposium on Computer Architecture DQG 2003 Federated Computing Research Conference Town and Country Resort and Convention Center b San Diego, California June 8, 2003 Workshop on Computer Architecture Education Sunday, June 8, 2003 Session 1. Welcome and Keynote 8:45–10:00 8:45 Welcome Edward F. Gehringer, workshop organizer 8:50 Keynote address, “Teaching and teaching computer Architecture: Two very different topics (Some opinions about each),” Yale Patt, teacher, University of Texas at Austin 1 Break 10:00–10:30 Session 2. Teaching with New Architectures 10:30–11:20 10:30 “Intel Itanium floating-point architecture,” Marius Cornea, John Harrison, and Ping Tak Peter Tang, Intel Corp. ................................................................................................................................. 5 10:50 “DOP — A CPU core for teaching basics of computer architecture,” Miloš BeþváĜ, Alois Pluháþek and JiĜí DanƟþek, Czech Technical University in Prague ................................................................. 14 11:05 Discussion Break 11:20–11:30 Session 3. Class Projects 11:30–12:30 11:30 “Superscalar out-of-order demystified in four instructions,” James C. Hoe, Carnegie Mellon University ......................................................................................................................................... 22 11:50 “Bridging the gap between undergraduate and graduate experience in -
Series 3000 Reference Manua
inter Series 3000 Family Of Computing Elements - The Total System Solution. Since its introduction in September, 1974, the Series 3000 family of computing elements has found acceptance in a wide range of high performance applications from disk controllers to airborne CPU's. The Series 3000 family represents more than a simple collection of bipolar components, it is a complete family of computing elements and hardware/software support that greatly simplifies the task of transforming a design from concept to production. The Series 3000 Component Family A complete set of computing elements that are designed as a system requiring a minimum amount of ancillary circuitry. 3001 Microprogram Control Unit. 3002 Central Processing Element. 3003 . Look-Ahead Carry Generator. 3212 Multi-Mode Latch Buffer. 3214 Interrupt Control Unit. 3216/26 Parallel Bi-directional Bus Driver. ROMs/PROMs A complete set of bipolar ROMs and PROMs. RAMs A Complete family of MOS and bipolar RAMs. rhe Series 3000 Support A comprehensive support system that assists the designer in writing microprograms, debugging hardware and microcode, and programming prototype and production PROMs. CROMIS Cross microprogram assembler. MDS-800 Microcomputer development system with TTY/CRT, line printer, diskette, PROM programmer and high speed paper tape reader facilities. ICE-30 In-circuit emulation for the 3001 MCU. ROM-SIM ROM simulation for all of Intel's Bipolar ROMs and PROMs. Application Central processor and disk controller designs and Notes system timing considerations. Customer Comprehensive 3 day course covering the component Course family, CPU and controller designs, microprogramming and the MDS-800, ICE-30 and ROM-SIM operation. -
Micro Machine·Independent Microassembler
MICRO MACHINE·INDEPENDENT MICROASSEMBLER 11 July 1980 ... by. Edward Fiala Peter Deutsch Butler Lampson Xerox Palo Alto Research Center 3333 Coyote Hill Rd. Palo Alto, CA. 94304 Filed on: [Maxcl]<AltoDOCS>Micro.Press Sources on: [Ivy]<DoradoSource)MicroMemo.Dm This manual describes a machine-independent microassembly language originally developed for the Maxcl computer and since used for the Maxc2, Dorado, and DO computers as well as for several smaller projects. This manual is the property of Xerox Corporation and is to be used solely for evaluative purposes. No part thereof may be reproduced, stored in a retrieval system transmited, disseminated, or disclosed to others in any form or by any means without prior written permission of Xerox. Micro: Machine-Independent MicroAssembler 11 July 1980 2 TABLE OF CONTENTS 1. Introduction . .. 3 2. Assembly Procedures . .. 3 3. Error Messages. .. 6 4. Assembly Listings ..............'. .. 7 5. Cross Reference Listings. .. 8 6. Comments .................................... 9 7. Statements.................................... 10 7.1 Builtins.................................. 11 7.2 Defining Symbols . ............... 11 7.3 Tokens.................................. 13 7.4 Neutrals and Tails ........................... 14 7.5 Clause Evaluation ........................... 16 7.6 Treatment of Arguments ...................... 16 7.7 Undefined Symbols. .. 17 7.7.1 Destination Addresses .................... 18 7.7.2 Octal Numbers ......................... 18 7.7.3 Literals ............................. -
C-Ware Software Toolset Tutorial Workbook
User Guide C-WARE SOFTWARE TOOLSET TUTORIAL WORKBOOK C-WARE SOFTWARE TOOLSET VERSION 2.2 CSTTW-UG/D Rev 00 C-Ware Software Toolset Tutorial Workbook C-WARE SOFTWARE TOOLSET, VERSION 2.2 CSTTW-UG/D Rev 00 Copyright © 2003 Motorola, Inc. All rights reserved. No part of this documentation may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from Motorola. Motorola reserves the right to revise this documentation and to make changes in content from time to time without obligation on the part of Motorola to provide notification of such revision or change. Motorola provides this documentation without warranty, term, or condition of any kind, either implied or expressed, including, but not limited to, the implied warranties, terms or conditions of merchantability, satisfactory quality, and fitness for a particular purpose. Motorola may make improvements or changes in the product(s) and/or the program(s) described in this documentation at any time. C-3e, C-5, C-5e, C-Port, C-Ware, Q-3, and Q-5 are all trademarks of C-Port, a Motorola Company. Motorola and the stylized Motorola logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. CSTTW-UG/D Rev 00 CONTENTS About This Guide Guide Overview . 9 Using PDF Documents . 10 Guide Conventions . 11 References to CST Pathnames . 12 Revision History . 13 Related Product Documentation . 14 LESSON 1 Workbook Overview Overview . 17 Lessons . 17 Lessons in This Workbook . -
Optimal Multithreaded Batch-Parallel 2-3 Trees Arxiv:1905.05254V2
Optimal Multithreaded Batch-Parallel 2-3 Trees Wei Quan Lim National University of Singapore Keywords Parallel data structures, pointer machine, multithreading, dictionaries, 2-3 trees. Abstract This paper presents a batch-parallel 2-3 tree T in an asynchronous dynamic multithreading model that supports searches, insertions and deletions in sorted batches and has essentially optimal parallelism, even under the restrictive QRMW (queued read-modify-write) memory contention model where concurrent accesses to the same memory location are queued and serviced one by one. Specifically, if T has n items, then performing an item-sorted batch (given as a leaf-based balanced binary tree) of b operations · n ¹ º ! 1 on T takes O b log b +1 +b work and O logb+logn span (in the worst case as b;n ). This is information-theoretically work-optimal for b ≤ n, and also span-optimal for pointer-based structures. Moreover, it is easy to support optimal intersection, n union and difference of instances of T with sizes m ≤ n, namely within O¹m·log¹ m +1ºº work and O¹log m + log nº span. Furthermore, T supports other batch operations that make it a very useful building block for parallel data structures. To the author’s knowledge, T is the first parallel sorted-set data structure that can be used in an asynchronous multi-processor machine under a memory model with queued contention and yet have asymptotically optimal work and span. In fact, T is designed to have bounded contention and satisfy the claimed work and span bounds regardless of the execution schedule. -
On Data Structures and Memory Models
2006:24 DOCTORAL T H E SI S On Data Structures and Memory Models Johan Karlsson Luleå University of Technology Department of Computer Science and Electrical Engineering 2006:24|: 402-544|: - -- 06 ⁄24 -- On Data Structures and Memory Models by Johan Karlsson Department of Computer Science and Electrical Engineering Lule˚a University of Technology SE-971 87 Lule˚a, Sweden May 2006 Supervisor Andrej Brodnik, Ph.D., Lule˚a University of Technology, Sweden Abstract In this thesis we study the limitations of data structures and how they can be overcome through careful consideration of the used memory models. The word RAM model represents the memory as a finite set of registers consisting of a constant number of unique bits. From a hardware point of view it is not necessary to arrange the memory as in the word RAM memory model. However, it is the arrangement used in computer hardware today. Registers may in fact share bits, or overlap their bytes, as in the RAM with Byte Overlap (RAMBO) model. This actually means that a physical bit can appear in several registers or even in several positions within one regis- ter. The RAMBO model of computation gives us a huge variety of memory topologies/models depending on the appearance sets of the bits. We show that it is feasible to implement, in hardware, other memory models than the word RAM memory model. We do this by implementing a RAMBO variant on a memory board for the PC100 memory bus. When alternative memory models are allowed, it is possible to solve a number of problems more efficiently than under the word RAM memory model.