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MIPI I3C®: a New Bare-Metal Interface for Debug and Test

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MIPI I3C®: a New Bare-Metal Interface for Debug and Test March 3 - 6, 2019 Hilton Phoenix / Mesa Hotel Mesa, Arizona Archive COPYRIGHT NOTICE The presentation(s)/poster(s) in this publication comprise the proceedings of the 2019 TestConX workshop. The content reflects the opinion of the authors and their respective companies. They are reproduced here as they were presented at the 2019 TestConX workshop. This version of the presentation or poster may differ from the version that was distributed in hardcopy & softcopy form at the 2019 TestConX workshop. The inclusion of the presentations/posters in this publication does not constitute an endorsement by TestConX or the workshop’s sponsors. There is NO copyright protection claimed on the presentation/poster content by TestConX. However, each presentation/poster is the work of the authors and their respective companies: as such, it is strongly encouraged that any use reflect proper acknowledgement to the appropriate source. Any questions regarding the use of any materials presented should be directed to the author(s) or their companies. “TestConX” and the TestConX logo are trademarks of TestConX. All rights reserved. www.testconx.org Session 1B Presentation 4 TestConX 2019 On the Bus - Advanced bus protocols for validation MIPI I3C®: A New Bare-Metal Interface for Debug and Test Enrico Carrieri Intel Corporation Debug WG Chair, MIPI Alliance Mesa, Arizona ● March 3 - 6, 2019 TestConX Workshop www.testconx.org March 3-6, 2019 Session 1B Presentation 4 TestConX 2019 On the Bus - Advanced bus protocols for validation Topics • Problem Statement • Goals • Solution: MIPI I3C • Debug/Test Extensions to MIPI I3C • On-going Development • Summary / Conclusions MIPI I3C: A New Bare-Metal Interface for Debug and Test 2 TestConX Workshop www.testconx.org March 3-6, 2019 Session 1B Presentation 4 TestConX 2019 On the Bus - Advanced bus protocols for validation Problem Statement Current debug and test interface solutions (e.g., JTAG/cJTAG, I2C, UART) are falling short in meeting newer requirements/use cases. For example: • Want to debug/test all components (application processor, PMIC, & modem). Application Processor Switch/Mux • Want to attach debug and test system SB U Pins For USB Interface (DTS) to external pins yet still use the Type-C application processor and modem as USB Type-C Receptacle DTS. Modem PMIC • Must work if application processor is Interface Interface powered down (e.g., low power state). MIPI I3C: A New Bare-Metal Interface for Debug and Test 3 TestConX Workshop www.testconx.org March 3-6, 2019 Session 1B Presentation 4 TestConX 2019 On the Bus - Advanced bus protocols for validation Goals Have a scalable, multi-mastering debug and test interface that can connect power managed components on a platform. It shall… 1. Require a minimal set of pins (i.e., 2 wires) including those needed for interrupts. Application Processor Switch/Mux SB U Pins For USB Interface Type-C USB Type-C Receptacle 2 Modem PMIC Interface Interface MIPI I3C: A New Bare-Metal Interface for Debug and Test 4 TestConX Workshop www.testconx.org March 3-6, 2019 Session 1B Presentation 4 TestConX 2019 On the Bus - Advanced bus protocols for validation Goals (#2) Have a scalable, multi-mastering debug and test interface that can connect power managed components on a platform. It shall… 2. Allow multi-component connectivity. Application Processor Switch/Mux SB U Pins Slave For USB Interface Type-C USB Type-C Receptacle 2 Modem PMIC Slave Slave Interface Interface MIPI I3C: A New Bare-Metal Interface for Debug and Test 5 TestConX Workshop www.testconx.org March 3-6, 2019 Session 1B Presentation 4 TestConX 2019 On the Bus - Advanced bus protocols for validation Goals (#3) Have a scalable, multi-mastering debug and test interface that can connect power managed components on a platform. It shall… 3. Support multiple entry/mastering points to allow flexibility across the platform’s lifecycle. Debug and Test Application Processor System (DTS) Switch/Mux Master Debug and Master SBU Pins For USB & Slave Software Test System Interface Type-C Interface (DTS) USB Type-C Receptacle 2 Modem PMIC Debug and Master Slave Network Interface & Slave Test System Interface (DTS) Interface MIPI I3C: A New Bare-Metal Interface for Debug and Test 6 TestConX Workshop www.testconx.org March 3-6, 2019 Session 1B Presentation 4 TestConX 2019 On the Bus - Advanced bus protocols for validation Goals (#4) Have a scalable, multi-mastering debug and test interface that can connect power managed components on a platform. It shall… 4. Allow components in the platform to power down (and not break the network) and rejoin the network upon powering up. Debug and Test Application Processor System (DTS) Switch/Mux Master Debug and Master SBU Pins For USB & Slave Software Test System Interface Type-C Interface (DTS) USB Type-C Receptacle 2 Modem PMIC Debug and Master Slave Network Interface & Slave Test System Interface (DTS) Interface MIPI I3C: A New Bare-Metal Interface for Debug and Test 7 TestConX Workshop www.testconx.org March 3-6, 2019 Session 1B Presentation 4 TestConX 2019 On the Bus - Advanced bus protocols for validation Foundation: MIPI Alliance I3C® The MIPI Improved Inter Integrated Circuit (I3C) interface has key features that address debug and test requirements. • Multi-drop, two wire interface supporting multiple masters and the ability for devices to hot-join. Supports clocks up to 12.5MHz and high data rate modes. • Uses a master-slave communication/control method. – Supports multiple masters and uses a handoff method to change mastership of the bus. • Supports in-band interrupts (IBI) from the slave to the master. – For debug, can be used to indicate changes in states and when trace buffering thresholds have been reached. • The solution is based on the MIPI I3C BasicSM v1.0 Specification and the upcoming MIPI I3C® v1.1 Specification. MIPI I3C: A New Bare-Metal Interface for Debug and Test 8 TestConX Workshop www.testconx.org March 3-6, 2019 Session 1B Presentation 4 TestConX 2019 On the Bus - Advanced bus protocols for validation Solution: MIPI Debug for I3C The MIPI I3C specification alone helps to achieve our goals… Debug and Test Application Processor System (DTS) Switch/Mux Debug and SBU Pins I3C Master I3C Master For USB Software Test System & Slave Type-C (DTS) USB Type-C Receptacle Modem PMIC Debug and (SDA/SCL) I3C I3C Master Network Interface I3C Slave Test System & Slave (DTS) … but there is more that can be done to help debug/test! MIPI Debug for I3C Specification MIPI I3C: A New Bare-Metal Interface for Debug and Test 9 TestConX Workshop www.testconx.org March 3-6, 2019 Session 1B Presentation 4 TestConX 2019 On the Bus - Advanced bus protocols for validation How Debug and Test Uses/Extends I3C Using the MIPI I3C Specification as the foundation, the solution extends the capabilities specifically for debug and test functionality. • The MIPI Debug for I3C Specification describes these “extensions” for using the I3C bus interface for debug and test. • All the features of I3C including 2 wires, hot-join, IBI, multi-drop, broadcast messaging, and multi-mastering are supported. • It uses existing common command codes (CCC) as well as defines specific CCCs for debug/test configuration, function selection, and action/event triggers and interrupts. • It also standardizes the data exchange mechanisms on predefined port based communication. MIPI I3C: A New Bare-Metal Interface for Debug and Test 10 TestConX Workshop www.testconx.org March 3-6, 2019 Session 1B Presentation 4 TestConX 2019 On the Bus - Advanced bus protocols for validation MIPI Debug for I3C Features • Allows dedicated debug/test or shared bus topologies. • Handles debug communication over defined byte-oriented streaming interface ports that can support different protocols. • Allows the target system (TS) to expose multiple debug/test interfaces/ports from a single physical connection. • Allows the debug and test system (DTS) to send broadcast or directed action requests. (e.g., halt, reset) • Allow the TS to send event indications via IBIs. (e.g., triggers, requests) MIPI I3C: A New Bare-Metal Interface for Debug and Test 11 TestConX Workshop www.testconx.org March 3-6, 2019 Session 1B Presentation 4 TestConX 2019 On the Bus - Advanced bus protocols for validation Conceptual Target System Diagram Defined by MIPI Debug for I3C SoC’s Current Debug/Test Infrastructure Processor x Debug Port UART Debug Port I3C Private Data to Debug/ Machine Inbound FIFO Write Data Test Function Processor y FIFO Control FIFO Status Access Debug/Test I3C CCCs Configuration, Control, Control from Deb ug/ MIPI I3C Slave Space Logic I3C IBIs and Status Logic Test Function Debug Port SneakPeek Controller Engine Access FIFO Control FIFO Status I3C Bus (SDA/SCL) Bus I3C Space JTAG/TAP I3C Private Data from Debug/ Network Outbound FIFO Read Data Test Function Debug/Test Debug Port Logic • The MIPI SneakPeek Engine is defined by the MIPI SneakPeek Protocol Specification. MIPI I3C: A New Bare-Metal Interface for Debug and Test 12 TestConX Workshop www.testconx.org March 3-6, 2019 Session 1B Presentation 4 TestConX 2019 On the Bus - Advanced bus protocols for validation Besides Hardware Specifications… …work is being done to help define tooling and software. DTS Application Processor I3C on USB Switch/Mux Type-C SBU pins SBU Pins I3C Master For USB & Slave Type-C USB-to-I3C USB Adapter USB Type-C Receptacle Modem PMIC I3C (SDA/SCL) I3C I3C Master I3C Slave • DTS Adapters for USB & Slave • USB Device Class for I3C • Software Flows including those for multiple-mastering MIPI I3C: A New Bare-Metal Interface for Debug and Test 13 TestConX Workshop www.testconx.org March 3-6, 2019 Session 1B Presentation 4 TestConX 2019 On the Bus - Advanced bus protocols for validation DTS Development • Common (both debug/test and not) USB Device Class for I3C Mastering from the DTS.
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