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Leakage Reduction Techniques Leakage Reduction Techniques Stefan Rusu Senior Principal Engineer Intel Corporation February 3rd, 2008 © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Outline • Leakage mechanisms and trends • Leakage reduction techniques • Future process technology options • Summary © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Transistor Leakage Mechanisms © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Technology Scaling Trends • Physics requires increased leakages at smaller dimensions • Failure to deal with leakage implies slower scaling © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Server Processor Power Trends 1000 Total Power 100 ▼ 10 Active Power 1 Power [W] Power 0.1 Leakage ► 0.01 0.001 1990 1992 1994 1996 1998 2000 2002 2004 2006 Year © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Source/Drain Leakage (Ioff) 1.E-04 Research data in literature ( ) 1.E-06 1.E-08 Production data in literature ( ) (A/um) 1.E-10 Off I 1.E-12 1.E-14 10 100 1000 Physical Gate Length (nm) © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Strained Silicon K.K.Mistry,Mistry, 2004 VLSI • 30% Idsat improvement at fixed Ioff • 50x Ioff reduction at fixed Idsat • Performance and leakage are intimately related © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Gate Leakage Trends → 40% ∆Vgs ~5X IG © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Gate Leakage Trends (cont) 106 nFET 105 Measurement 10 A 104 Simulation 103 ) 15 A 2 102 101 20 A 100 21.9 A 10-1 10-2 25.6 A 10-3 29.1 A 10-4 32.2 A 10-5 -6 35.0 A Gate Current Density (A/cm Density Current Gate 10 10-7 36.1 A 10-8 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Gate Voltage (V) • Leakage increases by 10x for every 2Å (SiO2) gate thickness reduction K. Itoh, Trends in Low-Voltage RAM Circuits, FTFC 2003 © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Gate Leakage Trends (cont) 10 1000 Poly SiON 100 Silicon 10 1 0.1 GateLeakage (Rel.) Electrical (Inv) ToxElectrical (Inv) (nm) 1 0.01 350nm 250nm 180nm 130nm 90nm 65nm • SiON scaling running out of atoms • Poly depletion limits inversion TOX scaling [Mistry, et. al, IEDM 2007] © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE 45nm High-K + Metal Gate Transistors Metal Gate –Increases the gate field effect High-K Dielectric – Increases the gate field effect – Allows use of thicker dielectric layer to reduce gate leakage HK + MG Combined – Drive current increased >20% – Or source-drain leakage reduced >5x – Gate oxide leakage reduced http://download.intel.com/pressroom/kits/45nm/ Press%2045nm%20107_FINAL.pdf © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE HK+MG Gate Leakage Reduction • Gate leakage is reduced >25X for NMOS and 1000X for PMOS 100 SiON/Poly 65nm 10 1 SiON/Poly 65nm 0.1 0.01 0.001 HiK+MG 45nm HiK+MG 45nm 0.0001 NormalizedGate Leakage PMOS NMOS 0.00001 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 VGS (V) 65nm: Bai, 2004 IEDM 45nm: Mistry, 2007 IEDM © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Voltage Dependence 100% 130nm process 80% 60% Sub-threshold 40% Leakage ► ◄ Gate 20% Leakage Normalized Leakage Normalized 0 0 0.3 0.6 0.9 1.2 1.5 Voltage (V) Leakage components are a strong function of voltage [Krishnamurthy, et. al, ASICON 2005] © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Temperature Dependence 6 Sub-threshold 5 Gate Junction 4 3 Relative Leakage Relative 2 1 20 30 40 50 60 70 80 90 100 Temperature [deg.C] [Mukhopadhyay, et al., VLSI Symposium 2003] © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Optimal Active / Leakage Power Ratio Optimal active/leakage power ratio is 70/30 [Kuroda, ICCAD 2002] © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Outline • Leakage mechanisms and trends • Leakage reduction techniques • Future process technology options • Summary © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Leakage Reduction Techniques • Transistor level – Longer transistor Le – Higher-Vt devices • Block level – MOS Threshold Voltage Control (MTCMOS, VTCMOS) –Gate Voltage Control (SCCMOS, BGMOS) – Transistor stacking methods – Cache leakage reduction – Sleep transistors • Chip level – Multiple voltage supplies – Adaptive body bias © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Transistor Leakage Reduction [Wang, et. al, ISSCC, 2007] © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Long-Le Transistors Nominal Le • All transistors can be either nominal or long-Le • Most library cells are available in both flavors • Long-Le transistors are ~10% slower, but have 3x lower leakage • All paths with timing slack use long-Le transistors • Initial design uses only long channel devices Long Le (Nom+10%) [Rusu, et. al, ISSCC 2006] © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Long-Le Transistors Usage Long channel device average usage summary Cores 54% Uncore 76% Cache 100% 100% 80% 60% 40% 20% Long-Le Usage (%) L3 Cache Cor 1 C 0% on tr ol Core 0 [Rusu, et. al, ISSCC 2006] © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Layout Regularity Dummy devices Layout View Before After Backside Infrared Emission Regular layout reduces variability and leakage [Rikhi and Rusu, IDF 2006] © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Low-Leakage PowerPC 750 • 0.13um SOI CMOS technology with copper interconnect, low-k dielectric, multi-threshold transistors, and dual oxide thickness FETs [Geissler, et. al, ISSCC 2002] © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Triple Vt Usage in PowerPC 750 • Three threshold voltage devices are used for both the nFET and pFET, high Vt, standard Vt and low Vt devices • Low Vt devices are used in frequency-limiting paths only • High Vt devices are used in paths which are not frequency- limiting and in SRAM arrays [Geissler, et. al, ISSCC 2002] © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Power5 Leakage Reduction IBM’s Power Processors are leveraging triple Vt process option [Clabes, et al., ISSCC 2004] © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Leakage Reduction Circuit Techniques Body Bias Stack Effect Sleep Transistor Vbp Vdd +Ve Equal Loading Logic Block -Ve Vbn © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Body Bias Leakage Reduction [Keshavarzi, et al., D&TC 2002] © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Speed-adaptive Vt with Forward Bias Gate length - 0.2 um Oxide thickness - 4.5 nm Interconnect metal - 5 layers Well structure - triple well [Miyazaki, et al – ISSCC 2000] © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE SA-Vt Implementation Bias voltages in different operating modes Bias and supply voltage distribution [Miyazaki, et al – ISSCC 2000] © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE SA-Vt Experimental Results Forward-bias effect Standby Current [Miyazaki, et al – ISSCC 2000] © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Scalability of Reverse Body Bias Reverse Body Bias is less effective with technology scaling [Keshavarzi, et al – ISLPED 1999] © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Stack Forcing 100e-1210 Two-stack Two-stack load Wu = Wl High-VtT Low -VtT w Performance input load - delay Loss ? Equal Loading wu? ½ w High-VtT wl??? ½ w Normalized delay Low -V- Normalized iso- Normalized wu+wl = w T wu under iso 10e-121 Leakage 1e-5 1e-4 1e-3 1e-2 1e-1 1e+01 Reduction NormalizedNormalized Ioff Ioff • Force one transistor into a two transistor stack wl with the same input load • Can be applied to gates with timing slack • Trade-off between transistor leakage and speed [Narendra, et al – ISLPED 2001] © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE 1.5V 0V Natural Stacks 1.5V Ileak = 9.96nA 1.5V 1.5V • Leakage reduced significantly when 1.5V two transistors are off in a stack 0V • Educate circuit designers, 0V Ileak = 1.71nA monitor average stacking factor 1.5V 1.5V 1.5V 12 0V 8 0V Ileak = 0.98nA 0V 1.5V 4 1.5V Leakage[nA] 0 0V 0V Ileak = 0.72nA 1 2 3 4 0V Number of OFF transistors in stack 0V © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Multi-Threshold CMOS (MTCMOS) [S. Shigematsu, et al - VLSI Symposium, 1995] © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Variable Threshold CMOS (VTCMOS) • In active mode, the VT circuit controls the active bias to compensate Vt fluctuations • In standby mode, the VT circuit applies deeper substrate bias to cut off leakage [T. Kuroda, et al - JSSC, Nov. 1996] © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Super Cut-off CMOS (SCCMOS) • On-chip voltage boost for the sleep control signal reverse biases the sleep PMOS device to suppress leakage • Requires N-well separation and an efficient on-chip boost voltage generator • Oxide reliability is another concern [H. Kawaguchi, et al – ISSCC 1998] © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Boosted Gate MOS (BGMOS) • Logic circuits use thin Tox and low Vt transistors • Leakage cut-off switches use thick Tox and high Vt devices • In active mode the leakage cut-off switches are driven by a boosted gate voltage to reduce the area penalty • Requires dual supply voltages and dual Tox manufacturing process [T. Inukai, et. al – CICC 2000] © 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE Stacking Transistor Insertion • Identify first the circuit input vector that minimizes leakage • For each gate in a high leakage state insert a leakage control transistor • Requires intensive simulations for the optimal vector [M.
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