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7. Smart Power Integrated Circuit Technology ECE1393F Nov. 16, 2004 ECE1393F Nov. 16, 2004 Outline 7. Smart Power Integrated Why Smart Power ICs Circuit Technology Design Challenges Power Devices and Processing Wai Tung Ng Technologies Associate Professor Smart PIC Output Drivers University of Toronto Electrical & Computer Engineering Smart PIC Applications Toronto Ontario Canada M5S 3G4 Future Trends Tel: (416) 978-6249 e-mail: [email protected] © 2002 University of Toronto 8-1 University of Toronto 8-2 ECE1393F Nov. 16, 2004 ECE1393F Nov. 16, 2004 7.1 Why Smart Power Integrated Circuits Why Smart PICs (cont’d) power X If an Integrated Driver- X Example: Conventional interface transistors Electronic Drive — a Controller is mounted on & control the back of each DC circuits number of DC motors motor. The number of may have to be DC wires that need to be controlled Motors routed can be greatly simultaneously. reduced. X The interface circuit on the Multiple smart PIC can also pass Channel monitoring information Power Electronic (e.g. current, voltage and Drives temperature) to and from DC Large wire the controlling host. motor bundle University of Toronto 8-3 University of Toronto 8-4 ECE1393F Nov. 16, 2004 ECE1393F Nov. 16, 2004 Why Smart PICs (cont’d) Why Smart PICs (cont’d) X With a smart PIC driver- X Implementing an integrated driver-controller using Interface bus controller, only a Smart PIC technology not only reduce the wiring minimum of 3 cable complexity, but also offer the following benefits: wires are required: DC x Reduced parts count — improves reliability, reduces Motors interface bus assembly cost, reduces size and weight. and DC power. x Integrated sensors — over current, over voltage and DC power temperature sensing circuits can be used to provide more accurate monitoring of the output power stages. Multiple Channel x Interface logic circuits can provide more advanced Power features such as remote diagnostics and remote Electronic programming. Drives Small wire bundle x Potentially can provide a more optimized design. University of Toronto 8-5 University of Toronto 8-6 ECE1393F Nov. 16, 2004 ECE1393F Nov. 16, 2004 What is Smart Power Integrated Circuits What is Smart PIC? (cont’d) X Conventional VLSI chips are designed to perform X Smart PIC is signal processing (e.g. microprocessor, DSP) only. combination of X Once a decision is made, external discrete power VLSI signal Power transistors electronics are used to drive actuators (e.g. motors, processing and solenoids). high power output driver on the same chip. X The percentage Smart split in chip area PIC can vary, but Analog and Digital 50% to 50% is Signal Processing not uncommon. Brain Power University of Toronto 8-7 University of Toronto 8-8 ECE1393F Nov. 16, 2004 ECE1393F Nov. 16, 2004 Smart PICs Comparing Hybrids and Smart PICs Low Voltage Control Circuits + Power Output Drivers Hybrid Monolithic PICs X LV Control Circuits: typical operating out of a low simple implementation lower total parts count voltage (LV) supply — 3 to 5V established higher reliability X Power Output Drivers: typically operating out of technology high voltage (HV) and/or smaller size high current supplies low cost potentially lower cost X On-chip features: reliability acknowledge D Provide diagnostics and feedback on load and restricted to single established operating conditions function technology D Thermal shutdown cost of developing and maintaining D Short circuit and over voltage protection technology University of Toronto 8-9 University of Toronto 8-10 ECE1393F Nov. 16, 2004 ECE1393F Nov. 16, 2004 Major Applications and Requirements of PICs Example of Smart PIC Chips 100 X Smart PICs can be Linear AC Regulator Motors packaged in a multi-pin 10 Automotive TO-220 like plastic package for better Switching Regulators thermal dissipation. 1 Fluorescent Ballast Digital 0.1 Telecom Load Current (A) Bipolar X The Smart PIC chips 0.01 linear Display are usually bonded on a metal carrier, and then encapsulated in 0.001 1 10 100 1000 plastic. University of Toronto Supply Voltage (V) 8-11 University of Toronto 8-12 ECE1393F Nov. 16, 2004 ECE1393F Nov. 16, 2004 World IC Usage (1998) 7.2 Design Challenges X VLSI usage is X Most high voltage devices are used as switches largely dominated by operating between on and off states computer and slope = 1/Ron consumer products. X Static Considerations: I X These are max D Off State: Breakdown Voltage, V commodity markets B — competitive and Leakage Currents high risk. D On State: Drive Current BV X Auto, industrial, and On resistance, R ∝ (V )2 communication on B Forward On Voltage, VON markets are Current handling Capability I ∝ Area relatively under max developed — great Power Dissipation PDC ∝ Area potential! D Safe Operating Area University of Toronto 8-13 University of Toronto 8-14 ECE1393F Nov. 16, 2004 ECE1393F Nov. 16, 2004 Design Challenges (cont’d) Design Challenges — Isolation Techniques X Dynamic Considerations: X Self Isolation Dynamic SOA D Used mostly in MOS technology D Switching Speed Imax D Storage Time D Source and drain junction isolate Static themselves from each other SDG D Power Dissipation SOA under reverse bias P = P + f E SiO SiO Loss DC SW D Simple implementation p+ n+ 2 n+ 2 B n-drift ESW = switching energy per cycle V f = switching frequency D Minimum area overhead p-well D Limited circuit flexibility D Safe Operating Area p-substrate — source always grounded D Breakdown voltage can be as high as 1000V University of Toronto 8-15 University of Toronto 8-16 ECE1393F Nov. 16, 2004 ECE1393F Nov. 16, 2004 Isolation Techniques (cont’d) Isolation Techniques (cont’d) X Junction Isolation X Dielectric Isolation D Isolation provided by pn junctions with enclosed D Require trench etching and refill technology device well D Trapped charges at wafer bonding interface may D More complicated cause unwanted inversion layer in n-epitaxial layer process, but also more SDG SD versatile G SiO2 n+ SiO2 n+ SiO2 D Source may be above p+ SiO SiO SiO 2 p+ n+ 2 n+ 2 ground potential p+ p-well p+ sinker n-epi sinker p-well D More area overhead n-epi D Large parasitic effects p-buried layer SiO2 (C, BV, leakage) p-substrate p-substrate D Low cost University of Toronto 8-17 University of Toronto 8-18 ECE1393F Nov. 16, 2004 ECE1393F Nov. 16, 2004 Dielectric Isolation Design Challenges — Packaging X Oxygen Implant method X Non-standard packing; primary considerations Oxygen implant include thermal resistance and pin counts. annealed silicon SiO2 oxygen rich silicon surface mount damaged silicon power QUAD n-substrate n-substrate (a) oxygen implant (b) high temperature annealing SiO SiO n-epitaxial layer isolated n-island 2 2 SiO2 SiO2 Variation of TO-220 packages n-substrate n-substrate (c) epitaxy (d) trench etch and refill University of Toronto 8-19 University of Toronto 8-20 ECE1393F Nov. 16, 2004 ECE1393F Nov. 16, 2004 7.3 Power Devices and Processing Power Devices Technologies X Power devices in smart PICs are usually required to X Smart PIC is a specialized subset of VLSI Technology. perform switching functions. X Digital oriented VLSI designer can basically ignore X Thyristors and transistors are the two main classes of process related issues, relying only on logic devices in power applications. synthesizers (e.g. VHDL) and still able to produce. X Transistors are more commonly used in smart PICs, by X Smart PIC designs (similar to analog ICs) are much far MOSFETs are more favorable than bipolar junction more process dependent, especially when pushing the transistors (BJTs) because of simple gate drive. performance envelop. X Power devices can be categorized into either vertical X Smart PIC designers must have a broad knowledge or lateral devices, depending on the path of current spanning from device, process, circuit to systems flow in the transistor structure. issues. X Figure of merit: specific on-resistance (Ω×cm2). X The Smart PIC designers must also have unrestricted access in making critical fabrication process changes. University of Toronto 8-21 University of Toronto 8-22 ECE1393F Nov. 16, 2004 ECE1393F Nov. 16, 2004 Power MOSFETs Power MOSFETs (cont’d) X Prior to the development of MOSFETs, the only X Power MOSFETs was developed in the 1970’s to devices for high speed, medium power applications address the deficiency of power BJTs. was the bipolar junction transistor. X These devices evolve from MOS VLSI technology. X Power BJTs have several problems: X One of main advantage of Power MOSFETs is that Da current driven device, require large base current the gate only requires a bias voltage with no steady- since β is usually very low. state current in either the on or off-state (but there is Deven larger reverse base current is required to turn off switching current to charge and discharge the gate Dbase drive circuitry are complex and expensive electrode), greatly simplifying the gate drive circuitry. Dvulnerable to secondary breakdown that usually occur X MOSFETs are unipolar devices, current when high voltage and high current conditions appears simultaneously conduction in the drift region is by majority DDifficult to make parallel connections for larger current carriers only without carrier injection — no delay handling capability. due to storage time. University of Toronto 8-23 University of Toronto 8-24 ECE1393F Nov. 16, 2004 ECE1393F Nov. 16, 2004 Power MOSFETs (cont’d) Power MOSFETs Structures X The inherent switching speed of MOSFETs is orders X Power MOSFETs can be categorized into V-MOS, of magnitude faster than for power BJTs. VDMOS, and UMOS. X MOSFETs are particularly useful for circuits with high X V-MOS have a V-groove etch from the top side of the switching frequencies where switching losses are the wafer using a preferential (isotropic) etch.
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