OpenPiton+Ariane: The RISC-V Hardware Research Platform
Princeton University and ETH Zürich
http://openpiton.org http://pulp-platform.org Simulating OpenPiton RTL
2 Anatomy of a Simulation
• Simulation model – Design under test (DUT) RTL – Top-level test bench – Simulator compiler arguments • Verilog macros, include directories, monitor params, etc.
• Test stimuli – Assembly tests – C tests – Source/sink bit vectors • Based on infrastructure from Christopher Batten’s group at Cornell
3 OpenPiton Simulation Models
4 Simulation Scripts/Tools
• sims – piton/tools/src/sims/sims,2.0 – Adapted from OpenSPARC T1 – Build individual simulation models and run test stimuli – Regressions • Single simulation model – Supports Synopsys VCS, Mentor ModelSim, and Verilator
• contint – piton/tools/src/contint/contint,1.0 – Calls sims – Continuous integration bundles • Multiple simulation models – Currently only supports SLURM job scheduler and Synopsys VCS
5 Simulator Choice
• Synopsys VCS, Mentor ModelSim, and Verilator are all supported – SPARC only: Cadence Incisive and Icarus Verilog
• Commands shown are for Verilator
• For VCS, replace vlt with vcs
• For ModelSim, replace vlt with msm
6 Building a Simulation Model
• Required sims arguments -sys=
• Other useful arguments -vlt_build_args=
7 Simulation Model Build Outputs
• stdout and sims.log
• build/
8 Example: The manycore Model
• sims -sys=manycore -vlt_build -ariane
– sims.log: check for build errors • Check for SIGDIE
– build/manycore/rel-0.1/
9 Hands-on: The manycore Model
• cd $PITON_ROOT • source piton/ariane_setup.sh • cd $PITON_ROOT/build • sims -sys=manycore -vlt_build –ariane
• Check Outputs – sims.log: check for build errors – build/manycore/rel-0.1/obj_dir/Vcmp_top
10 Running a Simulation
• Required sims arguments -sys=
• Other useful arguments -build_id=
11 Simulation Outputs
• Depends on test type • stdout and sims.log – PASS (HIT GOOD TRAP) • Test binary (diag.exe) • Memory image (mem.image) • Symbol table (symbol.tbl) • Performance log (perf.log) • Status log (status.log)
12 Example: C Program Simulation
• sims -sys=manycore -vlt_run -ariane hello_world.c
– RISC-V assembly tests have the same syntax, but end with .S or.riscv
13 Hands-on: C Program Simulation
• cd $PITON_ROOT/build • sims -sys=manycore -vlt_run -ariane hello_world.c –rtl_timeout=1000000
• Check fake_uart.log for output
14 Example output
15 Debugging Simulations
• Monitors (manycore) – Non-synthesizeable Verilog modules – Instantiated in top-level test bench – X-module references DUT signals • Print useful output • Check properties – Building with the following flag reduces verbosity • -config_rtl=MINIMAL_MONITORING
• Tools for parsing simulation output – pc_grep
16 Debugging Simulations
17 Debugging Simulations with VCS & DVE
• Waveforms - DVE – Build with -debug_all – Run with –gui
• Example: – sims -sys=manycore -ariane -vcs_build –debug_all – sims -sys=manycore -ariane -vcs_run hello_world.c -gui
18 Debugging Simulations
19 Debugging Simulations
20 Debugging Simulations with MSM
• Waveforms – Run with –gui –log_all
• Example: – sims -sys=manycore -ariane -msm_build – sims -sys=manycore -ariane -msm_run hello_world.c –gui –log_all
21 Debugging Simulations
22 Debugging Simulations
23 Exploring the assembly test suite
• piton/verif/diag/assembly/
• Diaglists (piton/verif/diag/*.diaglist) – Groups of assembly tests and assembly test declarations – Assembly test declaration label testfile.s
24 Diaglists
25 Common Test Flags
• -rtl_timeout= – Number of cycles sims will wait before timing out the test • -sim_run_args= – Arguments (e.g. plusargs) to Verilog simulator • -midas_args= – Arguments to SPARC assembler, midas – Thread count, thread stride, and more • -finish_mask= – Mask specifying threads to wait for
26 Example: Precompiled RISC-V Assembly Tests and Benchmarks • Assembly tests (e.g. rv64ui-p-addi.S): • sims -sys=manycore -vlt_run -ariane rv64ui-p-addi.S -precompiled -rtl_timeout=1000000
• Benchmarks (e.g. dhrystone.riscv): • sims -sys=manycore -vlt_run -ariane dhrystone.riscv -precompiled -rtl_timeout=1000000
27 Running a Regression
• Groups of tests as defined in diaglists
• Tests utilize the same simulation model – One build, multiple test runs
• sims -sim_type=vlt –group=
29 Running a Regression
• Example: • sims -sim_type=vlt -group=ariane_tile1_asm_tests_p • sims -sim_type=vlt -group=ariane_tile1_asm_tests_v • sims -sim_type=vlt -group=ariane_tile1_amo_tests_p • sims -sim_type=vlt -group=ariane_tile1_amo_tests_v • sims -sim_type=vlt -group=ariane_tile1_benchmarks • sims -sim_type=vlt -group=ariane_tile1_simple • sims -sim_type=vlt -group=ariane_tile16_simple
30 Regression Outputs
• Simulation model will be built as usual in build/
31 Regression Outputs
32 Continuous Integration Bundles
• Infrastructure for large scale continuous integration testing
• Supports multiple different simulation models
• Specified by XML files
33 Continuous Integration Bundles
. . .
34 Continuous Integration Bundles
35 Running a contint Bundle
• contint – continuous integration tool – Currently requires SLURM job scheduler
• contint --bundle=
• Example: – contint --bundle=git_push
36 contint Bundle Outputs
• All simulation models will be built and simulations submitted to scheduler
• Results will be aggregated and printed to stdout
• Individual simulation results located in – build/contint_
• Re-process results – contint --bundle=
37 contint Bundle Outputs
38 contint Bundle Outputs
39