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Str91xfa ARM9®- Based Microcontroller Family

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Str91xfa ARM9®- Based Microcontroller Family RM0006 Reference manual STR91xFA ARM9®- based microcontroller family Introduction This reference manual provides complete information for application developers on how to use the STR91xFA microcontroller memory and peripherals. The STR91xFA is a family of microcontrollers with different memory sizes, packages and peripherals. For ordering information, pin description, mechanical and electrical device characteristics please refer to the STR91xFA datasheet. For information on programming, erasing and protection of the internal Flash memory please refer to the STR9 Flash programming manual. For information on the ARM966E-S core, please refer to the ARM966E-S Rev. 2 technical reference manual. Related documents ■ Available from www.arm.com: ARM966E-S Rev. 2 technical reference manual ■ Available from www.st.com: – STR91xFA datasheet – STR9 Flash programming manual (PM0020) July 2009 Doc ID 13742 Rev 4 1/488 www.st.com Contents RM0006 Contents 1 Memory and bus architecture . 20 1.1 Introduction . 20 1.2 ARM9 TCM memories . 21 1.2.1 Burst Flash . 22 1.2.2 Memory accelerator: Pre-Fetch Queue (PFQ) and Branch Cache (BC) 23 1.2.3 Main SRAM . 25 1.3 Memory map . 25 1.4 Initialization . 32 1.5 Boot configuration . 33 1.6 OTP sector . 33 1.7 External memory . 34 1.8 Peripheral access . 35 1.9 Peripheral memory map . 35 1.10 FMI register description . 38 1.10.1 Boot bank size register (FMI_BBSR) . 39 1.10.2 Non-boot bank size register (FMI_NBBSR) . 40 1.10.3 Boot Bank base address register (FMI_BBADR) . 40 1.10.4 Non-boot bank base address register (FMI_NBBADR) . 41 1.10.5 FMI Control register (FMI_CR) . 42 1.10.6 FMI Status register (FMI_SR) . 43 1.10.7 BC 16th Entry Target Address register (FMI_BCE16ADDR) . 44 1.11 FMI register map . 44 1.12 External memory interface (EMI) . 45 1.12.1 Functional description . 45 1.12.2 Summary of bus configurations . 46 1.12.3 External memory interface (EMI) configuration/control . 49 1.12.4 External memory interface clock (BCLK) . 49 1.12.5 EMI bus timing configuration . 50 1.12.6 Timing rules . 50 1.12.7 Bus mode configuration . 51 1.12.8 Register description . 58 1.12.9 EMI register map . 64 2/488 Doc ID 13742 Rev 4 RM0006 Contents 2 Power, reset and clocks . 66 2.1 Power supply . 66 2.1.1 Main operating voltages . 66 2.1.2 Independent A/D converter supply and reference voltage . 67 2.1.3 Battery backup . 67 2.1.4 Power-up . 67 2.2 Reset . 68 2.2.1 System reset . 68 2.2.2 Global reset . 68 2.2.3 Reset flags . 68 2.2.4 Reset peripherals (software reset) . 69 2.2.5 Reset output . 69 2.3 Low voltage detector . 69 2.4 Clocks . 70 2.4.1 External clock sources . 70 2.4.2 Master clock (fMSTR) . 72 2.4.3 Flash memory interface clock (FMICLK) . 72 2.4.4 UART and SSP clock (BRCLK) . 72 2.4.5 External memory interface clock (BCLK) . 72 2.4.6 USBCLK . 72 2.4.7 External RTC calibration clock . 72 2.4.8 PHY clock output . 73 2.4.9 PLL . 73 2.4.10 Changing the PLL configuration . 74 2.4.11 Clock dividers . 74 2.4.12 Peripheral clock gating . 74 2.5 Low power modes . 75 2.5.1 Normal run mode . 77 2.5.2 Special interrupt run mode . 77 2.5.3 Idle mode . 78 2.5.4 Sleep mode . 79 2.5.5 Sleep mode and Idle mode configuration considerations . 79 2.6 System control unit (SCU) . 83 2.6.1 SCU interrupts . 83 2.6.2 SRAM configuration/control . 84 2.6.3 PFQ/BC configuration/control . 84 Doc ID 13742 Rev 4 3/488 Contents RM0006 2.6.4 External memory interface (EMI) configuration/control . 84 2.6.5 UART configuration/control . 84 2.6.6 Port 3.0 ETM trigger or external debug request selection . 84 2.6.7 System control unit GPIO registers . 85 2.6.8 ADC Fast trigger conversion in single mode . 85 2.6.9 Register description . 85 2.6.10 SCU register map . 114 3 General purpose I/O ports (GPIO) . 116 3.1 Functional description . 116 3.2 I/O operation . 116 3.2.1 GPIO_DATA register read/write masking . 116 3.2.2 Reset state . 117 3.3 System control unit GPIO registers . 118 3.4 Register description . 119 3.4.1 GPIO data register (GPIO_DATA) . 119 3.4.2 GPIO data direction register (GPIO_DIR) . 120 3.4.3 GPIO mode control register (GPIO_SEL) . 120 3.4.4 GPIO register map . ..
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