BIOS and Programmer's Reference Guide
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North American Company Profiles 8X8
North American Company Profiles 8x8 8X8 8x8, Inc. 2445 Mission College Boulevard Santa Clara, California 95054 Telephone: (408) 727-1885 Fax: (408) 980-0432 Web Site: www.8x8.com Email: [email protected] Fabless IC Supplier Regional Headquarters/Representative Locations Europe: 8x8, Inc. • Bucks, England U.K. Telephone: (44) (1628) 402800 • Fax: (44) (1628) 402829 Financial History ($M), Fiscal Year Ends March 31 1992 1993 1994 1995 1996 1997 1998 Sales 36 31 34 20 29 19 50 Net Income 5 (1) (0.3) (6) (3) (14) 4 R&D Expenditures 7 7 7 8 8 11 12 Capital Expenditures — — — — 1 1 1 Employees 114 100 105 110 81 100 100 Ownership: Publicly held. NASDAQ: EGHT. Company Overview and Strategy 8x8, Inc. is a worldwide leader in the development, manufacture and deployment of an advanced Visual Information Architecture (VIA) encompassing A/V compression/decompression silicon, software, subsystems, and consumer appliances for video telephony, videoconferencing, and video multimedia applications. 8x8, Inc. was founded in 1987. The “8x8” refers to the company’s core technology, which is based upon Discrete Cosine Transform (DCT) image compression and decompression. In DCT, 8-pixel by 8-pixel blocks of image data form the fundamental processing unit. 2-1 8x8 North American Company Profiles Management Paul Voois Chairman and Chief Executive Officer Keith Barraclough President and Chief Operating Officer Bryan Martin Vice President, Engineering and Chief Technical Officer Sandra Abbott Vice President, Finance and Chief Financial Officer Chris McNiffe Vice President, Marketing and Sales Chris Peters Vice President, Sales Michael Noonen Vice President, Business Development Samuel Wang Vice President, Process Technology David Harper Vice President, European Operations Brett Byers Vice President, General Counsel and Investor Relations Products and Processes 8x8 has developed a Video Information Architecture (VIA) incorporating programmable integrated circuits (ICs) and compression/decompression algorithms (codecs) for audio/video communications. -
Beyond MOV ADD XOR – the Unusual and Unexpected
Beyond MOV ADD XOR the unusual and unexpected in x86 Mateusz "j00ru" Jurczyk, Gynvael Coldwind CONFidence 2013, Kraków Who • Mateusz Jurczyk o Information Security Engineer @ Google o http://j00ru.vexillium.org/ o @j00ru • Gynvael Coldwind o Information Security Engineer @ Google o http://gynvael.coldwind.pl/ o @gynvael Agenda • Getting you up to speed with new x86 research. • Highlighting interesting facts and tricks. • Both x86 and x86-64 discussed. Security relevance • Local vulnerabilities in CPU ↔ OS integration. • Subtle CPU-specific information disclosure. • Exploit mitigations on CPU level. • Loosely related considerations and quirks. x86 - introduction not required • Intel first ships 8086 in 1978 o 16-bit extension of the 8-bit 8085. • Only 80386 and later are used today. o first shipped in 1985 o fully 32-bit architecture o designed with security in mind . code and i/o privilege levels . memory protection . segmentation x86 - produced by... Intel, AMD, VIA - yeah, we all know these. • Chips and Technologies - left market after failed 386 compatible chip failed to boot the Windows operating system. • NEC - sold early Intel architecture compatibles such as NEC V20 and NEC V30; product line transitioned to NEC internal architecture http://www.cpu-collection.de/ x86 - other manufacturers Eastern Bloc KM1810BM86 (USSR) http://www.cpu-collection.de/ x86 - other manufacturers Transmeta, Rise Technology, IDT, National Semiconductor, Cyrix, NexGen, Chips and Technologies, IBM, UMC, DM&P Electronics, ZF Micro, Zet IA-32, RDC Semiconductors, Nvidia, ALi, SiS, GlobalFoundries, TSMC, Fujitsu, SGS-Thomson, Texas Instruments, ... (via Wikipedia) At first, a simple architecture... At first, a simple architecture... x86 bursted with new functions • No eXecute bit (W^X, DEP) o completely redefined exploit development, together with ASLR • Supervisor Mode Execution Prevention • RDRAND instruction o cryptographically secure prng • Related: TPM, VT-d, IOMMU Overall.. -
Versa 2700 Series Service and Reference Guide
SOLD BY laptopia2005 DO NOT RESELL!! PROPRIETARY NOTICE AND LIABILITY DISCLAIMER The information disclosed in this document, including all designs and related materials, is the valuable property of NEC Computer Systems Division, Packard Bell NEC, Inc. (NECCSD, PBNEC) and/or its licensors. NECCSD and/or its licensors, as appropriate, reserve all pat- ent, copyright and other proprietary rights to this document, including all design, manufactur- ing, reproduction, use, and sales rights thereto, except to the extent said rights are expressly granted to others. The NECCSD product(s) discussed in this document are warranted in accordance with the terms of the Warranty Statement accompanying each product. However, actual performance of each such product is dependent upon factors such as system configuration, customer data, and operator control. Since implementation by customers of each product may vary, the suitability of specific product configurations and applications must be determined by the customer and is not warranted by NECCSD. To allow for design and specification improvements, the information in this document is subject to change at any time, without notice. Reproduction of this document or portions thereof without prior written approval of NECCSD is prohibited. NEC is a registered trademark, Versa is a U.S. registered trademark, VersaGlide, and PortBar are trademarks, and UltraCare is a U.S. registered service mark of NEC Corporation, used under license. FaxFlash is a service mark of NEC Computer Systems Division (NECCSD), Packard Bell NEC, Inc. All other product, brand, or trade names used in this publication are the property of their respective owners. Second Printing — November 1997 Copyright 1997 NEC Computer Systems Division, Packard Bell NEC, Inc. -
3. Das LPC-Interface 3.1
PCTEC14 Seite 1 3. Das LPC-Interface 3.1. Grundlagen 3.1.1. Einsatzgebiet LPC = Low Pin Count Interface Specification (= “Interface mit geringer Anschlußzahl”). Das LPC-Interface ist ein synchroner Zeitmultiplex-Bus, an den vorzugsweise PC-typische “Standard- und Klein-Peripherie” angeschlossen werden soll. Das betrifft Floppy-Disk-Controller, Tastatur-Controller, Realzeituhr, Schnittstellen-Controller, Audio-Hardware, Systemverwaltungseinrichtungen usw. sowie ROM-Speicheranordnungen (für POST, BIOS, Systemverwaltung usw.). LPC ist ein Interface zwischen Schaltkreisen auf jeweils einer einzigen Leiterplatte (vorzugsweise: auf einem PC-Motherboard); Steckplätze (Slots) sind nicht vorgesehen. LPC soll den bisher als Schaltkreis-Interface verwendeten ISA- bzw. X-Bus ablösen (Abbildungen 3.1 bis 3.3). Die LPC-Spezifikation wurde von Intel entwickelt und 1997 erstmals veröffentlicht (sie ist im Internet zugänglich). Die Entwicklungsziele: # etwas Moderneres als den ISA- oder X-Bus, # beträchtliche Verringerung der Leitungs- und Anschlußzahlen (Kostensenkung), # funktionelle Abwärtskompatibilität zum ISA- bzw. X-Bus (LPC soll dieselben Zugriffe ausführen können: Speicherzugriffe, E-A-Zugriffe, DMA-Betrieb, Busmasterbetrieb, Unterstützung von Wartezuständen, Interruptsignalisierung), # Unterstützung des gesamten linearen Speicheradreßraums (4 GBytes), # Unterstützung von Sonderfunktionen und -betriebsarten (Stromsparsteuerung, Systemverwaltung), # synchrone Arbeitsweise, # Datenraten und Latenzzeiten in derselben Größenordnung wie beim ISA- bzw. X-Bus (LPC muß nicht “schneller” sein; eine Datenrate von 1...2 MBytes/s genügt vollkommen), # Unterstützung weiterer (moderner) Bussysteme (z. B. USB) ist nicht erforderlich (an ein LPC-Interface werden grundsätzlich keine USB-Controller o. dergl. angeschlossen). Abbildung 3.1 Herkömmliches Motherboard mit X-Bus (nach: Intel) Erklärung: Die in der Abbildung dargestellten Speicher- und E-A-Schaltkreise werden herkömmlicherweise direkt an den ISA- Bus oder an den X-Bus angeschlossen. -
Pentium III Processor Active Thermal Management Techniques
Pentium® III Processor Active Thermal Management Techniques Application Note August 2000 Order Number: 273405-001 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Pentium® III processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placin g your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 2000 *Third-party brands and names are the property of their respective owners. -
Intel Pentium III Processor
Intel® Pentium® III Processor – Low Power/440BX AGPset Design Guide December 2002 Order Number: 273532-002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® Pentium® III Processor – Low Power/440BX AGPset, 82443BX Host Bridge/Controller, and 82371EB PCI-to-ISA/IDE Xcelerated Controller may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. -
Application Programming
AMD64 Technology AMD64 Architecture Programmer’s Manual Volume 1: Application Programming Publication No. Revision Date 24592 3.14 September 2007 Advanced Micro Devices AMD64 Technology 24592—Rev. 3.14—September 2007 © 2002 – 2007 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. The information contained herein may be of a preliminary or advance nature and is subject to change without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other appli- cations intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. -
Blancco Erasure Sw 4.10 Hardware Support
BLANCCO ERASURE SW 4.10 HARDWARE SUPPORT Blancco Ltd Länsikatu 15 FIN-80110 JOENSUU, FINLAND [email protected] Tel. +358-207-433-850 [email protected] Tel. +358-207-433-860 Fax +358-207-433-859 PAGE 1/74 Blancco Erasure SW v4.10 hardware support 30/06/2009 TABLE OF CONTENTS Mass storage controllers ....................................................................................................10 SCSI ......................................................................................................................................10 Adaptec .......................................................................................................................... 10 Advanced Micro Devices [AMD] ..................................................................................... 12 Advanced System Products, Inc..................................................................................... 12 Areca Technology Corp. .................................................................................................12 Artop Electronic Corp......................................................................................................12 BusLogic......................................................................................................................... 12 DTC Technology Corp. ...................................................................................................12 Digital Equipment Corporation ........................................................................................ 12 Future Domain Corp. -
Oracle VM Virtualbox Programming Guide
Oracle VM VirtualBox R Programming Guide and Reference Version 5.0.0_BETA1 c 2004-2015 Oracle Corporation http://www.virtualbox.org Contents 1 Introduction 20 1.1 Modularity: the building blocks of VirtualBox................... 20 1.2 Two guises of the same “Main API”: the web service or COM/XPCOM...... 21 1.3 About web services in general............................ 22 1.4 Running the web service............................... 23 1.4.1 Command line options of vboxwebsrv................... 23 1.4.2 Authenticating at web service logon.................... 24 2 Environment-specific notes 26 2.1 Using the object-oriented web service (OOWS)................... 26 2.1.1 The object-oriented web service for JAX-WS................ 26 2.1.2 The object-oriented web service for Python................ 28 2.1.3 The object-oriented web service for PHP................. 29 2.2 Using the raw web service with any language................... 29 2.2.1 Raw web service example for Java with Axis............... 29 2.2.2 Raw web service example for Perl..................... 30 2.2.3 Programming considerations for the raw web service.......... 31 2.3 Using COM/XPCOM directly............................. 35 2.3.1 Python COM API.............................. 35 2.3.2 Common Python bindings layer...................... 35 2.3.3 C++ COM API............................... 36 2.3.4 Event queue processing........................... 37 2.3.5 Visual Basic and Visual Basic Script (VBS) on Windows hosts...... 38 2.3.6 C binding to VirtualBox API........................ 38 3 Basic VirtualBox concepts; some examples 46 3.1 Obtaining basic machine information. Reading attributes............. 46 3.2 Changing machine settings: Sessions........................ 46 3.3 Launching virtual machines............................ -
Oracle VM Virtualbox Programming Guide and Reference
Oracle VM VirtualBox R Programming Guide and Reference Version 4.1.24 c 2004-2012 Oracle Corporation http://www.virtualbox.org Contents 1 Introduction 16 1.1 Modularity: the building blocks of VirtualBox................... 16 1.2 Two guises of the same “Main API”: the web service or COM/XPCOM...... 17 1.3 About web services in general............................ 18 1.4 Running the web service............................... 19 1.4.1 Command line options of vboxwebsrv................... 19 1.4.2 Authenticating at web service logon.................... 20 2 Environment-specific notes 22 2.1 Using the object-oriented web service (OOWS)................... 22 2.1.1 The object-oriented web service for JAX-WS................ 22 2.1.2 The object-oriented web service for Python................ 24 2.1.3 The object-oriented web service for PHP................. 25 2.2 Using the raw web service with any language................... 25 2.2.1 Raw web service example for Java with Axis............... 25 2.2.2 Raw web service example for Perl..................... 26 2.2.3 Programming considerations for the raw web service.......... 27 2.3 Using COM/XPCOM directly............................. 31 2.3.1 Python COM API.............................. 31 2.3.2 Common Python bindings layer...................... 31 2.3.3 C++ COM API............................... 32 2.3.4 Event queue processing........................... 33 2.3.5 Visual Basic and Visual Basic Script (VBS) on Windows hosts...... 34 2.3.6 C binding to XPCOM API.......................... 34 3 Basic VirtualBox concepts; some examples 39 3.1 Obtaining basic machine information. Reading attributes............. 39 3.2 Changing machine settings. Sessions........................ 39 3.3 Launching virtual machines............................ -
"Design Rules, Volume 2: How Technology Shapes Organizations
Design Rules, Volume 2: How Technology Shapes Organizations Chapter 17 The Wintel Standards-based Platform Carliss Y. Baldwin Working Paper 20-055 Design Rules, Volume 2: How Technology Shapes Organizations Chapter 17 The Wintel Standards-based Platform Carliss Y. Baldwin Harvard Business School Working Paper 20-055 Copyright © 2019 by Carliss Y. Baldwin Working papers are in draft form. This working paper is distributed for purposes of comment and discussion only. It may not be reproduced without permission of the copyright holder. Copies of working papers are available from the author. Funding for this research was provided in part by Harvard Business School. © Carliss Y. Baldwin Comments welcome. Please do not circulate or quote. Design Rules, Volume 2: How Technology Shapes Organizations Chapter 17 The Wintel Standards-based Platform By Carliss Y. Baldwin Note to Readers: This is a draft of Chapter 17 of Design Rules, Volume 2: How Technology Shapes Organizations. It builds on prior chapters, but I believe it is possible to read this chapter on a stand-alone basis. The chapter may be cited as: Baldwin, C. Y. (2019) “The Wintel Standards-based Platform,” HBS Working Paper (November 2019). I would be most grateful for your comments on any aspect of this chapter! Thank you in advance, Carliss. Abstract The purpose of this chapter is to use the theory of bottlenecks laid out in previous chapters to better understand the dynamics of an open standards-based platform. I describe how the Wintel platform evolved from 1990 through 2000 under joint sponsorship of Intel and Microsoft. I first describe a series of technical bottlenecks that arose in the early 1990s concerning the “bus architecture” of IBM-compatible PCs. -
PCM-5823 at Our Website: Click HERE PCM-5823
Full-service, independent repair center -~ ARTISAN® with experienced engineers and technicians on staff. TECHNOLOGY GROUP ~I We buy your excess, underutilized, and idle equipment along with credit for buybacks and trade-ins. Custom engineering Your definitive source so your equipment works exactly as you specify. for quality pre-owned • Critical and expedited services • Leasing / Rentals/ Demos equipment. • In stock/ Ready-to-ship • !TAR-certified secure asset solutions Expert team I Trust guarantee I 100% satisfaction Artisan Technology Group (217) 352-9330 | [email protected] | artisantg.com All trademarks, brand names, and brands appearing herein are the property o f their respective owners. Find the Advantech PCM-5823 at our website: Click HERE PCM-5823 NS Geode Single Board Computer with CPU SVGA/LCD, Dual Ethernet Interface Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com Copyright Notice This document is copyrighted, 2000. All rights are reserved. The original manufacturer reserves the right to make improvements to the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated or transmitted in any form or by any means without the prior written permission of the original manufacturer. Information provided in this manual is intended to be accurate and reliable. However, the original manufacturer assumes no responsibility for its use, nor for any infringements upon the rights of third parties which may result from its use. Acknowledgements AMD is a trademark of Advanced Micro Devices, Inc. Award is a trademark of Award Software International, Inc. IBM, PC/AT, PS/2 and VGA are trademarks of International Business Machines Corporation.