Freescale Powerpoint Template

Rajeev Kumar i.MX Product Line Manager

August 2011

Freescale on Kaixin Weibo? Tag yourself in photos Please use hashtag and upload your own! #FTF2011#

Connected − Single SW investment, multiple devices in market Automotive Displays − Pin compatibility • Trusted Technology − Up to 15 year life cycle support Over 150 million − Auto grade quality design practices processors shipped − Fully featured, market targeted reference designs − Android, Microsoft, QNX, Linux, Ubuntu optimizations Top 3 AP silicon vendor Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a TM 3 Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. Freescale

Ref Soln

SW/Pin Support Compatibility

Competitors Longevity $ BOM Out of the Box Experience PMIC

fast Channel boot Partner Program Docs

Multiple Markets; Scalable Targeted Secure Trusted Embedded Ease of Use Platforms SW Solutions Partner Leadership

50+ Products >150M Units

• Clear market leader for eReader apps processors (IDC) • No. 2 in Auto Infotainment (Strategy Analytics) • No. 3 in Mobile Apps Processors (Linley 5/2011)

i.MX 6Dual NEW

i.MX51, i.MX50 Color Business Mainstream Medical eReader Tablet Infotainment

i.MX 6Solo NEW i.MX28, i.MX233,

i.MX25, i.MX27, Monochrome Single Connected Smart Differentiation Best Better, Good, Performance/ Multimedia Capability Multimedia Performance/ i.MX31, i.MX35 eReader Function Radio Energy Driver Technology Creation, Content Tablet Meter

Power. We need more. More for streaming video, more for playing Freescale ups ante for games, and more just so that we tablets, phones with Freescale Boosts Share can say we have it. Freescale quad-core i.MX 6 Of Tablet Processor hears us, and it's delivering …. January 3, 2011 Market By Darren Murph By Esther Shein February 4, 2011. Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore December 10, 2010 and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a TM 9 Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. i.MX 6Quad

i.MX 6Dual • Quad ARM Cortex A9. 1/1.2GHz i.MX 6Solo • 1 MB L2 cache, Neon, VFPv3, • Dual ARM Cortex A9, 1/1.2GHz Trustzone • 1 MB L2 cache, Neon, VFPv3, • 3D graphics with 4 shaders up to • Single ARM Cortex A9, 1 GHz Trustzone 200MT/s • 512KB L2 cache, Neon, VFPv3, • 3D graphics with 4 shaders up to • Dual stream 1080p/720p dec/enc Trustzone 200MT/s • External memory support up to 64- • Next generation video, 3D graphics • Dual stream 1080p/720p dec/enc bit DDR3 and 2-channel 32-bit (6Solo only) • External memory support up to 64- LPDDR2 • External memory support up to bit DDR3 and 2-channel 32-bit • Integrated SATA-II 32bit DDR3 and LPDDR2 LPDDR2 • Integrated EPD controller • Integrated SATA-II

Common Features of the i.MX 6 Series Platform

• ARM Cortex A9 based solutions up to 1.2GHz • Dual HD 1080p decode, Dual 720p encode, single stream up to 1080p60, 50Mb/s • 3D video playback in High definition • Low power 1080p playback at 350mW Integrated IO‘s that include HDMI v1.4 w/PHY, LVDS display ports, MIPI CSI/DSI for camera/Display, MIPI HSI, Gigabit Ethernet, multiple USB 2.0, PCI-Express, CAN controller, MLB bus • Consumer, Industrial and Automotive temperature range qualifications • POP, BGA packaging options using low layer count PCB design rules • SW support: Google Android, Microsoft Windows Embedded CE, Ubuntu, QNX, Linux, Linaro, Adobe Flash, Skype

− First product family using new Modular Development Strategy (MDS)

• Family of products supports entire i.MX6x family

− Quad core

− Dual core

− Solo

• Various integration levels target different applications

− PFUZE100: Embedded/ auto-infotainment

− PFUZE101: Single-cell applications

− PFUZE201: Solo low-cost single-cell applications

• PFUZE100 will be available in two versions:

− MCxxxxx – Consumer and Industrial applications (-40C to +85C)

− MCxxxxxA – Automotive Grade 3 applications (-40C to +85C)

Benefits: Up to 2MBps (Slave)

Save System Power – • Local control and power management of multiple Up to 400KBps (Master) sensors

Save System Processing – • Preprocessing of multiple sensor inputs Cap • Fusion of multiple sensors into higher level data Mag Pressure Touch Algorithm Abstraction – Other Sensor Peripherals • Remove sensor specific algorithms from application software build

Speakers SDIO SSI Audio UART ESAI CODEC 3G UART Dual MIC Modem USB ULPI (if needed) i.MX 6 Dual

HDMI LVDS Applications Displays Processor ZigBee RF4CE Home Wireless PFUZE100 1.2Ghz l2C

Platform Dual 1080p Video l2C Power Triple Play Graphics Compass Management 0.8mm BGA or 0.4mm POP Sensors

l2C Gyro IC Accelerometer

3D (Dual) Camera

CSI

MIPI

I2S

SP, SP,

USB

HSI I HSI SDIO Watt Saver SATA AC adapter MCU RF MCU Multi-Format Radio Cap RF Device Storage Wireless Touch charging/docking and Connectivity Sensors

station Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a TM 13 Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. System Control i.MX 6Quad/6Dual Connectivity MMC 4.4 / SD 3.0 x3 • Specifications Secure JTAG − CPU: i.MX 6Quad 4x Cortex-A9 @1.2 GHz, 12000 DMIPS PLL, Osc CPU Platform MMC 4.4 / SDXC − i.MX 6Dual 2x Cortex-A9 @1.2 GHz, 6000 DMIPS Clock & Reset Dual / Quad Cortex-A9 UART x5, 5Mbps − Process: 40nm Smart DMA − Core Voltage: 1.1V 32KB I-cache 32KB D-cache I2C x3, SPI x5 IOMUX per core per core − Package: 21x21 0.8mm Flip-chip BGA 2 Timer x3 ESAI, I S/SSI x3 − 12x12 PoP (LP-DDR2, NAND) NEON PTM per core per core PWM x4 3.3V GPIO Watch Dog x2 • Key Features and Advantages 1MB L2-cache + VFPv3 Keypad − Multi-core architecture for high performance, 1MB L2 cache Power Mgmt S-ATA & PHY 3Gbps − 64-bit LP-DDR2, DDR3 and raw / managed NAND Multimedia − S-ATA 3Gbps interface (SSD / HDD) Power Supplies USB2 OTG & PHY Graphics: OpenGL/ES 2.x, USB2 Host & PHY − Delivers rich graphics and UI in HW Temp Monitor OpenCL/EP, OpenVG 1.x . OpenGL/ES 2.x 3D accelerator with OpenCL EP support USB2 HSIC Host x2 and OpenVG 1.1 acceleration Video Codecs: 1080p30 − Drives high resolution video in HW Internal Memory MIPI HSI Audio: ASRC . Multi-format HD1080 video decode and encode ROM S/PDIF Tx/Rx . 1080p60 decode, 720p60 encode 2x Imaging Processing Unit . High quality video processing (resizing, de-interlacing, etc.) RAM PCIe 2.0 (1-lane) Resizing & Blending − Flexible display support Inversion / Rotation FlexCAN x2 . Four simultaneous: 2x Parallel, 2x LVDS, MIPI-DSI, or HDMI Security Image Enhancement MLB150 + DTCP . Dual display up to WUXGA (1920x1200) and HD1080 RNG − MIPI-CSI2 and HSI LCD & Camera Interface 1Gb Ethernet + IEEE1588 − Increased analog integration simplifies system design and reduces TrustZone HDMI & PHY BOM Ciphers MIPI DSI NAND Ctrl (BCH40) . DC-DC converters and linear regulators supply cores and all internal logic Security Ctrl MIPI CSI2 LP-DDR2, DDR3 / LV-DDR3 . Temperature monitor for smart performance control Secure RTC 24-bit RGB, LVDS (x3-8) x32/64, 533 MHz − Expansion port support via PCIe 2.0 eFuses 20-bit CSI − Car network: 2xCAN, MLB150 with DTCP, 1Gb Ethernet with IEEE1588 Updated from i.MX53

i.MX6Q ARM A9 – Quad Core High Tier USB / MLB

i.MX6D Pin Compatible ARM A9 – Dual Core USB / MLB Software Compatible Mid Tier Common IP

i.MX6S Compatible Pin Entry Tier ARM A9 – Single core USB / MLB

Common ARMV7 architecture

PTM PTM PTM PTM FPU/NEON FPU/NEON FPU/NEON FPU/NEON I/F I/F I/F I/F HW Components:

Cortex-A9 CPU Cortex-A9 CPU Cortex-A9 CPU Cortex-A9 CPU •System: Instruction Data Instruction Data Instruction Data Instruction Data • 2x/4x Cores in i.MX 6 Dual/Quad Cache Cache Cache Cache Cache Cache Cache Cache • 32 KB L1 (I and D) •1MB L2 Cache Snoop Control Unit (SCU) Generalized Accelerator •128 Interrupts Interrupt Control Coherence •Using 2x 64-bit AXI to L2C Cache-2-Cache Snoop and Distribution Timers Port Transfers Filtering • Per core Advanced Bus Interface Unit •32 KB I and 32KB D L1 Cache •Neon, VPU, Jazelle, Trustzone Primary AMBA 3 64bit Interface Optional 2nd I/F with Address Filtering

L2 Cache Controller (PL310) AXI 64-bit AXI 64-bit

AXI 64-bit AXI 64-bit

AXI Fabric

Full suite of Enhanced Richer ‘Standard’ Apps Mobile Services 1- + 2- + 3- + 4- + 5- + +

Cortex A9 (1) Cortex A9 (2) Cortex A9 (3) Cortex A9 (4)

Rich Game VOIP 1 1 1 Same Performance

.82P (v dual) Power .64P (vs Single) .44P (v single) P 36% Lower Power 18 to 56% Lower Power

Assumption Power impact Note Frequency 2000 500 P .25P F linear scaling 2 vs 4 Cores 2 Core 4Cores 4* 0.25P 1P Quad Cores Voltage 1.2Volt 1.0Volt .82@ P .82P V2 scaling factor Frequency 2000 500 P .25P F linear scaling 1 vs 4 Cores 1 Core 4Cores 4* 0.25P 1P Quad Cores Voltage 1.5Volt 1.0Volt .44@ 1P .44P V2 scaling factor Frequency 2000 1000 P .5P F linear scaling 1 vs 2Cores 1 Core 2 Core 2* .5P 1P Dual Cores Voltage 1.5Volt 1.2Volt .64@ 1P .64P V2 scaling factor

15.7 mm 15.7 • Assumptions: 127.65 mm 78.4 mm LCD − System Size: 127.6 x 78.4 x 15.7 − Outside ambient temperature at 40 C − Processor usage power 2W continuous − Processor is the only power source in the system − System PCB is a 6 layer 1.2 mm thickness Board

CPU package size 2.19mm HFCBGA 1.7mm HFCBGA 1.7mm 1.2mm 1.2mm FCBGA FCBGA TFBGA Max pkg power without 2.3W 2.3W 1.8W 1.8W 1.7W heatsink (goal 2Watts) Max pkg power with graphite 4.6W 4.6W 3.6W 3.6W 3.4W heat spreader 5 cents (US) cost adder Max pkg power with heatsink 5.5W 5.5W 4.5W 4.5W 4.2W $1.50 (US) cost adder

14000 Dual A15 @ 2Ghz requires Better than A9 3.2 Watts thermal budget 12000 to equal 4 A9s @ 1.2Ghz Better

10000 than DMIPs A15 Using case study from previous 8000 Dual Cortex A15’s A9 example: require ~1W more 6000 A15 to reach same • Up to ~1.7W with no heat

ax Available Available ax performance as sink 4000 M Quad Cortex A9’s • Up to ~3.4W with graphite 2000 heat spreader($0.05) • Up to ~4.2W with heat sink 0 2 2.5 3 3.5 4 4.5 5 ($1.50) CPU thermal budget, W

• Max Performance Comparison (Dual A15 and Quad A9) − Assumes LVT cells used for A15 at 2Ghz vs 1.2Ghz Quad A9 − Assumes Tjunction temp of 125Deg C − Equivalent to sustained performance of Cores running flat out • Dual A15 @ 2Ghz outputs ~ 3.25Watts vs ~2.5W for Quad A9 at same max DMIPS • Dual A15 @ 1.2Ghz will never provide equivalent performance of Quad A9

Apps Processor: Current + Leakage 540mA(740mW) 900mA (2100mW) (125 Deg Tjunction) Main Memory 45 mA (164mW) 45 mA (164mW) Mobile ‘tabbed’ web (250-500Mhz+) WIFI 45mA (162mW) 45mA (162mW) –5Mbit/s, 5+ rich websites open PMIC 1.88 (6.8mW) 1.88 (6.8mW) –Frequent updates Display 47 mA (171mW) 47 mA (171mW) Audio codec 1.4mA (5mW) 1.4mA (5mW) Total Battery Power: (System) 680mA ( 1248mW) 1040mA (2608mW) Battery life (6400mAh) 9.4 hrs 6 hrs Rich web site (100-250 Mhz) –300+ Kb/s, Animated UI’s, Quad A9 @ 600Mhz/core provides 3.4 hours more –Embedded media browsing time at >50% lower total current/power than Dual A15 @ 800Mhz per core (note assumes high DMIPS/Mhz of A15)

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a TM 22 Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. System Control i.MX 6Quad/6Dual Connectivity MMC 4.4 / SD 3.0 x3 • Specifications Secure JTAG − CPU: i.MX 6Quad 4x Cortex-A9 @1.2 GHz, 12000 DMIPS PLL, Osc CPU Platform MMC 4.4 / SDXC − i.MX 6Dual 2x Cortex-A9 @1.2 GHz, 6000 Clock & Reset Dual / Quad Cortex-A9 DMIPS UART x5, 5Mbps Smart DMA − Process: 40nm 32KB I-cache 32KB D-cache I2C x3, SPI x5 − Core Voltage: 1.1V IOMUX per core per core 2 Timer x3 ESAI, I S/SSI x3 − Package: 21x21 0.8mm Flip-chip BGA NEON PTM per core per core − 12x12 PoP (LP-DDR2, NAND) PWM x4 3.3V GPIO • Key Features and Advantages Watch Dog x2 1MB L2-cache + VFPv3 Keypad − Multi-core architecture for high performance, 1MB L2 cache − 64-bit LP-DDR2, DDR3 and raw / managed NAND Power Mgmt S-ATA & PHY 3Gbps − S-ATA 3Gbps interface (SSD / HDD) Multimedia Power Supplies USB2 OTG & PHY − Delivers rich graphics and UI in HW Graphics: OpenGL/ES 2.x, USB2 Host & PHY . OpenGL/ES 2.x 3D accelerator with OpenCL EP support Temp Monitor OpenCL/EP, OpenVG 1.x USB2 HSIC Host x2 and OpenVG 1.1 acceleration Video Codecs: 1080p30 − Drives high resolution video in HW Internal Memory MIPI HSI . Multi-format HD1080 video decode and encode Audio: ASRC . 1080p60 decode, 720p60 encode ROM S/PDIF Tx/Rx 2x Imaging Processing Unit . High quality video processing (resizing, de-interlacing, etc.) RAM PCIe 2.0 (1-lane) − Flexible display support Resizing & Blending Inversion / Rotation . Four simultaneous: 2x Parallel, 2x LVDS, MIPI-DSI, or HDMI FlexCAN x2 Security Image Enhancement . Dual display up to WUXGA (1920x1200) and HD1080 MLB150 + DTCP − MIPI-CSI2 and HSI RNG LCD & Camera Interface 1Gb Ethernet − Increased analog integration simplifies system design and TrustZone HDMI & PHY + IEEE1588 reduces BOM . DC-DC converters and linear regulators supply cores Ciphers MIPI DSI NAND Ctrl (BCH40) and all internal logic Security Ctrl MIPI CSI2 LP-DDR2, . Temperature monitor for smart performance control DDR3 / LV-DDR3 Secure RTC 24-bit RGB, LVDS (x3-8) − Expansion port support via PCIe 2.0 x32/64, 533 MHz − Car network: 2xCAN, MLB150 with DTCP, 1Gb Ethernet with eFuses 20-bit CSI IEEE1588 Updated from i.MX53

• Accelerate existing windowing environments (Android™, X11, etc.) and GC320 base user interfaces with a low-power high-performance composition engine

• Providing compelling vector capabilities for high-quality fonts and automotive clusters in a manner that GC355 assures quality of service in performance

• Accelerate next-generation 3D and GPGPU applications with a feature-rich GC2000 high-performing unified graphics processor

i.MX 6

GC2000 Rightware GPU Benchmarks GPU Rightware

GL benchmark GPU Benchmarks

Vivante applies multi- sampling anti-aliasing by rendering into larger textures for ultra-high image quality

Blinn-Phong shader produces realistic colors calculated from the surrounding environment

Smoke particle system produces realistic plums which must be present

Hover 15-1110

Texture Vector Graphics + Gradient

Pipeline Unit MMU AHB Command & Cache System AXI System Interface GC355 Tessellation Pixel Engine Backend

TextureTexture AXI

&& Cache Cache MMU 2D BLIT System GC320 Command Composition AHB Engine Interface AXI System Engine PixelPixel BackendBackend

iPad 1 iPad 2 GC860 GC860 GC2000 GC2000 Benchmarks SGX535 SGX543MP2 (55nm) vs (40nm) vs 1024x768 (A4 - 40nm) (A5 - 40nm) (fps) iPad 1 (fps) iPad 2 (fps) (fps) 3DMark ES 2.0 Taiji Girl 3.25 11.29 3.70X 23.34 51.15 2.19X Hoverjet 1.93 6.92 3.59X 15.5 32.67 2.11X GLBench 2.0 Egypt 5.05 16.81 3.33X 42.26 76.6 1.80X PRO 17.4 35.52 2.04X 57.58 98.42 1.71X

• Specifications Secure JTAG MMC 4.4 / SD 3.0 x3 − CPU: i.MX 6Quad 4x Cortex-A9 @1.2 GHz, 12000 DMIPS PLL, Osc CPU Platform MMC 4.4 / SDXC − i.MX 6Dual 2x Cortex-A9 @1.2 GHz, 6000 Clock & Reset DMIPS Dual / Quad Cortex-A9 UART x5, 5Mbps − Process: 40nm Smart DMA 32KB I-cache 32KB D-cache I2C x3, SPI x5 − Core Voltage: 1.1V IOMUX per core per core − Package: 21x21 0.8mm Flip-chip BGA 2 Timer x3 ESAI, I S/SSI x3 − 12x12 PoP (LP-DDR2, NAND) NEON PTM per core per core PWM x4 3.3V GPIO Watch Dog x2 1MB L2-cache + VFPv3 Keypad • Key Features and Advantages − Multi-core architecture for high performance, 1MB L2 cache Power Mgmt S-ATA & PHY 3Gbps − 64-bit LP-DDR2, DDR3 and raw / managed NAND Multimedia Power Supplies USB2 OTG & PHY − S-ATA 3Gbps interface (SSD / HDD) Graphics: OpenGL/ES 2.x, USB2 Host & PHY − Delivers rich graphics and UI in HW Temp Monitor OpenCL/EP, OpenVG 1.x USB2 HSIC Host x2 . OpenGL/ES 2.x 3D accelerator with OpenCL EP support and OpenVG 1.1 acceleration Video Codecs: 1080p30 MIPI HSI − Drives high resolution video in HW Internal Memory Audio: ASRC . Multi-format HD1080 video decode and encode ROM S/PDIF Tx/Rx . 1080p60 decode, 720p60 encode 2x Imaging Processing Unit . High quality video processing (resizing, de-interlacing, etc.) RAM PCIe 2.0 (1-lane) Resizing & Blending − Flexible display support Inversion / Rotation FlexCAN x2 . Four simultaneous: 2x Parallel, 2x LVDS, MIPI-DSI, or Security Image Enhancement HDMI MLB150 + DTCP . Dual display up to WUXGA (1920x1200) and HD1080 RNG LCD & Camera Interface 1Gb Ethernet − MIPI-CSI2 and HSI TrustZone + IEEE1588 − Increased analog integration simplifies system design and HDMI & PHY reduces BOM Ciphers MIPI DSI NAND Ctrl (BCH40) . DC-DC converters and linear regulators supply cores Security Ctrl MIPI CSI2 LP-DDR2, and all internal logic DDR3 / LV-DDR3 Secure RTC 24-bit RGB, LVDS (x3-8) . Temperature monitor for smart performance control x32/64, 533 MHz − Expansion port support via PCIe 2.0 eFuses 20-bit CSI − Car network: 2xCAN, MLB150 with DTCP, 1Gb Ethernet with IEEE1588 Updated from i.MX53

Low-Power Audio Decode SW SW • Embeds a flexible, powerful and low power hardware acceleration MPEG-2 Main-High HW HW for HD video decoding in Blu-ray H.264 BP/MP/HP HW HW disk quality VC1 SP/MP/AP HW HW RV10 8/9/10 HW HW • Note: in all cases, the HW CODEC MPEG4/Xvid SP/ASP HW HW meets or exceeds the bit-rate DivX 3/4/5/6 HW HW Low-Power Video requirements specified in the H.263 P0/P3 HW HW Decode standards Sorenson H.263 N/A HW HW AVS Jizhun SW HW

On2 VP6/8 N/A SW HW SVC HP SW HW/SW

MVC N/A SW/HW HW 1080p60 1080i/p30 (* - p only) MJPEG Baseline HW, 40MP/sec HW, 120MP/sec 720p30 or 720p60 H.264 Baseline HW HW* + 720p60 720p20 WVGA H.263 P0/P3 HW HW Low-Power Video D1 (PAL/NTSC) Encode MPEG4 Simple HW HW MJPEG Baseline HW, 80MP/sec HW, 160MP/sec Video Telephony (SiP, H323) – H.264 BP HW HW

Transcode (DLNA) – (M)DMS/(M)DMP HW HW Video de-interlacing HW HW

Further Video Processing (deblocking, resizing, CSC) HW HW

7 to 15 hours of 3D video playback • 1080p60 h.264 MVC • Dual stream at 25Mbps each • 700mW decode power

i.MX 6Dual/ 6Quad 12 hours of 1080p video encode • 1080p30fps H.264 • Single stream at 20Mbps • 300mW encode power

8 hours of 3D video encode • 720p60 h.264 MVC • Dual stream at 25Mbps each • 700mW decode power

Including Memory Image Interface Memory Enhancements And Conversions Displays Display

Interface Optional IntegratedI/F Bridges

• Functions: comprehensive support for the flow of data from an image sensor and/or to a display device. − Connectivity to relevant devices − Related image processing and manipulation − Synchronization and control capabilities

External Memory

• Combining methods (in both cases) Plane 1 DI DP − Color keying and/or alpha blending DC Plane 2 − Alpha: global or per-pixel; interleaved with the DI pixels (upper plane) or as a separate input Plane 3 IC IPUv3 Plane 4

Note: This is the capability of each of the two IPUs, so Combining in the Image Converter (IC) the total capability of the Two planes; both ―full-screen‖ (cover the full output area) processor is doubled. Maximal rate: i.MX37/51 – 20 MP/sec , i.MX53 – 30 MP/sec, i.MX6 Series – 40 MP/sec

i.MX6 Dual/Quad External i.MX6 Dual/Quad External Memory Memory Plane 8 (top) Plane 7 (top) External DI DP DI DP i.MX6 Dual/Quad DC DC Memory

Plane 8 Plane 7 Plane 6 DI DP IC IC DC Plane 7 DI IPUv3 - 1 IPUv3 - 1 Plane 6 Plane 5 Plane 6 VDIC VDIC IC Plane 5 (bottom) CSI IPUv3 - 1 Plane 5 (bottom)

i.MX6 Dual/Quad External i.MX6 Dual/Quad External i.MX6 Dual/Quad External Memory Memory Memory Plane 4 (top) Plane 4 DI DP DI DP Plane 4 DC DC DI DP DC Plane 3

Plane 3 Plane 3 DI IC IC Plane 2 IC IPUv3 - 0 Plane 1 (bottom) IPUv3 - 0 IPUv3 - 0 Plane 2 Plane 2 VDIC VDIC Plane 1 (bottom) Plane 1 (bottom)

Note: Some planes may be a result of additional off-line combining of several planes. Such combining may be performed either with IPUs or GPUs.

Video Content 2 External Front Cam Memory Video Frame Content 3 DP Buffer VPU DI DC Rear Cam Video IPUv3 Content 1 Decode

GPU Graphics Content 1 NAV

External Graphics Memory Content 2 DP Frame DC Buffer DI Graphics Content 3 IPUv3

1280 x 720 (HD720) ~138 Hz 9VGA 1920 x 1440 2.76 74 4XGA 2048 x 1536 3.15 65 1024 x 768 (XGA) ~161 Hz HD1440 2560 x 1440 3.69 56 1920 x 1080 (HD1080) ~61 Hz 4WXGA 2560 x 1600 4.10 50

2048 x 1536 (4XGA) ~40 Hz 4K x 2K 4096 x 2048 8.39 25 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a TM 36 Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. Second Display SDTV WSVGA HDTV WXGA WSXGA+ HDTV First Display 480i30/576i25 (1024x600) 720p60/1080i30 (1366x768) (1680x1050) 1080p60 (27 MHz) (44-49 MHz) (74.25 MHz) (72-85 MHz) (119-146 MHz) (148.5 MHz)

WXGA (1366x768 ~ 1.0 MP; 72-85 MHz) Full Full Full Full Full Full

SXGA (1280x1024 ~ 1.3 MP; 91-109 MHz) Full Full Full Full Partial Partial

SXGA+ (1400x1050 ~ 1.5 MP; 101-122 MHz) Full Full Full Full Partial

WSXGA+ (1680x1050 ~ 1.8 MP; 119-146 MHz) Full Full Full Full Partial

UXGA (1600x1200 ~ 1.9 MP; 130-161 MHz) Full Full Full Partial

WUXGA (1920x1200 ~ 2.3 MP; 154-193 MHz) Full Partial Partial

9VGA (1920x1440 ~ 2.8 MP; 185-234 MHz) Partial Partial

4XGA (2048x1536 ~ 3.2 MP; 209-267 MHz) Partial

This is the capability of each of the two IPUs, so the total capability of the processor is doubled. − The maximal pixel clock rate supported by the display ports . Each display: 220 MHz; Total: 240 MHz − For a TV, the clock rate is fixed by the corresponding standards − For other displays . The assumed screen refresh rate is 60 Hz . The blanking overhead – impacting the pixel clock rate – may vary between displays. The table refers – for concreteness – to the VESA CVT (Coordinated Video Timing) specification • ―Full support‖: allowing full blanking (which is typically required for CRTs) • ―Partial support‖: allowing only reduced blanking (which is still typically sufficient for digital displays, e.g. LCDs) − The above table describes only the capabilities of the display ports to perform screen refresh. A full use case typically includes additional activities and to confirm its support with a given display configuration, additional aspects – video processing capabilities, capacity of the memory system, etc. – should be also analyzed carefully. Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a TM 37 Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. System Control i.MX 6Quad/6Dual Connectivity MMC 4.4 / SD 3.0 x3 • Specifications Secure JTAG − CPU: i.MX 6Quad 4x Cortex-A9 @1.2 GHz, 12000 DMIPS PLL, Osc CPU Platform MMC 4.4 / SDXC − i.MX 6Dual 2x Cortex-A9 @1.2 GHz, 6000 DMIPS Clock & Reset Dual / Quad Cortex-A9 UART x5, 5Mbps − Process: 40nm Smart DMA − Core Voltage: 1.1V 32KB I-cache 32KB D-cache I2C x3, SPI x5 IOMUX per core per core − Package: 21x21 0.8mm Flip-chip BGA 2 Timer x3 ESAI, I S/SSI x3 − 12x12 PoP (LP-DDR2, NAND) NEON PTM per core per core PWM x4 3.3V GPIO Watch Dog x2 • Key Features and Advantages 1MB L2-cache + VFPv3 Keypad − Multi-core architecture for high performance, 1MB L2 cache Power Mgmt S-ATA & PHY 3Gbps − 64-bit LP-DDR2, DDR3 and raw / managed NAND Multimedia − S-ATA 3Gbps interface (SSD / HDD) Power Supplies USB2 OTG & PHY Graphics: OpenGL/ES 2.x, USB2 Host & PHY − Delivers rich graphics and UI in HW Temp Monitor OpenCL/EP, OpenVG 1.x . OpenGL/ES 2.x 3D accelerator with OpenCL EP support USB2 HSIC Host x2 and OpenVG 1.1 acceleration Video Codecs: 1080p30 − Drives high resolution video in HW Internal Memory MIPI HSI Audio: ASRC . Multi-format HD1080 video decode and encode ROM S/PDIF Tx/Rx . 1080p60 decode, 720p60 encode 2x Imaging Processing Unit . High quality video processing (resizing, de-interlacing, etc.) RAM PCIe 2.0 (1-lane) Resizing & Blending − Flexible display support Inversion / Rotation FlexCAN x2 . Four simultaneous: 2x Parallel, 2x LVDS, MIPI-DSI, or HDMI Security Image Enhancement MLB150 + DTCP . Dual display up to WUXGA (1920x1200) and HD1080 RNG − MIPI-CSI2 and HSI LCD & Camera Interface 1Gb Ethernet + IEEE1588 − Increased analog integration simplifies system design and reduces TrustZone HDMI & PHY BOM Ciphers MIPI DSI NAND Ctrl (BCH40) . DC-DC converters and linear regulators supply cores and all internal logic Security Ctrl MIPI CSI2 LP-DDR2, DDR3 / LV-DDR3 . Temperature monitor for smart performance control Secure RTC 24-bit RGB, LVDS (x3-8) x32/64, 533 MHz − Expansion port support via PCIe 2.0 eFuses 20-bit CSI − Car network: 2xCAN, MLB150 with DTCP, 1Gb Ethernet with IEEE1588 Updated from i.MX53

LPDDR2 support Yes CS0# 2Gb, 2Gb, 2Gb, 2Gb, DDR2 support No x162Gb, x162Gb, x162Gb, x162Gb, CS1# DDR3/LVDDR3 support Yes A [15:0], BA [2:0] x16 x16 x16 x16 Bus width 1x32/64 DDR3; DQ [63:48] DQ [47:32] DQ [31:16] DQ [15:0] DQ [31:0] 2x32 (Dual channel) LPDDR2 Max memory size ~4GB Address 16 + 3 (DDR3) CA DDR bus (LPDDR2) # of CS 2 Max.frequency 533MHz (1066Mb/s) MMDC: 2xCh 32-bit, 1GB LPDDR2 ODT Yes Calibration Yes 2Gb, CS0# - ChA • Support of Dynamic Frequency Scaling CS1# - ChA • Software transparent, ensuring data integrity x322Gb, CA [9:0], ChA • Self Refresh and Power Down support x32 • Support Real-Time priority via QoS, e.g. for screen refresh DQ [31:0] - ChA • Access Latency hiding

CS0# - ChB • Bank interleaving, Channel interleaving 2Gb, • Consecutive read/write access optimizations x322Gb, CS1# - ChB • Enabling access priority to open memory pages x32 CA [9:0], ChB • Deep queues for read and write requests DQ [31:0] - ChB

1x LPDDR2 2x LPDDR2 MB/s Display Capability 200Mhz 400Mhz 533Mhz 400Mhz 533Mhz Configuration max 1600 3200 4264 6400 8528 50% 800 1600 2132 3200 4264 Movie Decode (720p) WVGA LCD output 792 Video Record (720p) WVGA LCD output 918 Smartphone Take Picture + Video Record with WVGA Display (720p) WVGA LCD output 1166 (854x480 resolution) Movie Playback (1080p) WVGA LCD + output to TV 1194 Video Record (1080p) WVGA LCD output 1467 Take Picture + Video Record (1080p) WVGA LCD output 1719 3D Game (30MT/s) WVGA LCD + output to TV 1031

Tablet or Smartphone with XGA Display Movie Decode (720p) WXGA LCD output 1011 (1024x768 resolution) Video Record (720p) WXGA LCD output 1731 Take Picture + Video Record (720p) WXGA LCD output 1881 Movie Playback (1080p) WXGA LCD + output to TV 2098 Video Record (1080p) WXGA LCD output 2431 Take Picture + Video Record (1080p) WXGA LCD output 2681 3D Game (30MT/s) WXGA LCD + output to TV 1391

Insufficient

1x LPDDR2 2x LPDDR2 Display Capability 200Mhz 400Mhz 533Mhz 400Mhz 533Mhz Configuration max 1600 3200 4264 6400 8528 50% 640 1280 1705.6 2560 3411 Movie Decode (720p) WVGA LCD output 792 Video Record (720p) WVGA LCD output 918 Take Picture + Video Record (720p) WVGA LCD output 1166 Smartphone Movie Playback (1080p) WVGA LCD + output to TV 1194 with WVGA Display Video Record (1080p) WVGA LCD output 1467 (854x480 resolution) Take Picture + Video Record (1080p) WVGA LCD output 1719 3D Game (30MT/s) WVGA LCD + output to TV 1031

Movie Decode (720p) WXGA LCD output 1011 Tablet or SmartphoneVideo Record (720p) WXGA LCD output 1731 with XGA Display Take Picture + Video (1024x768 resolution) Record (720p) WXGA LCD output 1881 Movie Playback (1080p) WXGA LCD + output to TV 2098 Video Record (1080p) WXGA LCD output 2431 Take Picture + Video Record (1080p) WXGA LCD output 2681 3D Game (30MT/s) WXGA LCD + output to TV 1391

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a TM 41 Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. System Control i.MX 6Quad/6Dual Connectivity MMC 4.4 / SD 3.0 x3 • Specifications Secure JTAG − CPU: i.MX 6Quad 4x Cortex-A9 @1.2 GHz, 12000 DMIPS PLL, Osc CPU Platform MMC 4.4 / SDXC − i.MX 6Dual 2x Cortex-A9 @1.2 GHz, 6000 DMIPS Clock & Reset Dual / Quad Cortex-A9 UART x5, 5Mbps − Process: 40nm Smart DMA − Core Voltage: 1.1V 32KB I-cache 32KB D-cache I2C x3, SPI x5 IOMUX per core per core − Package: 21x21 0.8mm Flip-chip BGA 2 Timer x3 ESAI, I S/SSI x3 − 12x12 PoP (LP-DDR2, NAND) NEON PTM per core per core PWM x4 3.3V GPIO Watch Dog x2 • Key Features and Advantages 1MB L2-cache + VFPv3 Keypad − Multi-core architecture for high performance, 1MB L2 cache Power Mgmt S-ATA & PHY 3Gbps − 64-bit LP-DDR2, DDR3 and raw / managed NAND Multimedia − S-ATA 3Gbps interface (SSD / HDD) Power Supplies USB2 OTG & PHY Graphics: OpenGL/ES 2.x, USB2 Host & PHY − Delivers rich graphics and UI in HW Temp Monitor OpenCL/EP, OpenVG 1.x . OpenGL/ES 2.x 3D accelerator with OpenCL EP support USB2 HSIC Host x2 and OpenVG 1.1 acceleration Video Codecs: 1080p30 − Drives high resolution video in HW Internal Memory MIPI HSI Audio: ASRC . Multi-format HD1080 video decode and encode ROM S/PDIF Tx/Rx . 1080p60 decode, 720p60 encode 2x Imaging Processing Unit . High quality video processing (resizing, de-interlacing, etc.) RAM PCIe 2.0 (1-lane) Resizing & Blending − Flexible display support Inversion / Rotation FlexCAN x2 . Four simultaneous: 2x Parallel, 2x LVDS, MIPI-DSI, or HDMI Security Image Enhancement MLB150 + DTCP . Dual display up to WUXGA (1920x1200) and HD1080 RNG − MIPI-CSI2 and HSI LCD & Camera Interface 1Gb Ethernet + IEEE1588 − Increased analog integration simplifies system design and TrustZone HDMI & PHY reduces BOM Ciphers MIPI DSI NAND Ctrl (BCH40) . DC-DC converters and linear regulators supply cores and all internal logic Security Ctrl MIPI CSI2 LP-DDR2, DDR3 / LV-DDR3 . Temperature monitor for smart performance control Secure RTC 24-bit RGB, LVDS (x3-8) x32/64, 533 MHz − Expansion port support via PCIe 2.0 eFuses 20-bit CSI − Car network: 2xCAN, MLB150 with DTCP, 1Gb Ethernet with IEEE1588 Updated from i.MX53

Secure Real Time Clock SRTC SNVS

External memory (EMI Watermark) External memory (TZASC) Hardware Firewalls On-chip peripherals (CSU) On-chip peripherals (CSU) Secure JTAG Full or Controlled Disable (3 modes) Full or Controlled Disable (3 modes)

Tamper Input GPIO Tamper Input GPIO Physical Tamper Detection Tamper Response (SCCv2) Tamper Response (SNVS)

Device Configuration Open, Closed Open, Closed, Field Return Peripheral DMA access control (CSU) Peripheral DMA access control (CSU) Memory DMA access control (EMI) Memory DMA access control (ARM TZASC) TrustZone Support Interrupt separation (TZIC) Interrupt separation (ARM GIC) Secure storage separation (SCCv2) Secure storage separation (CAAM/SNVS) Cryptographic separation (SAHARA) Cryptographic separation (CAAM)

Secure JTAG MMC 4.4 / SD 3.0 x3 • Specifications CPU Platform • CPU: i.MX 6Quad 4x Cortex-A9 @1.2 GHz, 12000 DMIPS PLL, Osc MMC 4.4 / SDXC • i.MX 6Dual 2x Cortex-A9 @1.2 GHz, 6000 DMIPS Clock & Reset Dual / Quad Cortex-A9 UART x5, 5Mbps • Process: 40nm Smart DMA • Core Voltage: 1.1V 32KB I-cache 32KB D-cache I2C x3, SPI x5 IOMUX per core per core • Package: 21x21 0.8mm Flip-chip BGA 2 Timer x3 ESAI, I S/SSI x3 • 12x12 PoP (LP-DDR2, NAND) NEON PTM per core per core PWM x4 3.3V GPIO Watch Dog x2 • Key Features and Advantages 1MB L2-cache + VFPv3 Keypad • Multi-core architecture for high performance, 1MB L2 cache Power Mgmt S-ATA & PHY 3Gbps • 64-bit LP-DDR2, DDR3 and raw / managed NAND Multimedia • S-ATA 3Gbps interface (SSD / HDD) Power Supplies USB2 OTG & PHY Graphics: OpenGL/ES 2.x, USB2 Host & PHY • Delivers rich graphics and UI in HW Temp Monitor OpenCL/EP, OpenVG 1.x • OpenGL/ES 2.x 3D accelerator with OpenCL EP support USB2 HSIC Host x2 and OpenVG 1.1 acceleration Video Codecs: 1080p30 MIPI HSI • Drives high resolution video in HW Internal Memory Audio: ASRC • Multi-format HD1080 video decode and encode ROM S/PDIF Tx/Rx • 1080p60 decode, 720p60 encode 2x Imaging Processing Unit • High quality video processing (resizing, de-interlacing, etc.) RAM PCIe 2.0 (1-lane) Resizing & Blending • Flexible display support Inversion / Rotation FlexCAN x2 • Four simultaneous: 2x Parallel, 2x LVDS, MIPI-DSI, or HDMI Security Image Enhancement MLB150 + DTCP • Dual display up to WUXGA (1920x1200) and HD1080 RNG • MIPI-CSI2 and HSI LCD & Camera Interface 1Gb Ethernet + IEEE1588 • Increased analog integration simplifies system design and reduces TrustZone HDMI & PHY BOM Ciphers MIPI DSI NAND Ctrl (BCH40) • DC-DC converters and linear regulators supply cores and all internal logic Security Ctrl MIPI CSI2 LP-DDR2, DDR3 / LV-DDR3 • Temperature monitor for smart performance control Secure RTC 24-bit RGB, LVDS (x3-8) x32/64, 533 MHz • Expansion port support via PCIe 2.0 eFuses 20-bit CSI • Car network: 2xCAN, MLB150 with DTCP, 1Gb Ethernet with IEEE1588 Updated from i.MX53

HS to Cellular, WLAN/WiFI/BT . Up to 6 EIM CS (were 4 in iMX53) Host2 IC-USB or/and HUB . 1.65 … 3.6V IO supply range . Bootable

HS Host2 To external Memory Card IC-USB • SATA • SATA 2.5 specification compliant and SATA SATA To HDD/SSD Host PHY AHCI 1.1 compliant Serial ATA Bus Adapter and internal 1 x PHY, up to 3Gbps 10/100/1000 operations Ethernet PHY IEEE1588 • Bootable AVB

PCIe PCIe x1 PCIe – PHY Root/Endpoint System extension port

WEIM SRAM, NOR, OneNAND . Host1- with HS/FS/LS PHY, • Host2 and Host 3 - HS IC-USB (480 Mb/s) To OTG OTG PHY connector • Ethernet Controller (FEC) HUB Host1 PHY (USB2524) 10/100/1000:

− Support SNI, MII, RMII and RGMII interfaces HS to Cellular, WLAN/WiFI/BT Host2 to an external PHY. IC-USB or/and HUB − 1.65V … 3.6V voltage range and automated

HS selection Host2 To external Memory Card IC-USB − IEEE1588 v2 and Supports Ethernet AVB SATA SATA To HDD/SSD Host PHY

10/100/1000 • PCIe 2.0 Ethernet PHY IEEE1588 AVB − 1 lane, 5 Gbps with integrated x1 PHY

PCIe PCIe x1 PCIe – PHY Root/Endpoint System extension port

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a TM 47 Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. • eCSPI/CSPI – one CSPI and two eCSPI ports, same as in • PWM - same as in i.MX53 i.MX53 • Two pulse-width modulators (PWM): 16-bit • Keypad – almost same as in i.MX53. 8x8 matrix resolution and a 4x16 data FIFO supported. (6 x 6 – ―maim‖ configuration, but all pads are • SDMA - same as in i.MX53. Two external SDMA events shared with other interfaces). External keypad controller • Interrupts - same as in i.MX53. considered for Netbook applications • I2C – • One-wire – same as in i.MX53 One wire EEPROM and • Three I2C ports compatible with I2C specifications battery connection. Dallas DS2205 compatible. v2.1 (all up to 400Kb/s) • UART: • GPIO: • High speed (up to 4MHz) – covers TIA/EIA-232-F • All multifunctional digital pads have the GPIO Standard functionality – Total number of GPIOs 224 • 3 ports, one of them can operate as 8 pins full UART, • The GPIO supports up to 32 interrupts: DCE and DTE modes. Other are four-wire • programmable active interrupt edges/level • IrDA 1.0 of external signal • SIR protocol support (115.2kbps or lower) • All of multifunctional (muxed) IOPADs are GPIO capable • 32 bytes FIFOs for transmitter and receiver, and could be programmed independently autobaud. • Most of GPIO capable pads are of UHVIO type - 1.65 … • 9 bit mode supported 3.6 V operational range with automated voltage range • RS-485 mode supported selection • GPT - same as in i.MX53 • Default state for most of GPIO capable pads: • Two general purpose timers, each of them is a 32-bit • GPIO ―free-running‖ or ―set and forget‖ mode timer. • Input o External/Internal clock selectable • Weak PU or PD o External/Internal event interval capturing That was done to avoid on-board contentions in o Programmable output logic, external output default state after reset. signal, ARM interrupt.

• Expansion Devices − SD/eSD/SDXC/MMC/eMMC − I2C − SPI

• Serial Downloader − USB (using USB OTG)

• Plug-in mode − For custom / user-defined boot

Fast DDR 8-bit (1)(2) 66 50MHz, SDR(1)(2) 63 Normal DDR 8-bit(1)(2) 90 100MHz, DDR, theoretical(1)(2) 34 Normal DDR 4-bit(1)(2) 90 1 MByte Normal SDR 8-bit(1)(2) 90 NOR, 16-bit [ms] Normal SDR 4-bit(1)(2) 103 ASYNC/SYNC InPlace(1)(3) 4 50ms with HAB SYNC DDR(1)(2) 110

Notes: 1. The boot time cannot be directly scaled to other code size as it includes not scalable initialization part. 2. HAB: Add 30ms for 1MByte (11.9ms + 1MByte * 16.7us/KByte) 3. HAB: Add 46ms for 1Mbyte (18.9ms + 1MByte * 27.3us/KByte)

• Two keys are used for encryption: − OEM Key is used for program image encryption. . This enables using same program image for all devices. − CAAM Key (per device) is used for OEM Key encryption. . The encrypted OEM Key is attached to image. . Post-production updates: • If no change in OEM Key – just a regular update of image, without update of stored encrypted OEM Key. • If OEM Key changes - update must be done using secure channel with OEM server, or in OEM Service Lab

Automotive i.MX6 Quad 21x21 FC BGA 0.8mm • 25x25 ball matrix, fully populated Consumer

Automotive i.MX6 Dual 21x21 FC BGA 0.8mm • 25x25 ball matrix, fully populated Consumer

• LPDDR2 2xCh/1xCh 32-bit. Compatible Pin i.MX6 Dual 12x12 PoP FC BGA 0.4mm Consumer • 29x29 ball matrix, partially populated

Tentative calculations (based on Micron POD’s): Max Total heights - 2 die in PoP top – 1.45 max ( .350 top mold cap) with Top memories

• Coplanarity <= 100um Requirements • Warpage <= 70um

• All external supply rails could be shared with system components

• Two stage power conversion: external DCDC pre-regulation, integrated LDOs (incl. DVS) • Total system level power delivery efficiency (including linear regulators) is similar to typical DCDC based PMU • 90% or better in high power mode with internally bypassed FET • Better than 65% in low power modes

• Lowest BoM – no multiple inductors, few external capacitors, • System level: low cost PMIC or few discrete DCDC • Maximal flexibility in power management system design

− Power up sequence and defaults is ―closed‖ inside the chip − System level power management – simple and cheap off-shelf components could be used for system design − Simple and fast interface with external PMIC / discrete – on/off only − HW dependent components of power management driver could be placed in ROM. Only standardized API could be exposed outside (to OS)

 System complexity reduction

 System BoM reduction - no multiple inductors, just few external (or on- package) capacitors

 Expecting 3% power saving in high load applications, due to better IR Drop compensation and optimized power distribution

 Power up / Power Down Sequencing: No special requirements!

Cortex A8. ARMv7, Kernel Enhancements, Low Level Initialization code Trustzone, Dual/Quad core Cortex A9. ARMv7. Performance Tuning for dual /Quad core. Updates to 32KB I/D L1 cache. 32KB I/D L1 cache drivers for multicore operation. Cores 256KB L2 cache. 1MB L2 Cache All is encapsulated within Freescale BSP. Single Core Multithreaded applications will benefit the most from multicore design.

L2 Cache 256K L2 Cache 1MB L2 Cache Minor changes to L2-$ flush routines.

General Purpose SIMD Neon, VFP Neon, VFP No changes

Internal SRAM 256KB SRAM 256KB SRAM Minor addressing changes for memory map.

Security MX5x Baseline Same + NIST-approved RNG, TZ ASC 380 Minor updates. Uses same block

Most updates are transparent to software or encapsulated in freescale BSP. LPDDR2 controller LPDDR2, DDR2, single Dual channel LPDDR2 and 64bit single SDRAM Memory Interface for example, automatically balances memory channel channel DDR3/LV-DDR3 storage between 2 channels with zero software intervention or required knowledge.

Same NAND controller but adds 40-bit ECC Minor changes to driver to account for higher ECC NAND Controller Baseline and additional CS bit correction

WEIM controller Baseline Same controller with additional chipselect Minor changes to account for additional chip select

Memory map updated for more SDRAM OEMAddressTable in OAL or low level kernel. System Memory Map Baseline space and new peripherals Encapsulated in Freescale BSP

Interrupt Handler changes. Will work seamlessly INTC Baseline New INTC for 2 to 4 processors with single core. Encapsulated in Freescale BSP

Same AXI but use dual 64-bit AXI ports AXI Fabric AXI fabric Transparent to OS from core complex and run at higher speed

3D: AMD Z430 - 33 MTri/s, 3D: Vivante GC2000 200 Mpxl/s 200 MTri/s, 1000 Mpxl/s Freescale will provide drivers for OpenGL, OpenVG. OpenGL|ES 2.0| OpenGL|ES 2.x, OpenCL|EP 1.1 2D Graphics/3D Graphics If software on i.MX53 is using OpenGL ES 2.0, 2D: Vivante GC320: 600Mpxl/s, BLIT OpenVG, then no changes on customer’s part 2D: AMD Z160: 200 Mpxl/s, VG: Vivante GC355: 300Mpxl/s, OpenVG OpenVG 1.1 1.1

Same mechanism of accessing IPU. Changes to display driver to handle communication to new LCD Dual IPU (same version) with support for Single IPU with support for interfaces like HDM I 1.4. Provided in Freescale LCD dual LVDS, parallel, MIPI DSI and HMDI LVDS, parallel display BSP. Customer can use dual IPU’s for more v1.4 enhanced layering of overlays vs i.MX53. Current software will be the same.

If using industry standard APIs then no real changes Baseline VPU with support for Updated VPU from same IP provider with support for at app level to communicate with the VPU. If new VPU 1080p 1080p high profile, 3D video decode, VP8 codec codec implemented, need to Integrate with DirectShow or GStreamer

No changes except selection option of using MIPI Camera Interface and Types: 2x 20-bit parallel Same Controller + MIPI-CSI-2 (4lanes) with three CSI sensors. Driver for MIPI CSI encapsulated in Controller simultaneous inputs. Two simultaneous inputs Freescale BSP

UART, I2C, I2S, Watchdog, PWM, SPDIF, Keypad, Timers, UART, APB peripheral Same, units, no changes Freescale porting drivers with minimal changes SmartDMA and other APB peripherals

Adding USB HSIC physical layer driver to BSP USB 2.0 Host, USB 12 pin USB Add USB HSIC (encapsulated in Freescale BSP). HSIC seen as just ulpi, USB OTG 2.0 another USB Port by upper layers.

Four SD/SDIO/MM Card New Driver for SD 3.0/SDXC. Encapsulated in SD/MMC/SDIO Interfaces supporting mmc Add support for SDXC, MMC 4.4 Freescale BSP 4.1, SD 2.0

GPIO and Peripheral Minimal changes to underlying configuration code to GPIO and ALT Functions Updated pin mux, alt functions Devices Registers ensure proper pin mux chosen.

Updated drivers to take advantage of ESAI port . No Audio Baseline Additional # of I2S ports + ESSAI peripheral changes by customer since encapsulated in Freescale BSP.

Standard Cortex A8 PMU, Performance Monitoring ASSP Registers, Events, Updated counters for Cortex A9 and multicore Encapsulated in Freescale BSP Unit Interrupt based

Minor changes due to new peripherals on tustzone Trust Boot Trusted Boot with Trustzone Same list

Bootrom support for USB, Freescale will change this but it is just boot routines BootROM Same + additional bootsource requirements. NAND, NOR , SD/MMC. used by customer.

Additional driver for HSI and HSIC but these are AP – CP Interface USB, UART, SPI, SD IO. Same + MIPI HSI, USB HSIC provided by Freescale.

If not using P-SATA then no change. SATA-II is same SATA, P-Sata P-SATA, SATA II – 1.5Gbps P-SATA dropped. SATA II at 3Gbps IP but runs at 2X bandwidth than i.MX 53

If not using ethernet, no changes. If using ethernet, Ethernet 10/100 Ethernet , IEEE 1588 Gigabit Ethernet, IEEE 1588 IP is same IP source but enhanced for Gigabit. Encapsulated in Freescale driver.