ISP1761 Hi-Speed Universal Serial Bus On-The-Go Controller Rev
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ISP1761 Hi-Speed Universal Serial Bus On-The-Go controller Rev. 04 — 5 March 2007 Product data sheet 1. General description The ISP1761 is a single-chip Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG) Controller integrated with advanced NXP slave Host Controller and the NXP ISP1582 Peripheral Controller. The Hi-Speed USB Host Controller and Peripheral Controller comply to Ref. 1 “Universal Serial Bus Specification Rev. 2.0” and support data transfer speeds of up to 480 Mbit/s. The Enhanced Host Controller Interface (EHCI) core implemented in the Host Controller is adapted from Ref. 2 “Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0”. The OTG Controller adheres to Ref. 3 “On-The-Go Supplement to the USB Specification Rev. 1.2”. The ISP1761 has three USB ports. Port 1 can be configured to function as a downstream port, an upstream port or an OTG port; ports 2 and 3 are always configured as downstream ports. The OTG port can switch its role from host to peripheral, and peripheral to host. The OTG port can become a host through the Host Negotiation Protocol (HNP) as specified in the OTG supplement. 2. Features n Compliant with Ref. 1 “Universal Serial Bus Specification Rev. 2.0”; supporting data transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) n Integrated Transaction Translator (TT) for Original USB (full-speed and low-speed) peripheral support n Three USB ports that support three operational modes: u Mode 1: Port 1 is an OTG Controller port, and ports 2 and 3 are Host Controller ports u Mode 2: Ports 1, 2 and 3 are Host Controller ports u Mode 3: Port 1 is a Peripheral Controller port, and ports 2 and 3 are Host Controller ports n Supports OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) n Multitasking support with virtual segmentation feature (up to four banks) n High-speed memory controller (variable latency and SRAM external interface) n Directly addressable memory architecture n Generic processor interface to most CPUs, such as Hitachi SH-3 and SH-4, NXP XA, Intel StrongARM, NEC and Toshiba MIPS, Freescale DragonBall and PowerPC Reduced Instruction Set Computer (RISC) processors n Configurable 32-bit and 16-bit external memory data bus n Supports Programmed I/O (PIO) and Direct Memory Access (DMA) n Slave DMA implementation on CPU interface to reduce the host system’s CPU load NXP Semiconductors ISP1761 Hi-Speed USB OTG controller n Separate IRQ, DREQ and DACK lines for the Host Controller and the Peripheral Controller n Integrated multi-configuration FIFO n Double-buffering scheme increases throughput and facilitates real-time data transfer n Integrated Phase-Locked Loop (PLL) with external 12 MHz crystal for low EMI n Tolerant I/O for low voltage CPU interface (1.65 V to 3.3 V) n 3.3 V-to-5.0 V external power supply input n Integrated 5.0 V-to-1.8 V or 3.3 V-to-1.8 V voltage regulator (internal 1.8 V for low-power core) n Internal power-on reset or low-voltage reset and block-dedicated software reset n Supports suspend and remote wake-up n Built-in overcurrent circuitry (analog overcurrent protection) n Hybrid-power mode: VCC(5V0) (can be switched off), VCC(I/O) (permanent) n Target total current consumption: u Normal operation; one port in high-speed active: ICC < 100 mA when the internal charge pump is not used u Suspend mode: ICC(susp) < 150 µA at room temperature n Available in LQFP128 and TFBGA128 packages n Host Controller-specific features u High performance USB host with integrated Hi-Speed USB transceivers; supports high-speed, full-speed and low-speed u EHCI core is adapted from Ref. 2 “Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0” u Configurable power management u Integrated TT for Original USB peripheral support on all three ports u Integrated 64 kB high-speed memory (internally organized as 8 k × 64 bit) u Additional 2.5 kB separate memory for TT u Individual or global overcurrent protection with built-in sense circuits u Built-in overcurrent circuitry (digital or analog overcurrent protection) n OTG Controller-specific features u OTG transceiver: fully integrated; adheres to Ref. 3 “On-The-Go Supplement to the USB Specification Rev. 1.2” u Supports HNP and SRP for OTG dual-role devices u HNP: status and control registers for software implementation u SRP: status and control registers for software implementation u Programmable timers with high resolution (0.01 ms to 80 ms) for HNP and SRP u Supports external source of VBUS n Peripheral Controller-specific features u High-performance USB Peripheral Controller with integrated Serial Interface Engine (SIE), FIFO memory and transceiver u Complies with Ref. 1 “Universal Serial Bus Specification Rev. 2.0” and most device class specifications u Supports auto Hi-Speed USB mode discovery and Original USB fallback capabilities u Supports high-speed and full-speed on the Peripheral Controller u Bus-powered or self-powered capability with suspend mode ISP1761_4 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 04 — 5 March 2007 2 of 163 NXP Semiconductors ISP1761 Hi-Speed USB OTG controller u Slave DMA, fully autonomous and supports multiple configurations u Seven IN endpoints, seven OUT endpoints and one fixed control IN and OUT endpoint u Integrated 8 kB memory u Software-controllable connection to the USB bus, SoftConnect 3. Applications The ISP1761 can be used to implement a dual-role USB device in any application, USB host or USB peripheral, depending on the cable connection. If the dual-role device is connected to a typical USB peripheral, it behaves like a typical USB host. The dual-role device can also be connected to a PC or any other USB host and behave like a typical USB peripheral. 3.1 Host/peripheral roles n Mobile phone to/from: u Mobile phone: exchange contact information u Digital still camera: e-mail pictures or upload pictures to the web u MP3 player: upload/download/broadcast music u Mass storage: upload/download files u Scanner: scan business cards n Digital still camera to/from: u Digital still camera: exchange pictures u Mobile phone: e-mail pictures, upload pictures to the web u Printer: print pictures u Mass storage: store pictures n Printer to/from: u Digital still camera: print pictures u Scanner: print scanned image u Mass storage: print files stored in a device n MP3 player to/from: u MP3 player: exchange songs u Mass storage: upload/download songs n Oscilloscope to/from: u Printer: print screen image n Personal digital assistant to/from: u Personal digital assistant: exchange files u Printer: print files u Mobile phone: upload/download files u MP3 player: upload/download songs u Scanner: scan pictures u Mass storage: upload/download files u Global Positioning System (GPS): obtain directions, mapping information u Digital still camera: upload pictures u Oscilloscope: configure oscilloscope ISP1761_4 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 04 — 5 March 2007 3 of 163 NXP Semiconductors ISP1761 Hi-Speed USB OTG controller 4. Ordering information Table 1. Ordering information Type number Package Name Description Version ISP1761BE LQFP128 plastic low profile quad flat package; 128 leads; body 14 × 20 × 1.4 mm SOT425-1 ISP1761ET TFBGA128 plastic thin fine-pitch ball grid array package; 128 balls; body 9 × 9 × 0.8 mm SOT857-1 ISP1761_4 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 04 — 5 March 2007 4 of 163 NXP Semiconductors ISP1761 Hi-Speed USB OTG controller 5. Block diagram VCC(I/O) 37 to 39, 41 to 43, 10, 40, 48, 59, 67, 45 to 47, 49, 51, 75, 83, 94, 104, 115 52, 54, 56 to 58, 11 60 to 62, 64 to 66, ISP1761BE XTAL1 68 to 70, 72 to 74, PLL 12 76 to 78, 80 XTAL2 30 MHz 13 D[15:0]/D[31:0] SEL16/32 CLKIN 60 MHz 82, 84, 86, 87, HC PTD 89, 91 to 93, MEMORY 95 to 98, 122 BUS INTERFACE: (3 kB) RESET_N 17 100 to 103, 105 HC PAYLOAD DC BUFFER GLOBAL CONTROL A[17:1] MEMORY 119 HC_SUSPEND/ MANAGEMENT MEMORY MEMORY AND POWER CS_N 106 WAKEUP_N UNIT (60 kB) 8 KBYTES MANAGEMENT RD_N 107 120 + DC_SUSPEND/ WR_N 108 WAKEUP_N SLAVE DMA DC_IRQ 111 CONTROLLER HC_IRQ 112 + DC_DREQ 113 POWER-ON 110 GENERIC PROCESSOR BUS INTERRUPT MEMORY ARBITER RESET AND BAT_ON_N HC_DREQ 114 CONTROL AND FIFO V ON HC_DACK 116 BAT DC_DACK 117 5, 50, REGISTERS 85, 118 SUPPORT 5 V-TO-1.8 V REG1V8 ADVANCED VOLTAGE ADVANCED 6, 7 NXP REGULATOR PERIPHERAL VCC(5V0) 124 SLAVE HOST C_B CONTROLLER TRANSACTION CONTROLLER 125 C_A CHARGE TRANSLATOR PUMP 5 V-TO-3.3 V V 126 (TT) AND RAM CC(C_IN) VOLTAGE 9 REGULATOR REG3V3 OTG CONTROLLER DIGITAL 2 AND ANALOG REF5V DYNAMIC PORT ROUTING AND PORT CONTROL LOGIC OVERCURRENT PROTECTION 8 3 GND(OSC) ID 4, 17, 24, HI-SPEED HI-SPEED HI-SPEED 31, 123 USB ATX1 USB ATX2 USB ATX3 GNDA 53, 88, 121 GNDC 14, 36, 44, 55, 63, 71, 79, 90, 99, 109 16 15 20 19 18 21 127 23 22 27 26 25 28 128 30 29 34 33 32 35 1 004aaa450 RREF1 DP1 DM1 RREF2 DP2 DM2 RREF3 DP3 DM3 GNDD GND GNDA OC1_N/ GND GNDA OC2_N GND GNDA OC3_N (RREF1) VBUS (RREF2) (RREF3) PSW1_N PSW2_N PSW3_N The figure shows the LQFP pinout.