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Verfahren Zum Auslesen Von Speicherzellen Mit Unterschiedlichen

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Verfahren Zum Auslesen Von Speicherzellen Mit Unterschiedlichen (19) *DE102012108545A120130404* (10) DE 10 2012 108 545 A1 2013.04.04 (12) Offenlegungsschrift (21) Aktenzeichen: 10 2012 108 545.5 (51) Int Cl.: G11C 16/26 (2013.01) (22) Anmeldetag: 13.09.2012 (43) Offenlegungstag: 04.04.2013 (30) Unionspriorität: (74) Vertreter: 10-2011-0098809 29.09.2011 KR Kuhnen & Wacker Patent- und Rechtsanwaltsbüro, 85354, Freising, DE (71) Anmelder: Samsung Electronics Co., Ltd., Suwon City, (72) Erfinder: Kyungki, KR Joo, Sang-Hyun, Gyeonggi-do, KR; Song, Kiwhan, Seoul, KR; Lee, Ju Seok, Seoul, KR; Choi, Kiwhan, Gyeonggi-do, KR Die folgenden Angaben sind den vom Anmelder eingereichten Unterlagen entnommen (54) Bezeichnung: Verfahren zum Auslesen von Speicherzellen mit unterschiedlichen Schwellwertspannungen ohne Änderung der Wortleitungsspannung, sowie nicht-flüchtige Speichervorrichtung, die dieses verwendet (57) Zusammenfassung: Ein Soft-Decision-Leseverfahren einer nichtflüchtigen Speichervorrichtung enthält Empfan- gen eines Soft-Decision-Lesebefehls, Anlegen einer Lese- spannung (Vwl2), eine ausgewählte Wortleitung (WL), Vorla- den von Bitleitungen (BL), die jeweils mit ausgewählten Spei- cherzellen (A, B, C) der ausgewählten Wortleitung (WL) ver- bunden sind, kontinuierliches Abtasten von Zuständen der ausgewählten Speicherzellen (A, B, C). Die vorgeladenen Spannungen der Bitleitungen (BL) und die an die ausgewähl- te Wortleitung (WL) gelieferte Lesespannung (Vwl2) werden nicht variiert während des Abtasten von Zuständen der aus- gewählten Speicherzellen (A, B, C). DE 10 2012 108 545 A1 2013.04.04 Beschreibung QUERVERWEIS AUF VERWANDTE ANMELDUNG [0001] Es wird die Priorität der am 29. September 2011 eingereichten koreanischen Patentanmeldung, deren Gesamtheit hierin durch Inbezugnahme aufgenommen wird, beansprucht gemäß 35 U. S. C § 119. HINTERGRUND [0002] Beispielhafte Ausführungsformen beziehen sich auf nichtflüchtige Speichervorrichtungen mit Speicher- zellen, die jeweils eine variable Schwellwertspannung besitzen. [0003] Halbleiterspeicher werden angesehen als die vielleicht grundlegendsten mikroelektronischen Kompo- nenten eines digitalen logischen Systementwurfs, wie z. B. von Computer und Mikroprozessor-basierenden Anwendungen, die von Satelliten bis zu Unterhaltungselektronik reichen. Daher helfen Fortschritte bei der Herstellung von Halbleiterspeichern einschließlich Verfahrensverbesserungen und Technologieentwicklungen durch Skalieren für höhere Dichten und höhere Geschwindigkeiten, Leistungsstandards für andere digitale Logikfamilien zu etablieren. [0004] Halbleiterspeichervorrichtungen schließen zum Beispiel flüchtige Schreib-Lese-Speicher (RAMs) und nichtflüchtige Speichervorrichtungen mit ein. In dem Fall der flüchtigen RAMs wird Logikinformation typischer- weise gespeichert entweder durch Festlegen des Logikzustands eines bistabilen Flip-Flops, wie z. B. bei einem statischen Schreib-Lese-Speicher (SRAM), oder durch Aufladen eines Kondensators wie bei einem dynami- schen Schreib-Lese-Speicher (ERAM). In beiden Fällen werden Daten gespeichert und können ausgelesen werden solange Strom angelegt ist, und gehen verloren, wenn die Spannungsversorgung ausgeschaltet wird; daher fallen sie in die Kategorie der flüchtigen Speicher. [0005] Nichtflüchtige Speicher, wie z. B. ein maskenprogrammierter Nur-Lese-Speicher (MROM), ein pro- grammierbarer Nur-Lese-Speicher (PROM), ein löschbarer programmierbarer Nur-Lese-Speicher (EPROM) und ein elektrisch löschbarer programmierbarer Nur-Lese-Speicher (EEPROM) sind in der Lage, gespeicherte Daten zu halten, selbst wenn die Spannungsversorgung abgeschaltet wird. Das Datenspeicherverfahren des nichtflüchtigen Speichers kann permanent oder umprogrammierbar sein in Abhängigkeit von der verwende- ten Herstellungstechnologie. Nichtflüchtige Speicher werden verwendet für Programm- und Mikrocode-Spei- cher bei einer Vielzahl von Anwendungen in der Computer-, der Luftfahrtelektronik-, der Telekommunikations- und der Unterhaltungselektronikindustrie. Eine Kombination von flüchtigen und nichtflüchtigen Einzelchip-Spei- cherbetriebsarten ist außerdem verfügbar bei Vorrichtungen wie z. B. einem nichtflüchtigen SRAM (nvSRAM) zur Verwendung in Systemen, die einen schnellen, programmierbaren nichtflüchtigen Speicher erfordern. Zu- sätzlich haben sich dutzende von speziellen Speicherarchitekturen herausgebildet, die irgendeine zusätzliche Logikschaltung enthalten zum Optimieren ihrer Leistungsfähigkeit für anwendungsspezifische Aufgaben. [0006] In nichtflüchtigen Speichern können jedoch ein MROM, ein PROM und ein EPROM nicht von einem System selbst gelöscht und beschrieben werden, so dass es nicht einfach ist für einen üblichen Benutzer, gespeicherte Inhalte zu aktualisieren. Andererseits kann ein EEPROM elektrisch gelöscht oder beschrieben werden. Die Anwendung des EEPROM hat sich erweitert auf einen Hilfsspeicher oder auf Systemprogrammie- rung, bei denen kontinuierliche Aktualisierungen benötigt werden (z. B. Flash-EEPROM). KURZFASSUNG [0007] Ein Aspekt von Ausführungsformen des erfinderischen Konzepts ist gerichtet auf ein Soft-Decisi- on-Ausleseverfahren einer nichtflüchtigen Speichervorrichtung. Das Soft-Decision-Ausleseverfahren umfasst Empfangen eines Soft-Decision-Auslesebefehls; Anlegen einer Lesespannung an eine ausgewählte Wortlei- tung, Vorladen von Bitleitungen, die jeweils mit ausgewählten Speicherzellen der ausgewählten Wortleitung verbunden sind; und kontinuierliches Abtasten von Zuständen der ausgewählten Speicherzellen, wobei die vorgeladenen Spannungen der Bitleitungen und die an die ausgewählte Wortleitung angelegte Lesespannung nicht variiert werden während des Abtastens von Zuständen der ausgewählten Speicherzellen. [0008] Ein weiterer Aspekt von Ausführungsformen des erfinderischen Konzepts ist gerichtet auf eine nicht- flüchtige Speichervorrichtung mit einem Speicherzellenarray mit Speicherzellen, die an Kreuzungspunkten von Wortleitungen und Bitleitungen angeordnet sind; einer Zeilenauswahlschaltung, die konfiguriert ist zum Treiben einer ausgewählten von den Wortleitungen; und einer Lese/Schreib-Schaltung mit Speicherseitenpuffern, die 2/52 DE 10 2012 108 545 A1 2013.04.04 jeweils mit den Bitleitungen verbunden sind; und einer Steuerlogik, die konfiguriert ist zum Steuern der Lese/ Schreib-Schaltung und der Zeilenauswahlschaltung, wobei die Steuerlogik eine Soft-Decision-Ausleseopera- tion steuert, bei der Bitleitungen, die jeweils mit ausgewählten Speicherzellen einer ausgewählten Wortleitung verbunden sind, die mit einer Lesespannung versorgt ist, vorgeladen werden und Spannungen von jeweils den Bitleitungen entsprechenden Abtastknoten zumindest zweimal, als erste Daten und zweite Daten, festgehalten werden, während die vorgeladenen Spannungen der Bitleitungen und eine an die ausgewählte Wortleitung angelegte Lesespannung nicht variiert werden; und wobei die Steuerlogik variabel jeweilige Entwicklungszei- ten der kontinuierlichen Abtastoperationen der Leseoperation steuert. KURZE BESCHREIBUNG DER FIGUREN [0009] Die obigen und andere Aufgaben und Merkmale werden anschaulich anhand der Beschreibung, die mit Bezug auf die begleitenden Zeichnungen folgt, wobei sich in den verschiedenen Figuren durchgehend gleiche Bezugsziffern auf gleiche Teile beziehen außer es ist anders spezifiziert. [0010] Fig. 1 ist ein Diagramm zum Beschreiben eines Ausleseverfahrens einer nichtflüchtigen Speichervor- richtung gemäß einer Ausführungsform des erfinderischen Konzepts. [0011] Fig. 2 ist ein Blockschaltplan, der schematisch eine nichtflüchtige Speichervorrichtung gemäß einer Ausführungsform des erfinderischen Konzepts darstellt. [0012] Fig. 3 ist ein Diagramm, das schematisch ein Speicherzellenarray mit einer All-Bit-Line-Speicherarchi- tektur oder einer Odd-Even-Speicherarchitektur darstellt. [0013] Fig. 4 ist ein Blockschaltplan, der schematisch einen Speicherseitenpuffer gemäß einer Ausführungs- form des erfinderischen Konzepts darstellt. [0014] Fig. 5 ist ein Diagramm, das Schwellwertspannungsverteilungen einer nichtflüchtigen Speichervorrich- tung darstellt, die 2-Bit-Daten pro Zelle speichert. [0015] Fig. 6 ist ein Diagramm zum Beschreiben eines Programmierverfahrens einer nichtflüchtigen Speicher- vorrichtung gemäß einer Ausführungsform des erfinderischen Konzepts. [0016] Fig. 7 ist ein Zeitablaufdiagramm zum Beschreiben einer Verifikationsoperation einer nichtflüchtigen Speichervorrichtung gemäß einer Ausführungsform des erfinderischen Konzepts. [0017] Fig. 8 ist ein Blockschaltplan, der schematisch eine nichtflüchtige Speichervorrichtung gemäß einer weiteren Ausführungsform des erfinderischen Konzepts darstellt. [0018] Fig. 9 ist ein Diagramm, das schematisch einen Booster in Fig. 8 gemäß einer Ausführungsform des erfinderischen Konzepts darstellt. [0019] Fig. 10 ist ein Diagramm zum Beschreiben eines Programmierverfahrens einer nichtflüchtigen Spei- chervorrichtung gemäß einer weiteren Ausführungsform des erfinderischen Konzepts. [0020] Fig. 11 ist ein Zeitablaufdiagramm zum Beschreiben einer Verifikationsoperation einer nichtflüchtigen Speichervorrichtung gemäß einer weiteren Ausführungsform des erfinderischen Konzepts. [0021] Fig. 12 ist ein Diagramm zum Beschreiben eines Programmierverfahrens zum Verringern von Wort- leitungskopplung. [0022] Fig. 13 ist ein Diagramm, das die mit Speicherzellen einer n-ten Wortleitung verknüpften Schwell- wertspannungsverteilungen darstellt bevor und nachdem Wortleitungskopplung verursacht wird beim Program- mieren von Speicherzellen einer (n + 1)-ten Wortleitung. [0023] Fig. 14 ist ein Diagramm, das alle
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