An I/O System on a Chip

An I/O System on a Chip The heart of the I/O subsystem for the HP 9000 Model 712 workstation is a custom VLSI chip that is optimized to minimize the manufacturing cost of the system while maintaining functional compatibility and comparable performance with existing members of the Series 700 family. by Thomas V. Spencer, Frank J. Lettang, Curtis R. McAllister, Anthony L. Riccio, Joseph F. Orth, and Brian K. Arnold The HP 9000 Model 712 design is based on threeOther custom I/O functionality that is completely implemented on pieces of VLSI that provide much of the system'sLASI functionalĆ with HP internal designs includes: RSĆ232, Centronics ity: CPU, graphics, and I/O. These chips communicateparallel via interface, a a batteryĆbacked realĆtime clock, and two highĆperformance local bus referred to as GSC (generalPS/2Ćstyle sysĆ keyboard and mouse ports. In addition, LASI proĆ tem connect). This paper will focus primarily on thevides I/O a chip. very simple way of connecting the WD37C65C flexĆ ible disk controller chip to the GSC bus. The system boot A major goal of the Model 712 I/O subsystem was to proĆ ROMs are also directly controlled by the LASI chip. The vide a superset of the I/O performance and functionality Model 712 provides 16Ćbit CDĆquality audio and optionally available from other family members at a significantly reĆ supports two telephone lines. LASI provides the GSC interĆ duced manufacturing cost. This goal was bounded by the face and clock generation (using digital phaseĆlocked loops) reality of a finite amount of engineering resources, and it for both of these audio functions. Fig. 2 shows an approxiĆ was obvious from the start that integrating several of the I/O mate floor plan of the LASI chip. The floor plan shows the functions onto a single piece of silicon could greatly reduce general layout and relative size of each block. the total I/O subsystem manufacturing cost. Each function of the I/O subsystem was examined individually as aLASI candidate contains several system functions that help to minimize for integration. The value of maintaining exact driverĆlevelthe miscellaneous logic required in the system. This includes software compatibility was also evaluated with respectGSC to arbitration the and reset control. LASI also serves as the advantages of minimizing the hardware cost for eachGSC of interrupt the controller. I/O functions. It is possible to use up to four LASI chips on the same GSC The investigation indicated that the optimal solutionbus. for LASIthe can be programmed at reset to reside in one of Model 712 was an I/O subsystem that centered aroundfour different a address locations. The arbitration circuit supĆ single piece of custom VLSI. The chip that resultedports from chaining, this and LASI can be programmed to either drive investigation directly implements many of the requiredor I/O receive reset. functions and provides a glueless interface between the GSC bus and other common industry I/O devices. ThisSystem chip was Support Blocks named LASI, which is an acronym that refers toThe the two following sections give a brief overview of each of major pieces of functionality in the chip, LAN andLASI's SCSI. major The functional blocks that provide system support LASI chip also provides several miscellaneous systemfunctionality funcĆ in the Model 712, but do not directly support or tions that further reduce the amount of discrete logicimplement reĆ any I/O function. quired in the system. GSC Interface. The GSC (general system connect) bus conĆ Chip Overview nects the major VLSI components in the Model 712. It is a 32Ćbit bus with multiplexed address and data. The bus conĆ The LASI chip was designedm inm aCMOS 0.8Ć process and sists of 47 signals for devices capable of being a bus master. is 13.2 mm by 12.0 mm in size (including I/O pads). It conĆ The GSC bus is defined to run at up to 40 MHz giving a tains 520,000 FETs and is packaged in a 240Ćpin MQUAD peak transfer rate of 160 Mbytes/s. package. LASI dissipates approximately three watts when operating at the maximum GSC frequency (40 MHz).The LASI GSC interface block in LASI provides the connectivity was designed primarily using standardĆcell design methodolĆbetween the GSC bus and the wide variety of internal bus ogies although several areas required full custom design.blocks, many of which have different logical and timing reĆ quirements. This block converts the GSC bus to a less comĆ A functional block diagram of LASI is shown in Fig. 1. The plex internal LASI bus. The LASI internal bus is very similar majority of circuitry in LASI is consumed by only two funcĆ to the GSC bus, but it is not as heavily multiplexed and is tions, LAN and SCSI. Both of theses designs were purchased more flexible than the GSC bus in that it easily accommoĆ from outside companies and ported to HP's design process. dates the simpler interface for the generalĆpurpose I/O The SCSI functionality is exactly identical to the NCR 53C710 blocks in LASI. The GSC interface block handles bus errors SCSI controller, and the LAN functionality is exactly identical and keeps track of parity information for other internal to an Intel 82C596 LAN controller. 36April 1995 HewlettĆPackard Journal Hewlett-Packard Company 1995 CPU and Graphics LASI (1) Arbitration GSC Bus (1) (1) Phase-Locked General Loop Clock System Connect Generator (GSC) (1) (1,3) Miscellaneous Interrupt Register Controller (3) (2) SCSI Megacell RS-232 (3) (2) PS/2 Keyboard LAN Megacell and Mouse Controller (2,3) (1) Telephony Real-Time Card Parallel Port (Optional) Clock (2,3) (2,3) Flash Audio Audio EPROM Flexible Disk Circuit and Telephone Interface Interface (1) (2) Clock Generator EPROM Flexible and Reset Interface Disk Controller Controller (1) System Support Blocks (2) General I/O Functions (3) Blocks Capable of Initiating Transactions on the GSC Bus. Fig. 1. LASI chip block diagram. blocks, removing the associated complexity from theseA simpleconĆ strobe signal is asserted while internal data and trollers. Both master and slave devices reside on theaddress LASI buses are valid. Internal devices have no direct inĆ internal bus. teraction with bus errors. LASI is a slave whenever the CPU initiates data transfer.As a bus As master, a LASI is capable of initiating subword, word, slave, LASI supports only subword and word write,doubleĆword, and subĆ and quadĆword transactions on the GSC bus. word, word, and doubleĆword reads.* Internal slaveOnce devices one of LASI's internal bus masters owns the bus, it can only need to support a subset of these transactions.signify There the start of a transaction by assertingmaster_valid the are five different protocol behaviors for slave devicessignal in (see Fig. 3). The device must then simultaneously LASI: unpaced byte wide, paced byte wide, packeddrive byte its DMA addressmaster_address ( ), transaction type, and wide, unpaced word wide, and paced word wide. byte enables onto the bus. On a read, the first available data word will appear on the internal busmaster_ac- when the Unpaced devices, such as the realĆtime clock, don't use a knowledge signal is asserted by the GSC interface. The GSC handshake with the GSC interface, making their protocol interface will not accept anothermaster_valid until all the read very simple. When a device requires a variable length of data has been transferred. time to transfer data it is called paced. The SCSI interface is an example of a paced device. A packed deviceIf is a one timeout that error, address parity error, or data parity error is sends a sequence of bytes to make up a wordencountered or double on the GSC bus, the GSC interface will always word. The boot ROM interface is an example ofdo a packed a normal handshake for the transaction by asserting the device. master_acknowledge signal. The transaction will complete as usual except that an error is logged, disabling arbitration for * In PA-RISC a subword is typically one byte, a word is 32 bits, a double word is 64 bits, and the device so it cannot be a bus master again. This means a quad word is 128 bits. Hewlett-Packard Company 1995 April 1995 HewlettĆPackard Journal37 RS-232 Audio PS/2 Intel 82C596 LAN Interface PS/2 Coprocessor External 8-Bit Bus Controller Real- Parallel Time Port LAN Clock Interface Clock Buffer Interrupt Controller NCR 53C710 SCSI SCSI Controller Interface GSC Phase-Locked Phase-Locked Interface Loop Clock Loop Clock Generator Generator Arbitration Fig. 2. LASI floorplan. that internal masters, at the hardware level, nevercontrolled need to by another arbiter. This feature allows LASI to be respond directly to bus errors. When the GSC interfaceused in block larger systems that provide their own arbitration sees a timeout error it will, from the perspectivecircuit. of its A interĆ second LASI can also be used for I/O expansion nal bus blocks, complete a transaction normally. Inin this lowĆend way systems in which the first LASI is providing the the GSC's error signaling mechanism can correctly terminatecentral arbitration. Support for multiple LASI's on the same an errant transaction without adding complexity to LASI'sGSC bus makes the speedy development of multifunction internal blocks. I/O expansion boards a relatively simple task. Parity is generated in the GSC interface wheneverThe LASI LASI design was simplified by requiring that the LASI sources data or an address on the bus. Parity isarbitration checked circuit gain control of the GSC bus before granting whenever LASI is a data sink. LASI does not respondthe internal to bus to potential bus masters. This saved a signifiĆ address parity errors on the GSC bus, which resultcant in amount a of complexity in the GSC interface block as well timeout error.

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