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MIPS Technologies Corporate Updates and MIPS Android

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MIPS Technologies Corporate Updates and MIPS Android MIPS Technologies Corporate Updates and MIPS Android October 2012 1 © 2012 MIPS Technologies, Inc. All rights reserved. MIPS Technologies Corporate Update 2 © 2012 MIPS Technologies, Inc. All rights reserved. MIPS Technologies Corporate Snapshot Business Overview Annual Unit Shipments . A leading provider of industry-standard processor Millions architectures and cores of units per quarter . A leading position in the digital home 800 CAGR 38% . Strong in wired and wireless networking . Growing position in embedded market 700 . Expanding into mobile, with millions of units of smartphones & tablets already shipping 600 500 . IP business model— licensing + royalties 400 . Licensees include Broadcom, Cavium, Loongson, 300 Ingenic, Microchip, MStar, MediaTek, Sony, Toshiba, others 200 . Valuable portfolio of 570+ patent properties worldwide 100 0 . Headquartered in Sunnyvale, CA; presence in 11 countries; approx. 160 employees; more than half in R&D *MIPS royalty units reflect previous quarter shipments . >3.6 billion unit installed base since 2000; 708 million units shipped in FY12 3 © 2012 MIPS Technologies, Inc. All rights reserved. Strategic Growth in Key Market Segments Home Wired/ Mobile Entertainment Wireless Embedded Networking • Use Android & • Maintain leading • Maintain 4G to dislodge position across leadership in • Leverage lead competition the home broadband CPE MCU licensee & WLAN • Make pioneer • Provide leading- • Grow ecosystem customers edge connected • Facilitate & leverage successful TV solutions for PowerPC partnerships Android and Linux transition to MIPS • Performance • Invest in • Help to define • Leverage efficiency connected device new product multicore 64-bit & leadership ecosystem categories multi-threading Maintaining lead in traditional markets; aggressive market expansion 4 © 2012 MIPS Technologies, Inc. All rights reserved. MIPS’ Market Presence Leading Market Share* Digital TV Cable, Satellite & IPTV Set-top Boxes Blu-ray Players Broadband CPE WiFi Access Points and Routers *MIPS and Industry Analyst Data Leading position in home entertainment; Strong in networking; Aggressively expanding into mobile and embedded 5 © 2012 MIPS Technologies, Inc. All rights reserved. Recent MIPS Mobile Milestones Growth in emerging Millions of Breaking MIPS fully Best-in-class markets—new units shipped; tablet price/ supported in Aggressively Cat 4 LTE devices in Mobile is no performance Latest release building the chipsets— China & longer barrier: of Android mobile apps certification in Indonesia; just an 1GHz & NDK from ecosystem progress in evaluations ARM sub-$100 Google for MIPS multiple underway in world countries Brazil and Thailand Mobile momentum continues with new ecosystem developments and new products in the market 6 © 2012 MIPS Technologies, Inc. All rights reserved. The Heritage of the MIPS Architecture Pioneered by Stanford President John Hennessy in the 1980s Pure, fast, efficient, elegant RISC architecture designed for performance Now the architecture of choice for multimedia, home networking & beyond Innovation continues by MIPS and architecture licensees—Broadcom, Cavium, Loongson, Ingenic, Renesas, Toshiba, others Strong patent position with more than 570 patent properties worldwide Photo: In 1984, Stanford computer scientists John Shott, John Hennessy and James D. Meindl brainstorm about the MIPS project (Photo: Chuck Painter) Widely used, widely taught architecture with millions of lines of code written for it 7 © 2012 MIPS Technologies, Inc. All rights reserved. A Systematic Philosophy for Design Success 2012 microMIPS Advanced 2010 Code Compression 2008 Coherent Multiprocessing 2007 Superscalar Performance 2006 Multi-threading DSP Extensions 2005 2002 Microcontroller-specific Cores 2001 Highest Performance, Synthesizable, Licensable 32-bit Cores 1999 MIPS32 and MIPS64 Architectures 1991 Industry’s First 64-bit Microprocessor Foundation for Success Built on MIPS’ Legacy of Scalability 8 © 2012 MIPS Technologies, Inc. All rights reserved. Industry’s Most Scalable Processor Architecture Microchip PIC32 64-bit Multicore Chips for Microcontrollers Advanced Networking And everything in between 9 © 2012 MIPS Technologies, Inc. All rights reserved. MIPS32® Processor Core Portfolio Classic MIPS Products Aptiv™ Generation Bonded triple-dispatch superscalar Out-of-Order CPU Family Enhanced Virtual Address (EVA), high-speed FPU, Per Core: high-performance CM+L2$ 16 core versions MP version 4.5 CoreMark/MHz 3.5 DMIPS/MHZ 1074K Series 74K Series Out of Order (OoO) Dual issue CPU Multi-threaded core, Family ECC, EVA, low power, MP version high-performance CM+L2$, 14 core versions Per Core: 1004K 3.2 CoreMark/MHz Series 1.7 DMIPS/MHZ 34K Series 24K/24KE Multi-threaded Series 9-stage pipeline 8-stage pipeline with DSP ASE Real-time CPU with Family DSP and SIMD for M14K/c microcontrollers and M4K/4KE Series deeply embedded Series 3.1 CoreMark/MHz applications 1.57 DMIPS/MHZ MCU/MPU 5 stage pipeline microMIPS ISA 10 © 2012 MIPS Technologies, Inc. All rights reserved. Welcome to the Aptiv™ Generation Don’t just think it. Do it. Get Aptiv! 11 © 2012 MIPS Technologies, Inc. All rights reserved. What the Experts had to Say about Aptiv “For now, the MIPS design team seems to have taken the performance lead away from ARM, and it deserves credit for this accomplishment.” – May 28, 2012 J. Scott Gardner, Senior Analyst at The Linley Group, senior editor for Full article is available for download at: Microprocessor Report http://www.mips.com/media/files/aptiv/Aptiv_Cores_Hit_the_Mark.pdf 12 © 2012 MIPS Technologies, Inc. All rights reserved. Competitive Per Core Performance – Half the Size Dual Core Cortex A15 size ~ Quad Core proAptiv size Quad Core for the Si cost of Dual Core! Core 1 Core 3 Cortex A15 Cortex A15 Core 1 Core 2 Coherence Core 2 Core 4 Balanced microarchitecture Minimizes area and power @ 1.0 GHz proAptiv Quad Cortex A15 Dual Total DMIPS 14,000 7,000 No specific process or implementations conditions included in above target frequency, but readily achievable in 40G and 28HPM on both processors, and area assumes common process node Cortex A15 info – Estimated area, no public info for this core is provided by ARM 13 © 2012 MIPS Technologies, Inc. All rights reserved. proAptiv Delivers High End Performance Efficiently proAptiv = top CoreMark score in Industry! proAptiv vs. A15 26% higher than Equal DMIPS @ nearly ½ the size! Cortex A15 1074K proAptiv A9 A15 1074K proAptiv A9 A15 proAptiv -> performance architecture • proAptiv results: prelim/target PPA specs + measured benchmarks on FPGA bitfile of pre-GA RTL with sophisticated branch prediction • Cortex A15 CoreMark results as estimated by Microprocessor Report 14 © 2012 MIPS Technologies, Inc. All rights reserved. interAptiv CoreMark Advantage @ 800 MHz interAptiv CoreMark 9000 performance leadership! 8000 7000 All implementations consume 6000 similar silicon area 5000 4000 3000 A7 2000 CoreMark Score? 1000 DMIPS DMIPS DMIPS DMIPS CoreMark CoreMark 0 CoreMark Cortex-A5 (x3) Cortex-A7 (x3) Cortex-A9 (x2) interAptiv (x3) interAptiv exceeds same-class Cortex devices on a CoreMark/MHz per core and CoreMark/mm2 basis 1. ARM = 12T power opt, MIPS = 12T area opt to 800 MHz freq, worst case SS corner with production margins Product configs include cores with FPU, 32KB Inst/Data L1$s, coherence fabric, IO coherence, L2$ (no L2 RAM) and debug logic Source: MIPS and ARM public data; A9 area estimated from published 4.6mm2 data and floorplan, with Neon area removed 15 © 2012 MIPS Technologies, Inc. All rights reserved. microAptiv vs. Cortex-M4 Performance DMIPS/MHz CoreMark/MHz 25% 40% microAptiv 1.57 microAptiv 3.09 Cortex-M4 1.25 Cortex-M4 2.19 Performance 2.5 Up to 2.5x 2 higher performance 1.5 1 0.5 0 FFT16, 64 FFT16, 256 IIR16, 16 FIR16, 256 LMS16, 256 PID16 CM4 microAptiv Comparing DSP performance (higher is better) microAptiv DSP Library, Cortex M4 CMSIS Library 16 © 2012 MIPS Technologies, Inc. All rights reserved. Aptiv Cores Span a Broad Application Range Home Mobile Networking Embedded Entertainment • High-end • Res. Gateway • High-end smartphone & • 802.11ac • Automotive DTV/STB/BD tablet apps • 3G/4G cellular infotainment processor processor infrastructure • Low-to mid- • Mainstream • Broadband CPE • Auto collision range apps DTV/STB/BD • Femtocell avoidance processor processor • Smart gateway • Auto powertrain • LTE baseband • Digital camera • NAS • SATA/RAID/SSD controller • MCU • Touchscreen • Conditional • VoIP • Industrial • SIM/security access • MOCA • Smart meters • GPS • WHDMI • WLAN • Automotive body/chassis 17 © 2012 MIPS Technologies, Inc. All rights reserved. Strategic Ecosystem in Place Complementary IP and Enabling Technologies Graphics RTOS/OS Video Audio Wireless Stacks VoIP User Interfaces Development Tools Networks Security EDA/ESL SoC IP Apps, Games, Web Foundries Industry Orgs Design Services Support for MIPS built over 20+ years 18 © 2012 MIPS Technologies, Inc. All rights reserved. MIPS Android 19 © 2012 MIPS Technologies, Inc. All rights reserved. 20 © 2012 MIPS Technologies, Inc. All rights reserved. Android on MIPS Timeline World’s first Google adopts non-nexus MIPS Android 4.1 (JB) tablet Philips architecture in Android to ship, it’s launches 100% MIPS again! CTS certified First Android MIPS tablets in 4.0 ICS China tablets worldwide, It’s MIPS! MIPS brings Android beyond mobile – in to STB 2009 2011 2012 21 © 2012 MIPS Technologies, Inc. All rights reserved. MIPS and the App Ecosystem Google officially supports the MIPS
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