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External Memory Interface Handbook Volume 3

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External Memory Interface Handbook Volume 3 External Memory Interface Handbook Volume 3: Reference Material Last updated for Altera Complete Design Suite: 15.0 Subscribe EMI_RM 101 Innovation Drive 2015.05.04 San Jose, CA 95134 Send Feedback www.altera.com TOC-2 Functional Description— UniPHY Contents Functional Description—UniPHY......................................................................1-1 I/O Pads.........................................................................................................................................................1-2 Reset and Clock Generation....................................................................................................................... 1-3 Dedicated Clock Networks......................................................................................................................... 1-3 Address and Command Datapath............................................................................................................. 1-4 Write Datapath.............................................................................................................................................1-5 Leveling Circuitry............................................................................................................................ 1-5 Read Datapath.............................................................................................................................................. 1-7 Sequencer...................................................................................................................................................... 1-8 Nios II-Based Sequencer................................................................................................................. 1-9 RTL-based Sequencer....................................................................................................................1-13 Shadow Registers........................................................................................................................................1-15 Shadow Registers Operation........................................................................................................ 1-17 UniPHY Interfaces.....................................................................................................................................1-17 The DLL and PLL Sharing Interface........................................................................................... 1-18 The OCT Sharing Interface.......................................................................................................... 1-19 UniPHY Signals..........................................................................................................................................1-21 PHY-to-Controller Interfaces.................................................................................................................. 1-25 Using a Custom Controller...................................................................................................................... 1-30 AFI 4.0 Specification..................................................................................................................................1-31 Bus Width and AFI Ratio............................................................................................................. 1-32 AFI Parameters...............................................................................................................................1-32 AFI Signals...................................................................................................................................... 1-34 Register Maps............................................................................................................................................. 1-41 UniPHY Register Map...................................................................................................................1-42 Controller Register Map............................................................................................................... 1-45 Ping Pong PHY.......................................................................................................................................... 1-46 Ping Pong PHY Feature Description.......................................................................................... 1-46 Ping Pong PHY Architecture....................................................................................................... 1-47 Ping Pong PHY Operation........................................................................................................... 1-49 Efficiency Monitor and Protocol Checker..............................................................................................1-50 Efficiency Monitor.........................................................................................................................1-50 Protocol Checker............................................................................................................................1-50 Read Latency Counter...................................................................................................................1-50 Using the Efficiency Monitor and Protocol Checker................................................................1-50 Avalon CSR Slave and JTAG Memory Map...............................................................................1-51 UniPHY Calibration Stages......................................................................................................................1-53 Calibration Overview.................................................................................................................... 1-54 Calibration Stages.......................................................................................................................... 1-54 Memory Initialization................................................................................................................... 1-55 Stage 1: Read Calibration Part One—DQS Enable Calibration and DQ/DQS Centering...1-55 Stage 2: Write Calibration Part One............................................................................................1-59 Altera Corporation Functional Description— UniPHY TOC-3 Stage 3: Write Calibration Part Two—DQ/DQS Centering.................................................... 1-61 Stage 4: Read Calibration Part Two—Read Latency Minimization........................................1-61 Calibration Signals.........................................................................................................................1-61 Calibration Time............................................................................................................................1-61 Document Revision History.....................................................................................................................1-62 Functional Description—Arria 10 EMIF............................................................2-1 Supported Memory Protocols....................................................................................................................2-2 Key Differences Compared to UniPHY IP and Previous Device Families..........................................2-2 Migrating from Previous Device Families................................................................................................2-2 Arria 10 EMIF Architecture: Introduction...............................................................................................2-3 Arria 10 EMIF Architecture: I/O Subsystem............................................................................... 2-4 Arria 10 EMIF Architecture: I/O Column....................................................................................2-4 Arria 10 EMIF Architecture: I/O AUX.........................................................................................2-5 Arria 10 EMIF Architecture: I/O Bank......................................................................................... 2-5 Arria 10 EMIF Architecture: I/O Lane..........................................................................................2-9 Arria 10 EMIF Architecture: Input DQS Clock Tree............................................................... 2-11 Arria 10 EMIF Architecture: PHY Clock Tree.......................................................................... 2-12 Arria 10 EMIF Architecture: PLL Reference Clock Networks................................................ 2-12 Arria 10 EMIF Architecture: Clock Phase Alignment..............................................................2-13 Hardware Resource Sharing Among Multiple EMIFs..........................................................................2-14 I/O Aux Sharing.............................................................................................................................2-15 I/O Bank Sharing........................................................................................................................... 2-15 PLL Reference Clock Sharing.......................................................................................................2-16 Core Clock Network Sharing....................................................................................................... 2-17 RZQ Pin Sharing............................................................................................................................2-17 Arria 10 EMIF IP Component................................................................................................................
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