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Research Collection Research Collection Doctoral Thesis Programmable intellectual property modules for system design by reuse Author(s): Röwer, Thomas Publication Date: 2000 Permanent Link: https://doi.org/10.3929/ethz-a-004039264 Rights / License: In Copyright - Non-Commercial Use Permitted This page was generated automatically upon download from the ETH Zurich Research Collection. For more information please consult the Terms of use. ETH Library Diss. ETH No. 13905 Programmable Intellectual Property Modules for System Design by Reuse A dissertation submitted to the SWISS FEDERAL INSTITUTE OF TECHNOLOGY ZURICH for the degree of Doctor of Technical Sciences presented by THOMAS ROWER Dipl. Ing. born August 1st, 1969 citizen of Germany accepted on the recommendation of Prof. Dr. W. Ficlitner, examiner Prof. Dr. L. Thiele, co-examiner 2000 f < * f s ; « : Acknowledgments I would like to thank my supervisor. Prof. Dr. Wolfgang Fichtner, for his overall support and for his faith in me and my work. 1 would also like to thank Prof. Dr. Lothar Thiele for reading and commenting on my thesis. Special thanks to Hubert Kaeslin and Norbert Felber for their en¬ couragement and support during my research work as well as for their proofreading of and commitment to my thesis. Furthermore, I want to thank the secretaries for taking care of the administration and Christoph Wicki for excellent supervision of hard- and software. Hanspeter "Die Granate" Mathys was a great, help in taking the chip-photos included in this thesis. The support of Mathias Bränclh and Robert Reutemann on the chip design process was of great value. 1 acknowledge the financial support of KTL a Commission for tech¬ nology and innovation supported by the Swiss Government and Siemens Schweiz AG. Several students worked with me during my thesis and provided very helpful discussions on different topics of this thesis. Peter Lût hi did a great job in implementing the register-based processor. Very special thanks go to Markus Th alma nu and Manfred Stadler my co-workers on the ITRASYS project. Many ideas that are presented in my thesis originate from discussions with the two. 1 also want to express my gratitude to all my colleagues at the Inte¬ grated Systems Laboratory who contributed to the good working envi- lii IV Acknowledgments ronment, especially Michael Oberle made the IIS a FUN place to work. I owe very special gratefulness to my parents who made this all possible, in the first place. I want to particularly thank my family, my wife, Susanne, for her un¬ limited patience and understanding, and our son, Alexander, for sleep¬ ing quite a lot at night. Contents Acknowledgments iii Abstract ix Zusammenfassung xi 1 Introduction 1 1.1 Goals of this work 3 1.2 Structure of the thesis 3 2 Hardware/software co-design 5 2.1 Principles 5 2.2 System-level hardware/software co-design 6 2.3 An example implementation 8 2.3.1 Description of the system 10 2.3.2 Hardware/software partitioning 11 2.3.3 Task scheduling and interrupt handling 12 2.3.4 instruct ion Application-specific set processor . 13 v VI Contents 2.3.5 Area efficiency 15 2.4 Discussion and Outlook 19 3 System design by reuse 23 3.1 History of IC design 23 3.2 System design and IP reuse 25 3.2.1 System design flow 27 3.2.2 IP module design 29 Hard IP modules 29 Soft IP modules 30 IP design How 31 3.2.3 Functional verification 33 3.2.4 Test 34 4 The case for programmable intellectual property mod¬ ules 37 4.1 Present Situation 38 4.2 Concept 42 4.3 System design advantages 43 4.3.1 Flexible hard-IPs 45 4.3.2 Adaptable interfaces 45 4.3.3 Block test 47 4.4 Evaluation 48 Contents vu 5 The embedded processor 51 5.1 Requirements 52 5.2 The stack processor 53 5.2.1 Architect ure 53 5.2.2 Qualitative adaption of 1 he processor core .... 56 5.2.3 Numerical parametrizatiou of the processor core 57 5.2.4 System interfaces 60 5.2.5 Implementation 60 5.3 The register-based processor 61 5.3.1 Architecture 62 5.3.2 Qualitative adaptation of the processor core ... 66 5.3.3 Numerical parameterization of the processor core 66 5.3.4 System interfaces 67 5.3.5 Implementation 69 5.4 Comparison 70 5.4.1 Compiler support 70 5.4.2 Interrupt capabilities 71 5.4.3 Parametrizatiou 71 5.4.4 Area efficiency 71 6 Functional verification of PIP modules 77 6.1 Behavioral model 78 6.2 Expected responses generation 82 6.3 Functional veriiicatiou of the customized RTL model . 85 vin Contents 6.4 Test bench and real-time constraints 85 7 A pip module design example 87 7.1 Architecture 87 7.2 Adaptable Interfaces 91 7.3 Built-in self-test 95 7.4 Parametrization of the PIP module 97 7.5 Implementation Results 100 8 Conclusions 105 A Parameter set of the PIP module 107 B Parameter set of the register-based processor IP module 113 Bibliography 117 Curriculum Vitae 131 f\ %r\ r~i -|- -i^» <rv /"» T" The design of integrated circuits (IC) is currently undergoing a paradigm shift from "application-specific" to "reusable". Increasing sys¬ tem complexity asks for a new approach to IC design, because starting a design from scratch in each and every new project leads to severe violations of time-to-market requirements. Housing large portions from previous projects for a new system may overcome the imposed efficiency problems. Hardware/software co-design is one of the most prominent method¬ ologies used to improve the design efficiency and quality. HowTever. system design by reuse is problematic in combination with system level hardware/software co-design. The tight coupling between a system pro¬ cessor and several reusable hardware blocks does not fit well into a, sys¬ tem design flow based on several independent intellectual property (IP) blocks. This thesis proposes the concept of programmable intellectual prop¬ erty modules (PIP) to solve this problem. The key innovation is to include a processor into every major fP module. PIP modules oiler the possibility to integrate highly reusable IP modifies that have superior properties because the embedded processor can be used for several sys¬ tem design tasks. Some of these are flexibility in the implementation of standards and protocols, system debugging after silicon production or the ability to postpone decisions due to t he high configurability. PIP modules fit perfectly into a system design flow based on system-level functional partitioning and IP-level hardware/software partitioning. The most important building block of PIP modules is obviously IX X Abstract the embedded processor. A detailed investigation of processor concepts showed that a register-based architecture using stack registers for fast interrupt switching is best suited for PIP modules. A convenient functional verification flow is crucial for successful IP modules. A simulation-based flow suitable for highly parametrized PIP modules has been established. It uses a configuration-independent be¬ havioral model to check the correctness of the synthesizable RTL model. An experimental implementation of a STM-J./STS3 block demon¬ strates additional advantages of the PIP concept, like flexible hard-IPs, software driven BIST, and adaptable interface protocols. Zusammenfassung Der Entwurf integrierter Schaltungen (IC) erfährt momentan eine tiefgreifende Veränderung von "anwendungsspezifisch"' zu "wiederver¬ wendbar". Die ständig wachsende Komplexität der integrierten Syste¬ me macht eine neue Vorgehensweise im Entwurf von ICs nötig. Die vom Markt geforderten immer kürzeren Produkt zyklcn können nicht mehr erfüllt werden, wenn in jedem neuen Projekt wieder von Grund auf neu mit dem Entwurf begonnen werden muß. Wenn es gelingt, große Tei¬ le vorhergehender Projekte in einen neuen IC zu übernehmen, können viele Effizienzprobleme gelöst werden. Die am häufigsten angewandte Methode zur Steigung der Effizienz und Qualität beim Entwurf integrierter Schaltungen ist die gleichzeitige Erstellung von Schaltungsteilen und Programmcode. genannt hardwa¬ re/software co-design. Es ist allerdings sehr problematisch, diese Metho¬ de mit einem Systementwurfsprozess zu verbinden, der auf der Wieder¬ verwertung großer Teile vorheriger Schaltungen basiert. Die sehr enge Kopplung zwischen dem Systemrechner und mehreren wiederverwend¬ baren Sehaltungsteilcn passt nicht gut in einen Entwurfsprozess, der auf der Verwendung von IP-Modulen (IP. intellectual property) basiert. Um dieses Problem zu lösen, wird in dieser Doktorarbeit das Prin¬ zip programmierbarer, wiederverwendbarer Bausteine (PIP) vorgeschla¬ gen. Die wichtigste Neuerung dieses Konzepts ist, einen Prozessor in je¬ des größere IP-Modul zu integrieren. PIP-Module haben herausragende Eigenschaften, welche durch die Integration des Prozessors ermöglicht werden und bieten viele Vorteile beim Systementwurf. Zum Beispiel erreicht mau hohe Flexibilität bei der Implementation von Protokollen und Standards, nach der Produktion der integrierten Schaltung können XI Xll Zusammenfassung mögliche Fehler noch korrigiert werden oder man kann Entscheidungen erst spät im Entwurfsprozess fällen. PIP-Module passen perfekt in einen Entwurfsprozess, der auf der Aufteilung der Funktionalität auf System¬ niveau und der Einteilung in Hardware und Software auf Modulniveau beruht. Der wichtigste Baustein von PIP-Modulen ist offensichtlich der inte¬ grierte Prozessor. Eine detaillierte Untersuchung verschiedener Prozes¬ sorkonzepte ergab, daß eine registerbasierte Architektur, die um Schat¬ tenregister für schnellen Kontextwechsel ergänzt wurde, am besten ge¬ eignet ist. Die funktionale Verifikation ist äußerst wichtig für den Erfolg von IP-Modulen. Für hochgradig parametrisiorbare PIP-Module wurde im Rahmen dieser Arbeit ein simulationsbasiorfer Ansatz etabliert. Er be¬ nutzt ein konfigurationunabhängiges Verhaltensmodel, um die Richtig¬ keit des RTL-Models zu überprüfen. Durch die Implementation eines STM-1/STS3 Blocks konnten wei¬ tere wichtige Vorteile von PIP-Modulen zu Tage gefördert werden. Das neue Konzept ermöglicht die Verwirklichung von flexiblen hard-IP-Mo- dulen, einen in Software realisierten BIST und anpassbare Schnittstel¬ lenprotokolle.
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