Parallel Finger Search Structures Seth Gilbert Computer Science, National University of Singapore Wei Quan Lim Computer Science, National University of Singapore
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Advanced Data Structures
Advanced Data Structures PETER BRASS City College of New York CAMBRIDGE UNIVERSITY PRESS Cambridge, New York, Melbourne, Madrid, Cape Town, Singapore, São Paulo Cambridge University Press The Edinburgh Building, Cambridge CB2 8RU, UK Published in the United States of America by Cambridge University Press, New York www.cambridge.org Information on this title: www.cambridge.org/9780521880374 © Peter Brass 2008 This publication is in copyright. Subject to statutory exception and to the provision of relevant collective licensing agreements, no reproduction of any part may take place without the written permission of Cambridge University Press. First published in print format 2008 ISBN-13 978-0-511-43685-7 eBook (EBL) ISBN-13 978-0-521-88037-4 hardback Cambridge University Press has no responsibility for the persistence or accuracy of urls for external or third-party internet websites referred to in this publication, and does not guarantee that any content on such websites is, or will remain, accurate or appropriate. Contents Preface page xi 1 Elementary Structures 1 1.1 Stack 1 1.2 Queue 8 1.3 Double-Ended Queue 16 1.4 Dynamical Allocation of Nodes 16 1.5 Shadow Copies of Array-Based Structures 18 2 Search Trees 23 2.1 Two Models of Search Trees 23 2.2 General Properties and Transformations 26 2.3 Height of a Search Tree 29 2.4 Basic Find, Insert, and Delete 31 2.5ReturningfromLeaftoRoot35 2.6 Dealing with Nonunique Keys 37 2.7 Queries for the Keys in an Interval 38 2.8 Building Optimal Search Trees 40 2.9 Converting Trees into Lists 47 2.10 -
Search Trees
Lecture III Page 1 “Trees are the earth’s endless effort to speak to the listening heaven.” – Rabindranath Tagore, Fireflies, 1928 Alice was walking beside the White Knight in Looking Glass Land. ”You are sad.” the Knight said in an anxious tone: ”let me sing you a song to comfort you.” ”Is it very long?” Alice asked, for she had heard a good deal of poetry that day. ”It’s long.” said the Knight, ”but it’s very, very beautiful. Everybody that hears me sing it - either it brings tears to their eyes, or else -” ”Or else what?” said Alice, for the Knight had made a sudden pause. ”Or else it doesn’t, you know. The name of the song is called ’Haddocks’ Eyes.’” ”Oh, that’s the name of the song, is it?” Alice said, trying to feel interested. ”No, you don’t understand,” the Knight said, looking a little vexed. ”That’s what the name is called. The name really is ’The Aged, Aged Man.’” ”Then I ought to have said ’That’s what the song is called’?” Alice corrected herself. ”No you oughtn’t: that’s another thing. The song is called ’Ways and Means’ but that’s only what it’s called, you know!” ”Well, what is the song then?” said Alice, who was by this time completely bewildered. ”I was coming to that,” the Knight said. ”The song really is ’A-sitting On a Gate’: and the tune’s my own invention.” So saying, he stopped his horse and let the reins fall on its neck: then slowly beating time with one hand, and with a faint smile lighting up his gentle, foolish face, he began.. -
The Random Access Zipper: Simple, Purely-Functional Sequences
The Random Access Zipper: Simple, Purely-Functional Sequences Kyle Headley and Matthew A. Hammer University of Colorado Boulder [email protected], [email protected] Abstract. We introduce the Random Access Zipper (RAZ), a simple, purely-functional data structure for editable sequences. The RAZ com- bines the structure of a zipper with that of a tree: like a zipper, edits at the cursor require constant time; by leveraging tree structure, relocating the edit cursor in the sequence requires log time. While existing data structures provide these time bounds, none do so with the same simplic- ity and brevity of code as the RAZ. The simplicity of the RAZ provides the opportunity for more programmers to extend the structure to their own needs, and we provide some suggestions for how to do so. 1 Introduction The singly-linked list is the most common representation of sequences for func- tional programmers. This structure is considered a core primitive in every func- tional language, and morever, the principles of its simple design recur througout user-defined structures that are \sequence-like". Though simple and ubiquitous, the functional list has a serious shortcoming: users may only efficiently access and edit the head of the list. In particular, random accesses (or edits) generally require linear time. To overcome this problem, researchers have developed other data structures representing (functional) sequences, most notably, finger trees [8]. These struc- tures perform well, allowing edits in (amortized) constant time and moving the edit location in logarithmic time. More recently, researchers have proposed the RRB-Vector [14], offering a balanced tree representation for immutable vec- tors. -
Design of Data Structures for Mergeable Trees∗
Design of Data Structures for Mergeable Trees∗ Loukas Georgiadis1; 2 Robert E. Tarjan1; 3 Renato F. Werneck1 Abstract delete(v): Delete leaf v from the forest. • Motivated by an application in computational topology, merge(v; w): Given nodes v and w, let P be the path we consider a novel variant of the problem of efficiently • from v to the root of its tree, and let Q be the path maintaining dynamic rooted trees. This variant allows an from w to the root of its tree. Restructure the tree operation that merges two tree paths. In contrast to the or trees containing v and w by merging the paths P standard problem, in which only one tree arc at a time and Q in a way that preserves the heap order. The changes, a single merge operation can change many arcs. merge order is unique if all node labels are distinct, In spite of this, we develop a data structure that supports which we can assume without loss of generality: if 2 merges and all other standard tree operations in O(log n) necessary, we can break ties by node identifier. See amortized time on an n-node forest. For the special case Figure 1. that occurs in the motivating application, in which arbitrary arc deletions are not allowed, we give a data structure with 1 an O(log n) amortized time bound per operation, which is merge(6,11) asymptotically optimal. The analysis of both algorithms is 3 2 not straightforward and requires ideas not previously used in 6 7 4 5 the study of dynamic trees. -
Bulk Updates and Cache Sensitivity in Search Trees
BULK UPDATES AND CACHE SENSITIVITY INSEARCHTREES TKK Research Reports in Computer Science and Engineering A Espoo 2009 TKK-CSE-A2/09 BULK UPDATES AND CACHE SENSITIVITY INSEARCHTREES Doctoral Dissertation Riku Saikkonen Dissertation for the degree of Doctor of Science in Technology to be presented with due permission of the Faculty of Information and Natural Sciences, Helsinki University of Technology for public examination and debate in Auditorium T2 at Helsinki University of Technology (Espoo, Finland) on the 4th of September, 2009, at 12 noon. Helsinki University of Technology Faculty of Information and Natural Sciences Department of Computer Science and Engineering Teknillinen korkeakoulu Informaatio- ja luonnontieteiden tiedekunta Tietotekniikan laitos Distribution: Helsinki University of Technology Faculty of Information and Natural Sciences Department of Computer Science and Engineering P.O. Box 5400 FI-02015 TKK FINLAND URL: http://www.cse.tkk.fi/ Tel. +358 9 451 3228 Fax. +358 9 451 3293 E-mail: [email protected].fi °c 2009 Riku Saikkonen Layout: Riku Saikkonen (except cover) Cover image: Riku Saikkonen Set in the Computer Modern typeface family designed by Donald E. Knuth. ISBN 978-952-248-037-8 ISBN 978-952-248-038-5 (PDF) ISSN 1797-6928 ISSN 1797-6936 (PDF) URL: http://lib.tkk.fi/Diss/2009/isbn9789522480385/ Multiprint Oy Espoo 2009 AB ABSTRACT OF DOCTORAL DISSERTATION HELSINKI UNIVERSITY OF TECHNOLOGY P.O. Box 1000, FI-02015 TKK http://www.tkk.fi/ Author Riku Saikkonen Name of the dissertation Bulk Updates and Cache Sensitivity in Search Trees Manuscript submitted 09.04.2009 Manuscript revised 15.08.2009 Date of the defence 04.09.2009 £ Monograph ¤ Article dissertation (summary + original articles) Faculty Faculty of Information and Natural Sciences Department Department of Computer Science and Engineering Field of research Software Systems Opponent(s) Prof. -
THE INVARIANCE THESIS 1. Introduction in 1936, Turing [47
THE INVARIANCE THESIS NACHUM DERSHOWITZ AND EVGENIA FALKOVICH-DERZHAVETZ School of Computer Science, Tel Aviv University, Ramat Aviv, Israel e-mail address:[email protected] School of Computer Science, Tel Aviv University, Ramat Aviv, Israel e-mail address:[email protected] Abstract. We demonstrate that the programs of any classical (sequential, non-interactive) computation model or programming language that satisfies natural postulates of effective- ness (which specialize Gurevich’s Sequential Postulates)—regardless of the data structures it employs—can be simulated by a random access machine (RAM) with only constant factor overhead. In essence, the postulates of algorithmicity and effectiveness assert the following: states can be represented as logical structures; transitions depend on a fixed finite set of terms (those referred to in the algorithm); all atomic operations can be pro- grammed from constructors; and transitions commute with isomorphisms. Complexity for any domain is measured in terms of constructor operations. It follows that any algorithmic lower bounds found for the RAM model also hold (up to a constant factor determined by the algorithm in question) for any and all effective classical models of computation, what- ever their control structures and data structures. This substantiates the Invariance Thesis of van Emde Boas, namely that every effective classical algorithm can be polynomially simulated by a RAM. Specifically, we show that the overhead is only a linear factor in either time or space (and a constant factor in the other dimension). The enormous number of animals in the world depends of their varied structure & complexity: — hence as the forms became complicated, they opened fresh means of adding to their complexity. -
Biased Finger Trees and Three-Dimensional Layers of Maxima
Purdue University Purdue e-Pubs Department of Computer Science Technical Reports Department of Computer Science 1993 Biased Finger Trees and Three-Dimensional Layers of Maxima Mikhail J. Atallah Purdue University, [email protected] Michael T. Goodrich Kumar Ramaiyer Report Number: 93-035 Atallah, Mikhail J.; Goodrich, Michael T.; and Ramaiyer, Kumar, "Biased Finger Trees and Three- Dimensional Layers of Maxima" (1993). Department of Computer Science Technical Reports. Paper 1052. https://docs.lib.purdue.edu/cstech/1052 This document has been made available through Purdue e-Pubs, a service of the Purdue University Libraries. Please contact [email protected] for additional information. HlASED FINGER TREES AND THREE-DIMENSIONAL LAYERS OF MAXIMA Mikhnil J. Atallah Michael T. Goodrich Kumar Ramaiyer eSD TR-9J-035 June 1993 (Revised 3/94) (Revised 4/94) Biased Finger Trees and Three-Dimensional Layers of Maxima Mikhail J. Atallah" Michael T. Goodricht Kumar Ramaiyert Dept. of Computer Sciences Dept. of Computer Science Dept. of Computer Science Purdue University Johns Hopkins University Johns Hopkins University W. Lafayette, IN 47907-1398 Baltimore, MD 21218-2694 Baltimore, MD 21218-2694 mjalDcs.purdue.edu goodrich~cs.jhu.edu kumarlDcs . j hu. edu Abstract We present a. method for maintaining biased search trees so as to support fast finger updates (i.e., updates in which one is given a pointer to the part of the hee being changed). We illustrate the power of such biased finger trees by showing how they can be used to derive an optimal O(n log n) algorithm for the 3-dimcnsionallayers-of-maxima problem and also obtain an improved method for dynamic point location. -
December, 1990
DIMACS Technical Report 90-75 December, 1990 FULLY PERSISTENT LISTS WITH CATENATION James R. Driscolll Department of Mathematics and Computer Science Dartmouth College Hanover, New Hampshire 03755 Daniel D. K. Sleator2 3 School of Computer Science Carnegie Mellon University Pittsburgh, PA 15213 Robert E. Tarjan4 5 Computer Science Department Princeton University Princeton, New Jersey 08544 and NEC Research Institute Princeton, New Jersey 08540 1 Supported in part by the NSF grant CCR-8809573, and by DARPA as monitored by the AFOSR grant AFOSR-904292 2 Supported in part by DIMACS 3 Supported in part by the NSF grant CCR-8658139 4 Permanent member of DIMACS 6 Supported in part by the Office of Naval Research contract N00014-87-K-0467 DIMACS is a cooperative project of Rutgers University, Princeton University, AT&T Bell Laboratories and Bellcore. DIMACS is an NSF Science and Technology Center, funded under contract STC-88-09648; and also receives support from the New Jersey Commission on Science and Technology. 1. Introduction In this paper we consider the problem of efficiently implementing a set of side-effect-free procedures for manipulating lists. These procedures are: makelist( d).- Create and return a new list of length 1 whose first and only element is d. first( X ) : Return the first element of list X. Pop(x): Return a new list that is the same as list X with its first element deleted. This operation does not effect X. catenate(X,Y): Return a new list that is the result of catenating list X and list Y, with X first, followed by Y (X and Y may be the same list). -
Optimal Multithreaded Batch-Parallel 2-3 Trees Arxiv:1905.05254V2
Optimal Multithreaded Batch-Parallel 2-3 Trees Wei Quan Lim National University of Singapore Keywords Parallel data structures, pointer machine, multithreading, dictionaries, 2-3 trees. Abstract This paper presents a batch-parallel 2-3 tree T in an asynchronous dynamic multithreading model that supports searches, insertions and deletions in sorted batches and has essentially optimal parallelism, even under the restrictive QRMW (queued read-modify-write) memory contention model where concurrent accesses to the same memory location are queued and serviced one by one. Specifically, if T has n items, then performing an item-sorted batch (given as a leaf-based balanced binary tree) of b operations · n ¹ º ! 1 on T takes O b log b +1 +b work and O logb+logn span (in the worst case as b;n ). This is information-theoretically work-optimal for b ≤ n, and also span-optimal for pointer-based structures. Moreover, it is easy to support optimal intersection, n union and difference of instances of T with sizes m ≤ n, namely within O¹m·log¹ m +1ºº work and O¹log m + log nº span. Furthermore, T supports other batch operations that make it a very useful building block for parallel data structures. To the author’s knowledge, T is the first parallel sorted-set data structure that can be used in an asynchronous multi-processor machine under a memory model with queued contention and yet have asymptotically optimal work and span. In fact, T is designed to have bounded contention and satisfy the claimed work and span bounds regardless of the execution schedule. -
On Data Structures and Memory Models
2006:24 DOCTORAL T H E SI S On Data Structures and Memory Models Johan Karlsson Luleå University of Technology Department of Computer Science and Electrical Engineering 2006:24|: 402-544|: - -- 06 ⁄24 -- On Data Structures and Memory Models by Johan Karlsson Department of Computer Science and Electrical Engineering Lule˚a University of Technology SE-971 87 Lule˚a, Sweden May 2006 Supervisor Andrej Brodnik, Ph.D., Lule˚a University of Technology, Sweden Abstract In this thesis we study the limitations of data structures and how they can be overcome through careful consideration of the used memory models. The word RAM model represents the memory as a finite set of registers consisting of a constant number of unique bits. From a hardware point of view it is not necessary to arrange the memory as in the word RAM memory model. However, it is the arrangement used in computer hardware today. Registers may in fact share bits, or overlap their bytes, as in the RAM with Byte Overlap (RAMBO) model. This actually means that a physical bit can appear in several registers or even in several positions within one regis- ter. The RAMBO model of computation gives us a huge variety of memory topologies/models depending on the appearance sets of the bits. We show that it is feasible to implement, in hardware, other memory models than the word RAM memory model. We do this by implementing a RAMBO variant on a memory board for the PC100 memory bus. When alternative memory models are allowed, it is possible to solve a number of problems more efficiently than under the word RAM memory model. -
Algorithms: a Quest for Absolute Definitions∗
Algorithms: A Quest for Absolute De¯nitions¤ Andreas Blassy Yuri Gurevichz Abstract What is an algorithm? The interest in this foundational problem is not only theoretical; applications include speci¯cation, validation and veri¯ca- tion of software and hardware systems. We describe the quest to understand and de¯ne the notion of algorithm. We start with the Church-Turing thesis and contrast Church's and Turing's approaches, and we ¯nish with some recent investigations. Contents 1 Introduction 2 2 The Church-Turing thesis 3 2.1 Church + Turing . 3 2.2 Turing ¡ Church . 4 2.3 Remarks on Turing's analysis . 6 3 Kolmogorov machines and pointer machines 9 4 Related issues 13 4.1 Physics and computations . 13 4.2 Polynomial time Turing's thesis . 14 4.3 Recursion . 15 ¤Bulletin of European Association for Theoretical Computer Science 81, 2003. yPartially supported by NSF grant DMS{0070723 and by a grant from Microsoft Research. Address: Mathematics Department, University of Michigan, Ann Arbor, MI 48109{1109. zMicrosoft Research, One Microsoft Way, Redmond, WA 98052. 1 5 Formalization of sequential algorithms 15 5.1 Sequential Time Postulate . 16 5.2 Small-step algorithms . 17 5.3 Abstract State Postulate . 17 5.4 Bounded Exploration Postulate and the de¯nition of sequential al- gorithms . 19 5.5 Sequential ASMs and the characterization theorem . 20 6 Formalization of parallel algorithms 21 6.1 What parallel algorithms? . 22 6.2 A few words on the axioms for wide-step algorithms . 22 6.3 Wide-step abstract state machines . 23 6.4 The wide-step characterization theorem . -
A Microcoded Machine Simulator and Microcode Assembler in a FORTH Environment A
A Microcoded Machine Simulator and Microcode Assembler in a FORTH Environment A. Cotterman, R. Dixon, R. Grewe, G. Simpson Department ofComputer Science Wright State University Abstract A FORTH program which provides a design tool for systems which contain a microcoded component was implemented and used in a computer architecture laboratory. The declaration of standard components such as registers, ALUs, busses, memories, and the connections is required. A sequencer and timing signals are implicit in the implementation. The microcode is written in a FORTH-like language which can be executed directly as a simulation or interpreted to produce a fixed horizontal microcode bit pattern for generating ROMs. The direct execution of the microcode commands (rather than producing bit patterns and interpreting those instructions) gives a simpler, faster implementation. Further, the designer may concentrate on developing the design at a block level without considering some ofthe implementation details (such as microcode fields) which might change several times during the design cycle. However, the design is close enough to the hardware to be readily translated. Finally, the fact that the same code used for the simulation may be used for assembly ofthe microcode instructions (after the field patterns have been specified) saves time and reduces errors. 1. Introduction At the Wright State University computer architecture laboratory a microcoded machine simulator and microcode generator have been developed using FORTH. These tools have been used as "hands-on" instructional aids in graduate courses in computer architecture, and are also being used to aid the in-house development of new architectures in ongoing research efforts. The simulator provides basic block-level functional control and data-flow simulation for a machine architecture based on a microcoded implementation.