Anatomy of a Hypersparc Module
Total Page：16
File Type：pdf, Size：1020Kb
TECH BRIEF: ANATOMY OF A hyperSPARC MMODULEODULE Microprocessor technology is continuously five execution units: an Arithmetic and Logic Unit the RT625s cache coherency logic can quickly evolving in complexity in order to meet the (ALU), a load/Store unit, a Branch/Call unit (for determine snoop hits and misses for multiprocess- demands of todays high-performance applications. processing control transfer instructions), a float- ing applications without stalling the RT620s access Through advanced packaging technology, ROSS has ing-point adder, and a floating-point multiplier to the cache. Both copy-back and write-through increased the speed and reliability, reduced the unit. The RT620 contains two register files: 136 caching modes are supported. size, and facilitated the manufacturability of its integer resisters configured as eight register win- The memory management portion (MMU) of CPU chip sets in order to address the markets dows, and 32 separate floating-point registers in the RT625 is a SPARC Reference MMU with a 64- requirements. the floating-point unit. entry, fully set-associative Translation Lookaside ROSS hyperSPARC chip set utilizes multi-die Buffer (TLB) that supports 4096 contexts. The packaging (MDP) in which multiple die are con- The hyperSPARC chip set RT625 contains a read buffer and a write buffer for nected through a multi-layer substrate in a single delivers world-class buffering the 32-byte cache lines in and out of the package to achieve higher clock frequencies, lower performance in second-level cache. power consumption, less capacitive loading, and The RT627 is a high speed SRAM that is custom- smaller board-surface requirements. The multi-die packaging. designed for hyperSPARCs cache requirements. It hyperSPARC chip set is comprised of the super- is organized as four arrays of 16-Kbyte static mem- scalar RT620 Central Processing Unit (CPU), the hyperSPARCs second-level cache is built ory with byte-write logic, registered inputs, and RT625 Cache Controller, Memory Management, and around the RT625 CMTU, a combined cache con- data-in and data-out latches. The RT627 provides a Tag Unit (CMTU), and four RT627 Cache Data Units troller and memory management unit that sup- zero-wait-state cache to the CPU with no pipeline (CDUs) for 256 Kbytes of second-level cache. The ports shared-memory, symmetric multiprocessing. penalty (i.e., stalls) for loads and stores that hit the chip set supports uniprocessing (Level 1 MBus) or The cache controller portion supports 256 Kbytes cache. The RT627 is designed specifically for multiprocessing (Level 2 MBus). of cache, made up of four RT627 CDUs. The RT625 hyperSPARC, so it doesnt require glue logic for The RT620, hyperSPARCs primary processing contains 4-Kbytes of on-chip cache tags. The cache interfacing to the RT620 (CPU) and the RT625 unit, consists of an 8-Kbyte instruction cache and is physically tagged and virtually indexed so that (CMTU). RT620 CPU: The RT620 is a high performance full- RT625 CMTU: The RT625 is a combined Cache custom CMOS implementation of integrated SPARC Controller and Memory Management Unit opti- integer and floating-point logic, with an on-chip mized for multiprocessing. It features a SPARC cache for instructions. Combining a superscalar, Reference MMU, cache controller, cache tag memory highly-pipelined architecture with advanced manu- (supports up to 256-KBytes of second-level cache), facturing technology allows the RT620 to achieve read and write buffers, and asynchronous bus ultra-high performance without requiring software interface. The RT625 supports the SPARC MBus recompilation. Level 2 protocol for multiprocessing systems. Reliability: Specially designed for ROSS hyperSPARC modules, heat sinks provide effec- tive thermal management to ensure hyperSPARCs reliability in a wide range of Connector: The MBus connector is a con- applications and environments. trolled-impedance type based on a microstrip configuration that provides a controlled char- acteristic impedance plus very low inductance RT627 CDU: The RT627 Cache Data Unit is organized as four MBus Module: hyperSPARC conforms to the SPARC-stan- and capacitance. Separate power and ground arrays of 16-KByte static memory with a built-in, one-deep dard MBus specifications and is populated with either blades are provided for isolation and to pre- write buffer pipeline, byte write logic, registered inputs, data- one or two hyperSPARC MDPs. Specially designed are vent noise transference. The connector is a in and data-out latches, and data forwarding logic for the write both uni- and multiprocessing daughtercards. These SPARC standard. buffer. The RT627 is designed specifically for hyperSPARC, modules provide an easy and inexpensive upgrade path requiring no glue logic for interfacing to the RT620 and RT625. for SPARCstation users. ® 5316 West Hwy. 290 Austin, Texas 78735 RTB104 (512) 919-5207 FAX (512) 919-5200 E-mail: [email protected].