Single Rail Ternary Null Convention Logic Architecture for Digital Signal Processing Applications
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Single Rail Ternary Null Convention Logic Architecture for Digital Signal Processing Applications A thesis submitted in fulfillment of the requirements for the Degree of Doctor of Philosophy Sameh Andrawes Master of Engineering (Electronics and Telecommunications) Victoria University, Melbourne, Australia School of Engineering College of Science, Engineering and Health RMIT University February 2020 Declaration I certify that except where due acknowledgement has been made, the work is that of the author alone; the work has not been submitted previously, in whole or in part, to qualify for any other academic award; the content of the thesis is the result of work which has been carried out since the official commencement date of the approved research program; any editorial work, paid or unpaid, carried out by a third party is acknowledged; and, ethics procedures and guidelines have been followed. I acknowledge the support I have received for my research through the provision of an Australian Government Research Training Program Scholarship. Sameh Andrawes February 2020 ii Abstract Synchronous design techniques have been used for decades to design and implement digital systems mainly due to their simplicity and the ready availability of sophisticated tools. While these techniques offer many advantages there are also some disadvantages. Issues such as clock skew and the need for high power clock drivers to generate the required global clock may result in large area and high dynamic power consumption. In contrast, asynchronous techniques eliminate the need for a global clock along with its associated drivers and offer a promising path to overcome many of the problems with synchronous design. While there are many different techniques and architectures that can be used to create asynchronous digital systems, Null Convention Logic is considered one of the more effective methods due to its straightforward “structural” approach to design, being based on a predefined library of majority logic (threshold) gates. Just as for any other asynchronous digital design technique, Null Convention Logic eliminates the need for a high frequency global clock, replacing it with localised handshaking signals. This may lead to lower power consumption in some circumstances and the gate library approach does not require the sort of complicated timing analysis required by other methodologies, including synchronous. A Null Convention Logic design can therefore be “correct by construction”, with its overall performance adjusting automatically to suit changes in operating conditions due to process variability, supply voltage and/or temperature. On the other hand, there are various drawbacks. Null Convention Logic relies on multi-rail signals, where each individual logic bit can be represented by a dual or quad-rail, two or four wires respectively. While multi-rail logic in NCL may simplify path logic in some cases, it invariably results in greater area and also supports the generation of illegal states. For instance, in both dual-rail and quad-rail systems, the rails must be mutually exclusive, such that they can never be asserted simultaneously. This type of illegal state may occur within high speed, low power system on chip (SOC) implementations due to system noise or delays caused by variable interconnection lengths or unbalanced fanouts. iii This research proposes and analyses the concept of using single-rail, ternary logic to represent the three levels required to define Null Convention Logic i.e., Data-One, Null and Data-Zero. The architecture is implemented using two different CMOS technology processes and voltage level mappings to demonstrate that is largely technology independent. Two different versions are presented in this work: register-controlled and register-less ternary. The more conventional register controlled ternary NCL system relies on the use of the ternary delay insensitive registers to control the flow of the data in the pipeline. The “register-free” implementation eliminates the additional pipeline registers, which helps to reduce both the total design area as well as its power consumption. Both designs propagate data only and do not need to propagate Null thereby enhancing the performance of the design by eliminating the Null cycle propagation. A representative example of a Short Word Length Digital Finite Impulse Response Low Pass Filter is used to demonstrate that the Single-Rail Ternary Logic approach can be used to design and implement a sophisticated NCL system. The system was designed and implemented at the CMOS transistor level and the three alternative architectures, dual-rail Binary Logic NCL, register-controlled Single-Rail Ternary Logic NCL and register-less Single-Rail Ternary Logic NCL, were compared in terms of total design area, power consumption and design performance. The register-less ternary NCL example system exhibited an approximately 30% reduction in both area and propagation delay, at the cost of a significant increase in power compared to dual rail binary NCL. The register-less ternary system has reduced both power consumption and design area by almost 2.5% and 8% respectively compared to the register-controlled ternary version. These comparisons indicate that both register-controlled and register-less Single-Rail Ternary Logic NCL can reduce the design area, as each signal is represented by only one wire, and at the same time can enhance system performance. However, as the conventional dual-rail Binary Logic NCL still exhibits much lower overall power consumption, the main advantage of the two proposed Single-Rail Ternary Logic NCL architectures are their slightly higher performance and the elimination of illegal state that can otherwise occur. They also offer a means to save area where this is a key design parameter. iv Acknowledgements I would like to express my sincere gratitude to my supervisor Professor Paul Beckett for his continuous support and being always available. His door was always open and without his guidance I couldn’t have finished this thesis. As a Part-Time PhD student, I experienced many unexpected hurdles while doing my PhD and sometimes it was difficult to keep my spirits high, but my supervisor’s patience and enthusiasm motivated me to complete and finish this research. One of my biggest challenges was changing my study load from a full-time research student to a part-time one due to family circumstances and therefore giving up my full-time scholarship. Part-time research students always have to juggle a research degree with a professional career, and I was no exception. Whilst my career requires lots of continuous self-development and self-learning due to the rapid rate of technology change, it was still a big challenge to be able to allocate the necessary time every week to focus on my research degree. Accessing the simulation tools remotely over the internet was always a challenge, especially when I had to relocate interstate and the simulator performance was slow and therefore getting the required results was taking longer than expected. However, even while I was interstate, my supervisor always made himself available and was able to attend our fortnightly meeting either on Skype or on the phone. My sincere thanks also go to RMIT University for offering me the scholarship including all the academic and administrative staff for all their great work and support. Last, but by no means least, I would like to sincerely thank my wife Lucy and my daughter Scarlett for their love, support, immense encouragement and for ultimately being very understanding about what I was going through and for putting up with my absence for many nights and weekends. v Contents Declaration ...................................................................................................................................... ii Abstract .......................................................................................................................................... iii Acknowledgements .......................................................................................................................... v List of Figures .................................................................................................................................. ix List of Tables .................................................................................................................................. xii CHAPTER 1: INTRODUCTION ....................................................................................... 1 1.1 Introduction ............................................................................................................................ 1 1.2 Research Motivation and Purpose .......................................................................................... 2 1.3 Research Questions................................................................................................................. 4 1.4 Publication arising from this work........................................................................................... 5 1.5 Introduction to the key concepts used in this work ................................................................. 5 1.5.1 Delay Insensitive Implementation using NCL ....................................................................... 6 1.5.2 Multi Threshold CMOS ....................................................................................................... 11 1.6 Novel contributions and outcomes ......................................................................................