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Simulating a Balanced Ternary Ripple Carry Adder in Systemc: an Overview of an Under-Represented Radix

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Simulating a Balanced Ternary Ripple Carry Adder in Systemc: an Overview of an Under-Represented Radix Bachelor Informatica Simulating a balanced ternary ripple carry adder in SystemC: an overview of an under-represented radix Brasso Kattenberg June 16, 2020 Informatica | Universiteit van Amsterdam Supervisor(s): Anthony van Inge Signed: Signees Abstract Binary computers are ubiquitous, but progress is slowing down. [23] This paper poses the balanced ternary base as an alternative and evaluates its merits as compared to binary with regards to transistor usage, and therefor latency, power usage; and construction complexity. A ternary trit represents more information than a binary bit by a factor of roughly 1.58. An overview of the timeline of this particular signed-digit base is given, as well as a comparison between binary and (balanced) ternary adder circuits. A balanced ternary ripple carry adder is simulated using SystemC to aid the evaluation. Quote Your computer uses ones and zeros to represent data. There's no real reason for be the basic unit of information in a computer to be only a one or zero, though. It's a historical choice that is common because of convention, like driving on one side of the road or having right-hand threads on bolts and screws. In fact, computers can be more efficient if they're built using different number systems. Base 3, or ternary, computing is more efficient at computation and actually makes the design of the computer easier. (...) Hackaday 2 Contents 1 Introduction 5 1.1 Research questions . .6 2 Timeline overview of past pursuits 7 3 Theoretical advantages of the balanced ternary radix 11 3.1 Radix economy . 11 3.1.1 Positional numeral system . 11 3.1.2 Ideal radix . 11 3.2 Negative numbers and representation . 12 3.3 Truncating-rounding equivalence . 12 3.4 Addition and multiplication tables . 13 3.5 Extra: calculating to and from balanced ternary . 13 4 Balanced Ternary logic 14 4.1 Single-input gates . 14 4.2 Dual-input gates . 14 5 Simulating a balanced ternary ripple carry adder 16 5.1 Making the choice for simulation with SystemC . 16 5.2 Balanced ternary ripple carry adder: design . 17 6 Balanced ternary gate design 19 6.1 Types of MOSFET . 19 6.2 Balanced ternary gates . 19 6.2.1 Substituting the any-gate . 19 6.3 Binary MOSFET-based gates . 20 7 Results and discussion 25 7.1 Simulation results . 25 7.2 Critical paths . 26 7.2.1 Binary critical path . 26 7.2.2 Balanced ternary critical path . 26 7.2.3 Comparison . 26 7.2.4 Delay: number of MOSFETs and OpAmps . 27 7.3 Component cost . 27 7.3.1 Total binary ripple carry adder cost . 27 7.3.2 Total balanced ternary ripple carry adder cost . 27 7.4 Sublinear addition . 28 3 8 Conclusions and future research 29 8.1 Latency . 29 8.2 Component count . 29 8.3 Final thoughts . 29 8.3.1 Logic levels and supply voltage . 30 8.4 Closing remarks . 30 4 CHAPTER 1 Introduction Moore's law is a well-known indication of computing capability progress. For years, Moore's law has been said to have ceased to apply, and various metrics have shown to be flat-lining. [23] Furthermore, semiconductor fabrication facilities are having increasing difficulty to advance production of ever smaller transistors. At the same time, the power efficiency benefits the industry is accustomed to with every smaller production node is decreasing as well, primarily due to increased leakage current and parasitic electrical effects at smaller scales. The increased density exacerbates issues such as interference, quantum tunnelling. Even endurance is at stake; life expectancy was long considered a non-issue, usually electrical lifespan far outstrips practical lifespan. [5] Furthermore, the high resolution required for the small-size components result in requiring multiple passes in the masking process, increasing manufacturing time, cost, and error-margin. Current chip production is impressively small; since the 1970s device fabrication has improved 3 orders of magnitude: from 10 micrometer (1∗10−5) to around 10 nanometer (1∗10−8). TSMC and Samsung currently produce 7nm chips, and have 5nm and 3nm on their roadmaps for the next two years. Past assumptions of physical 'hard' limits have been proven pessimistic as evidenced by these achievements, but these sizes are nearing the size of a silicon atom which has a atomic radius of 111 picometer, making its diameter 0.222 nanometer. Efforts to alleviate the problems of going ever smaller the industry are trying different materials than silicon, such as graphene; expanding chips from planar to using the third dimension which presents additional challenges with heat removal and tracing inter-planar connections. All-in-all, with all the problems the industry faces and the seemingly impending crossroads the computer technology will arrive at, now might be an opportune moment to re-evaluate alternative avenues other than the aforementioned electrical engineering or materials science. Why not take another look at the literal basis of computing: the radix we use for number representation? Binary is fairly ideal in a number of aspects: simplicity, noise-resilience, etc. However the ternary radix |in particular the balanced ternary radix| has several distinct advantages. log(3) • Trits represent log(2) ≈ 1:58 more information than bits. • Balanced radices have native representation of negative numbers, obviating the need for complement notation • Balanced radices present equivalence in truncating and rounding fractions. • The ternary radix is the closest integer base to Euler's number Such claims warrant investigation, as is done by numerous parties over time indicating recurring interest, there must be good reasons that compelled all these efforts. They are briefly mentioned in the next chapter before this paper will go into each of these aforementioned advantages, culminating in a discussion of arithmetic properties and aided by a simulated balanced ternary ripple carry adder. 5 1.1 Research questions Based on these claims, the following research questions- and sub questions have been formulated to investigate, which will be elaborated on in later sections 1. Can a (balanced) ternary architecture be more efficient than a binary equivalent? (a) What latency would a (balanced) ternary adder have? i. What is the critical path for a balanced ternary ripple carry adder? ii. What is the critical path for a binary ripple carry adder? iii. Is a sub-linear complexity ternary adder possible? (b) What effect does a (balanced) ternary radix have on component count? 6 CHAPTER 2 Timeline overview of past pursuits Chronologically, the earliest suggested [13] appearance of signed digit arithmetic is in the Hindu Vedic texts known as the Vedas from the Vedic period (India, 1500-500 BCE) [6] Balanced ternary specifically is mentioned in the 1544 Arithmetica Integra by Michael Stifel. [27] There the numbers 1-40 are represented as sums of (positive and negative) powers of three; indicating counting with balanced ternary. Charles Babbage's place in the history of computing is fairly well-known, with the designs he made for his difference engine (1822) and analytical engine (1837). [8] Babbage was ahead of his time, the difference engine was built over a century later in 1991 by the London Science Musuem, decades after the first electronic computers. https://en.wikipedia.org/wiki/Analytical_ Engine The Analytical engine was never built, but efforts into researching and potentially building the turing-complete design started in 2010 led by John Graham-Cumming. Unfortunately, the early digital computer pioneers (ENIAC) were unaware of Babbage's efforts and as such several architectural innovations had to be re-invented. Lesser-known than Charles Babbage is Thomas Fowler, who invented and built a wooden computer based on the balanced ternary numeral system. His machine did not survive, but a replica was built in 1999-2000. [12] [30] Figure 2.1: Fowler's machine. stained glass window, St. Michaels Church [Torrington, Devon] Claude E. Shannon wrote in 1950 about balanced ternary (and other signed-digit symmetrical systems) [25] In 1952, Grosch proposed using balanced ternary for the Whirlwind II project. [21] [22] [10] 7 Figure 2.2: reconstruction of Fowler's machine, by Glusker, Vass & Hogan In 1958, |the Sputnik-era| the Moscow State University led by Brusentsov built an electronic ternary computer called the Setun, named after a nearby river. [21] 50 machines were produced between 1959-1965. It was both economical (27,500 rubles) and reliable (17 years continuous operation, 3 components replaced in year 1) despite the sometimes harsh operating climates. It was also deemed power efficient but this was not quantified. [19] Heralded for its architectural simplicity, unfortunately it was constructed with two binary components for every trit. [7] Its successor the Setun-70 from 1970 can be considered the last ternary computer. [10] Figure 2.3: original Setun 1958 8 Figure 2.4: Setun, serially produced model Figure 2.5: Setun-70 In 1969, Donald Knuth wrote in 'the art of computer programming' about balanced ternary calling it "perhaps the prettiest number system of all". [17] In 1973, Gideon Frieder at the State University New York, Buffalo implemented the TERNAC, an emulation in FORTRAN to validate the feasibility of a ternary computer. It featured both fixed and floating point arithmetic. It was deemed successful, the speed and price was in the order of binary computers. [11] [22] [10] 9 In 2014 Jessie Tank started working on a FPGA implementation of a balanced ternary cpu [28] which she presented on in 2016 [29] Simultaneously Tank is involved in the cryptocurrency IOTA, which launched
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