Hi3716m V310 Brief Data Sheet

Hi3716M V310

Triple-Play Translation HD Interactive STB Solution

Key Specifications CPU Graphics Processing z High-performance ARM Cortex A9 processor z Enhanced full-hardware TDE z Dual-core service processing mechanism z Full-hardware anti-aliasing and anti-flicker z Built-in I-cache, D-cache, and L2 cache z Hardware Java acceleration Display Processing z Floating-point coprocessor z 3-layer OSDs z 16-bit or 32-bit color depth Memory Control Interfaces z Two background layers and two video layers z DDR3/DDR3L interface z 1920-pixel width for each layer − Maximum 512 MB z Image enhancement − 16-bit memory Audio/Video Interfaces z SPI flash interface z PAL, NTSC, and SECAM standard output, and forcible z NAND flash interface standard conversion z SPI NAND flash interface z Aspect ratio of 4:3 or 16:9, forcible aspect ratio conversion, HiVXE Video Decoding Engine and free scaling z H.264 MP, [email protected] z 1080p50(60)/1080i/720p/576p/576i/480p/480i outputs z AVS [email protected] z SD and HD signal reception z AVS+ z HD and SD outputs from the same source or two different z MPEG1 sources z MPEG2 MP@HL z xvYCC (IEC 61966-2-4) standard for color gamut z MPEG4 SP@L0−3, ASP@L0−5 z HDMI 1.4 with HDCP 1.2 z VC-1 AP z Analog video interfaces z VP6 and VP8 − One CVBS interface z 1080p@30 fps real-time decoding − One YPrPb interface z Video post-processing such as denoising and deblocking − One S-Video interface Image Decoding − Four embedded VDACs z JPEG decoding, maximum 64 megapixels − Configurable output interfaces z PNG decoding, maximum 64 megapixels − Rovi Audio Decoding − VBI z MPEG L1/L2 decoding z Audio interfaces z Dolby Digital and Dolby Digital Plus decoding, and Dolby − Audio-left and audio-right channels: RCA, Digital Plus transcoding low-impedance, and unbalanced output interfaces z Dolby Digital transparent transmission − SPDIF interface z DTS core decoding − One embedded ADAC z DTS transparent transmission z DRA Peripheral Interfaces z Downmixing z Two USB 2.0 host ports, integrated with the PHY z Resampling z Two 10/100 Mbit/s adaptive Ethernet ports and one z 2-channel audio mixing embedded 100 Mbit/s PHY, supporting layer 2 and layer 3 z Intelligent volume control switching z One UART interface TS Demultiplexing/PVR z One smart card interface, supporting T0, T1, and T14 z Two TS inputs, and one IF input protocols z Maximum 96 hardware PID filters z One IR receiver with two input interfaces z DVB-CSA2, AES, and DES descrambling algorithms z One LED and keypad control interface z Full-service PVR z Two I2C interfaces z Recording of scrambled and non-scrambled streams z Five groups of GPIO interfaces Channel Decoding Low-power consumption z One embedded QAM, compliant with the ITU J83-A/B/C z passive standby, Less than 0.5 W standby power standards consumption of the STB z One QAM loopback output z Less than 5 W typical working power consumption of the Security Processing STB z Advanced security CA Others z Downloadable CA z Fast startup z OTP and chip ID z Boot program download and execution over a serial port z AES, DES, and 3DES data encryption z QFP or PBGA package z Content protection for USB devices z 2-layer PCB z Data protection for DDR SDRAMs

Copyright © HiSilicon Technologies Co., Ltd. 2014. All rights reserved. Manufacture Center of Huawei Electrical, Huawei Base, Bantian, Longgang District, Shenzhen, P. R. China Postal Code: 518129 www.hisilicon.com Issue: 00B03 1 Date: 2014-11-26 Hi3716M V310

Triple-Play Translation HD Interactive STB Solution

Functional Block Diagram

z DTS, mentioned in this document, is a registered trademark of DTS Inc. and its subsidiaries. Any parties intending to use the trademark must obtain the permission from DTS Inc. or its subsidiaries. z Dolby, mentioned in this document, is a registered trademark of Dolby Laboratories, Inc. Any parties intending to use the trademark must obtain the permission from Dolby Laboratories, Inc.

Acronyms and Abbreviations ADAC audio digital-to-analog converter AES advanced encryption standard AVS audio video standard BOM bill of material CA conditional access CVBS composite video broadcast signal DES data encryption standard DHCP Dynamic Host Configuration Protocol DRA dynamic resolution adaptation EPG electronic program guide GPIO general-purpose input/output GPU graphics processing unit HDMI high-definition multimedia interface I2C inter-integrated circuit IR infrared I2S inter-IC sound JPEG Joint Photographic Experts Group MJPEG Motion Joint Photographic Experts Group MPEG Moving Picture Experts Group Copyright © HiSilicon Technologies Co., Ltd. 2014. All rights reserved. Manufacture Center of Huawei Electrical, Huawei Base, Bantian, Longgang District, Shenzhen, P. R. China Postal Code: 518129 www.hisilicon.com Issue: 00B02 2 Date: 2014-10-30 Hi3716M V310

Triple-Play Translation HD Interactive STB Solution

NTSC National Television System Committee PBGA plastic ball grid array PCB printed circuit board PID packet identifier QFP quad flat package SCI smart card interface SPDIF Sony/Philips digital interface SPI serial peripheral interface STB set-top box TDE two-dimensional engine UART universal asynchronous receiver transmitter VBI vertical blanking interval VDAC video digital-to-analog converter