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Mesfets – Gaas and Inp

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Mesfets – Gaas and Inp Metal-Semiconductor Interfaces • Metal-Semiconductor contact • Schottky Barrier/Diode • Ohmic Contacts • MESFET UMass Lowell 10.523 - Sanjeev Manohar Device Building Blocks UMass Lowell 10.523 - Sanjeev Manohar UMass Lowell 10.523 - Sanjeev Manohar Energy band diagram of an isolated metal adjacent to an isolated n-type semiconductor UMass Lowell 10.523 - Sanjeev Manohar Energy band diagram of a metal-semiconductor contact in thermal equilibrium. UMass Lowell 10.523 - Sanjeev Manohar Measured barrier height for metal-silicon and metal-gallium arsenide contacts UMass Lowell 10.523 - Sanjeev Manohar Energy band diagrams of metal n-type and p-type semiconductors under thermal equilibrium UMass Lowell 10.523 - Sanjeev Manohar Energy band diagrams of metal n-type and p-type semiconductors under forward bias UMass Lowell 10.523 - Sanjeev Manohar Energy band diagrams of metal n-type and p-type semiconductors under reverse bias. UMass Lowell 10.523 - Sanjeev Manohar Charge distribution electric-field distribution UMass Lowell 10.523 - Sanjeev Manohar Depletion Layer ρ = −qND 0 < x < W ρ qN ∇2V = = − D εs εs dE qN ∇E = = − D dx εs qN E(x) = D (W − x) εs UMass Lowell 10.523 - Sanjeev Manohar WW qND Vbi −V = ∫∫E(x)dx = (W − x)dx 00εs qN 0 qN W 2 = D ∫(W − x)d(W − x) = D εs W 2εs Depletion width W = 2εs (Vbi −V)/ qNq D Charge per unit area Q = QNDW = 2qεsND (Vbi −V) UMass Lowell 10.523 - Sanjeev Manohar Capacitance ∂Q qε N ε Per unit area: C = = s D = s ∂V 2(Vbi −V ) W Rearranging: 1 2(Vbi −V ) 2 = C qεsND Or: ⎡ ⎤ 2 ⎢ − 1 ⎥ ND = qε ⎢d 1 / dV ⎥ s ⎣ ( C 2 ) ⎦ UMass Lowell 10.523 - Sanjeev Manohar 1/C2 versus applied voltage for W-Si and W-GaAs diodes UMass Lowell 10.523 - Sanjeev Manohar 1/C2 vs V •If straight line – constant doping profile – slope = doping concentration •If not straight line, can be used to find profile •Intercept = Vbi can be used to find φBn φBn = Vn +Vbi kT ⎛ ND ⎞ Vn = ln⎜ ⎟ q ⎝ ni ⎠ UMass Lowell 10.523 - Sanjeev Manohar Current transport by the thermionic emission process Thermal equilibrium forward bias reverse bias UMass Lowell 10.523 - Sanjeev Manohar Thermionic emission Number of electrons with enough thermal energy to overcome barrier: ⎛ −qφ ⎞ ⎜ Bn ⎟ ⎝ kT ⎠ nth = NCe At thermal equilibrium, current going both ways is the same: ⎛ −qφ ⎞ ⎜ Bn ⎟ ⎝ kT ⎠ jm→s = js→m = C1NCe UMass Lowell 10.523 - Sanjeev Manohar Forward Bias Barrier for electrons in semiconductor is reduced by VF ⎛ −(qφ −V ) ⎞ ⎜ Bn F ⎟ ⎝ kT ⎠ nth = NCe Barrier for electrons from metal to semiconductor is the same Net current: ⎛ −q(φ −V ) ⎞ ⎛ −qφ ⎞ ⎜ Bn F ⎟ ⎜ Bn ⎟ ⎝ kT ⎠ ⎝ kT ⎠ j = js→m − jm→s = C1NCe − C1NCe ⎛ −qφBn ⎞ qV ⎜ ⎟ ⎛ F ⎞ j C N e⎝ kT ⎠ ⎜e kT 1⎟ = 1 C ⎜ − ⎟ ⎝ ⎠ C N = A *T 2 1 C UMass Lowell 10.523 - Sanjeev Manohar Forward Bias ⎛ qV ⎞ j j ⎜e kT 1⎟ = s ⎜ − ⎟ ⎝ ⎠ −qφBn 2 kT js = A *T e 4πqm * k 2 Effective Richardson Constant A* = e h3 Derive by determining current with integral of velocity and density of states j = ∫v(E)dN(E) = ∫v(E)g(E)f (E)dE UMass Lowell 10.523 - Sanjeev Manohar Forward current density vs applied voltage of W-Si and W-GaAs diodes UMass Lowell 10.523 - Sanjeev Manohar Thermionic Emission over the barrier – low doping UMass Lowell 10.523 - Sanjeev Manohar Tunneling through the barrier – high doping UMass Lowell 10.523 - Sanjeev Manohar Tunneling through the barrier Narrow depletion width for high doping – tunneling From QM 101 : Wavefunction is exponential depending on barrier width and height probability of making it to the other side ~ ψ2 −iωt −αx 2m(U − E) Ψ(x,t) = e e α = 2 h 2 I ~ exp[− 2W 2m(qφBn − qV)/ h ] W = 2εs (Vbi −V)/ qND ⎡ ⎤ − C2 (φBn −V ) C = 4 mε / I ~ exp⎢ ⎥ 2 s h ND ⎣ ⎦ UMass Lowell 10.523 - Sanjeev Manohar Contact resistance Specific Contact Resistance(based on current density) −1 ⎛ ∂J ⎞ RC ≡ ⎜ ⎟ ⎝ ∂V ⎠ V =0 For tunneling current through barrier (high doping): ⎡− C2 (φBn −V )⎤ I ~ exp⎢ ⎥ ⎣ ND ⎦ ⎛C φ ⎞ Ohmic Contact: 2 Bn RC ~ exp⎜ ⎟ ⎝ ND h ⎠ UMass Lowell 10.523 - Sanjeev Manohar Calculated and measured values of specific contact resistance UMass Lowell 10.523 - Sanjeev Manohar MESFET UMass Lowell 10.523 - Sanjeev Manohar MESFET – Qualitative Operation •No gate voltage – depletion from built-in voltage •Positive drain voltage causes reverse bias •Increased depletion width with increased V L L R = ρ = A qμnNDZ(a −W ) UMass Lowell 10.523 - Sanjeev Manohar MESFET – Qualitative Operation At higher drain voltages, W=a – pinch off at VDsat 2 qN a2 qNDW D V −V = ⇒ VDsat = −Vbi bi 2ε 2εs s UMass Lowell 10.523 - Sanjeev Manohar MESFET – Qualitative Operation Above pinchoff voltage, drain current does not increase Voltage at pinch-off point is still Vdsat UMass Lowell 10.523 - Sanjeev Manohar MESFET – Qualitative Operation Addition of gate voltage (negative) increases baseline depletion width Pinch-off occurs sooner Saturation voltage and current are reduced (narrower channel) 2 qNDa VDsat = −Vbi −VG 2εs UMass Lowell 10.523 - Sanjeev Manohar I-V Characteristics – Linear Region IDdy dV = IDdR = qμnNDZ[a −W (y)] 2ε (V(y) +V +V ) W (y) = s G bi qND qN dV = D WdW εs UMass Lowell 10.523 - Sanjeev Manohar I-V Characteristics – Linear Region IDdy = qμnNDZ[a −W (y)]dV qND = qμnNDZ[a −W ] WdW εs 2 2 W2 q μnND ID = ∫(a −W )WdW Lεs W1 2 2 q μ N ⎡ 2 2 2 3 3 ⎤ I = n D a W −W − W −W D ⎢ ()2 1 ()2 1 ⎥ 2Lεs ⎣ 3 ⎦ UMass Lowell 10.523 - Sanjeev Manohar I-V Characteristics – Linear Region 2εs (VG +Vbi ) W1 = qND 2εs (VD +VG +Vbi ) W2 = qND 3 3 ⎡V 2⎛V +V +V ⎞ 2 2⎛V +V ⎞ 2 ⎤ I = I ⎢ D − ⎜ D G bi ⎟ + ⎜ G bi ⎟ ⎥ D P V 3 V 3 V ⎣⎢ P ⎝ P ⎠ ⎝ P ⎠ ⎦⎥ 2 2 3 Zμnq NDa IP ≡ 2εsL 2 qNDa VP ≡ 2εs UMass Lowell 10.523 - Sanjeev Manohar Normalized ideal current-voltage characteristics of a MESFET with VP = 3.2 V. UMass Lowell 10.523 - Sanjeev Manohar UMass Lowell 10.523 - Sanjeev Manohar Transconductance 3 3 ⎡V 2⎛V +V +V ⎞ 2 2⎛V +V ⎞ 2 ⎤ I = I ⎢ D − ⎜ D G bi ⎟ + ⎜ G bi ⎟ ⎥ D P V 3 V 3 V ⎣⎢ P ⎝ P ⎠ ⎝ P ⎠ ⎦⎥ In Saturation: VP = VD +VG +Vbi ⇒ VDsat = VP −VG −Vbi 3 3 ⎡V −V −V 2 ⎛V −V −V +V +V ⎞ 2 2 ⎛V +V ⎞ 2 ⎤ I = I ⎢ P G bi − ⎜ P G bi G bi ⎟ + ⎜ G bi ⎟ ⎥ Dsat P V 3 V 3 V ⎣⎢ P ⎝ P ⎠ ⎝ P ⎠ ⎦⎥ 3 ⎡ ()V +V 2 2⎛V +V ⎞ 2 ⎤ I = I ⎢1− G bi − + ⎜ G bi ⎟ ⎥ Dsat P V 3 3 V ⎣⎢ P ⎝ P ⎠ ⎦⎥ 3 ⎡1 ()V +V 2⎛V +V ⎞ 2 ⎤ I = I ⎢ − G bi + ⎜ G bi ⎟ ⎥ Dsat P 3 V 3 V ⎣⎢ P ⎝ P ⎠ ⎦⎥ UMass Lowell 10.523 - Sanjeev Manohar Transconductance 3 ⎡1 (V +V ) 2⎛V +V ⎞ 2 ⎤ I = I ⎢ − G bi + ⎜ G bi ⎟ ⎥ Dsat P 3 V 3 V ⎣⎢ P ⎝ P ⎠ ⎦⎥ ∂ID gm = ∂VG VD 1 2 3 −3 1 ⎡ 2 2 ⎤ gm = IP ⎢0 − + * ()VP ()VG +Vbi ⎥ ⎣ VP 3 2 ⎦ IP ⎛ VG +Vbi ⎞ gm = ⎜1− ⎟ VP ⎝ VP ⎠ 2ZμnqNDa ⎛ VG +Vbi ⎞ gm = ⎜1− ⎟ L ⎝ VP ⎠ UMass Lowell 10.523 - Sanjeev Manohar Equivalent Circuit - High Frequency AC • Input stage looks like capacitances gate-to-channel • OtOutput capacit ances i gnored -didrain-to-source capacitance small UMass Lowell 10.523 - Sanjeev Manohar Maximum Frequency (not in saturation) •Ci is capacitance per unit area and Cgate is total capacitance of the gate Cgate = Ci ZL •F=fmax when gg(ain=1 (iout/iin=1) gm fmax = 2πCgate ⎛ εS ⎞ Cgate = ZL⎜ ⎟ ⎝W ⎠ 2ZμnqNDa μ qN a2 f ≈ L = n D max ⎛ ε ⎞ 2πL2ε 2πZL⎜ S ⎟ s W ⎝ ⎠ UMass Lowell 10.523 - Sanjeev Manohar Velocity Saturation Drain current: ID = A * qnυs = Z(a −W )qNDυs Transconductance ∂ID ∂ID ∂W Zυs εs gm = = = ∂VG ∂W ∂VG W Cutoff Frequency: gm fmax = 2πCgate Zυs εs /W εS fmax = = 2πZL()ε /W 2πL UMass Lowell 10.523 - Sanjeev s Manohar Figure 7.15. The drift velocity versus the electric field for electrons in various semiconductor materials. UMass Lowell 10.523 - Sanjeev Manohar III-V MESFETs – GaAs and InP +Semi-insulating material – high speed devices (like built-in SOI) +High Electron Mobility/Saturation Velocity – high speed +Direct Bandgap – photonic devices +Heterostructures – bandgap engineering -No Simple Oxides – MOSFETS not viable – no equivalent to SiO2 UMass Lowell 10.523 - Sanjeev Manohar III-V Transistors: GaAs No simple oxides for GOX – MOSFETS not widely used MESFET structure more common – mesa structure depletion mode transistor Gate Source Drain Semi-insulating Substrate UMass Lowell 10.523 - Sanjeev Manohar Depletion Mode GaAs MESFET •N-type material – high electron mobility •Mesa etch for isolation on SI substrate •Ohmic contacts for Source and Drain – alloyed •Shottky contact for Gate – Ti •Recessed gate – depth determines threshold UMass Lowell 10.523 - Sanjeev Manohar GaAs MESFET Fabrication Si Implant Si3N4 Semi-insulating GaAs Substrate Deposit Si 3N4 layer, implant Si and anneal for form n-type material Can also grow n-type epi layer by MBE or MOCVD UMass Lowell 10.523 - Sanjeev Manohar N-type GaAs Semi-insulating GaAs Substrate Ohmic contact formation for source and drain – NiAuGe evaporate Au(88wt%)Ge(12wt%) then Ni (+Au) anneal30l 30 m in a t450t 450°CiC in H2/N2 Au reacts with Ga from substrate – Ga vacancies Ge fills Ga vacancies – heavy n-tyygpe doping low contact resistance ohmic UMass Lowell 10.523 - Sanjeev Ge doping not uniform – spreading resistanceManohar effect Semi-insulating GaAs Substrate Gate Recess Etch Wet etching Channel depth determines pinch-off voltage Channel resistance can be monitored in-situ UMass Lowell 10.523 - Sanjeev Manohar Semi-insulating GaAs Substrate Mesa Recess Etch Wet etching Semi-insulating substrate for device isolation UMass Lowell 10.523 - Sanjeev Manohar Semi-insulatingSemi-insulating GaAs GaAs Substrate Substrate Shottky Gate Electrode deposition – Ti/Pt/Au or Ti/Pd/Au Almost any metal will form barrier Ga diffuses in many metals Ti –contact Pt or Pd barrier layer Au added for low resistivity UMass Lowell 10.523 - Sanjeev Manohar GaAs Digital Circuits: Direct Coupled FET Logic (DCFL) – lowest power and highest level of integration Uses enhancement and depletion mode transistors Enhancement mode transistors made using thinner gate recess or different doping to change threshold UMass Lowell 10.523 - Sanjeev Manohar DCFL Fabrication Sequence UMass Lowell 10.523 - Sanjeev Manohar DCFL Fabrication Sequence(cont.) UMass Lowell 10.523 - Sanjeev Manohar.
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