Compound Semiconductors on Si|icon For more than 2o years many millions of dol- semiconductor substrate. And, for some time lars have been spent for the growth of galli- the only compound semiconductor that um arsenide and other hetero-materials on showed promise was silicon-germanium, silicon for all the obvious reasons, larger, which does not quite present the same tech- cheaper and higher quality substrates avail- nology challenge, since both elements are in Dr Alan Mills able in quantity (mostly elemental Groups the same Group IV of the Periodic Table and PO Box 4098, Mountain View, IIl-V and II-Vl). Unfortunately most of it was therefore the silicon-germanium material CA 94o4o, USA spent producing either little success or a system may be classed as an alloy rather Tel/fax: +~-65o-968-~383/84~6 E-mail. [email protected] cost in excess of the competing compound than a compound. Compound Semiconductors on Silicon The results of combining these dissimilar materi- will purchase development services from IQE, a als are now in from several research groups and $10 million equity investment by Motorola in they are close to changing the outlook for these IQE, a $14 million three year equity draw down inter group, or hetero-epitaxial processes from facility for IQE and an additional $10 million pur- dim to very promising or even to almost com- chase of warrant options in IQE, extending over mercial, (based on the latest gallium arsenide and five years. gallium nitride on silicon process advances). As reported in III-Vs Review earlier this year, Gallium Arsenide Motorola and IQE have been cooperating to The Motorola process involves the use of high develop the deposition of MBE-grown gallium dielectric-constant oxide-interlayers, such as arsenide on silicon wafers for about one year. strontium titanate (STO), which inhibit reaction This cooperation between Motorola and IQE between the silicon and the epitaxially grown already includes a Custom Evaluation Agreement gallium arsenide layers. If electrical conductivity 2000/~ of a gallium arsenide seed layer are deposited to open to IQE and Motorola customers, a Service to the substrates is required, the STO layer can form a pseudo substrate and Cooperation Agreement in which Motorola be doped with concentrations of up to lOE19 atoms per cm3 of aluminium.The crystalline qual- ity of this STO on silicon is reported to be better than any single crystal STO currently available. Template layer required to prepare Gallium arsenide I/ the surface of STO to accept GaAs Originally, Motorola's interest in this technology was the creation of a compliant substrate for the deposition of epitaxial, high dielectric constant Single crystal STO provides the surface for growing GaAs oxide films on silicon for random access memory devices, a concept previously proposed in 1991 Amorphous SiO2 i~ Amorphous SiO2 layer formed by Cornell Professor, Y.H. Lo. during growth of STO on silicon. decouples the Si from the overlying One of the keys to this type of hetero-epitaxy Silicon substrate I GaAs - absorbs strain associated with and one of the processes developed by Motorola, lattice and temperature mismatch is the formation during growth of a thin silicon dioxide interlayer between the surface layer of III-Vs REVIEW THE ADVANCED SEMICONDUCTOR MAGAZINE VOL~5 - NO 4" MAY 2oo2 30 Compound Semiconductors on Silicon silicon and the mechanical support silicon wafer however, the 20A silicon dioxide layer originally produced in the process was unsuitable for Blurring the boundaries for next generation CMOS applications and has been replaced by an "system on a chip" • Optical • Large wafer STO layer.This thin oxide can be either amor- capabilities f sizes phous or crystalline, but it serves to take the • High speed Integrate the superior • Low cost • High • Volume O stress out of the surface silicon layer and allows electrical and optical > frequency performance of III-V manufacturing the growth of a low stress hetero-epitaxial layer semiconductors with the 02 on the surface. In the case of strontium titanate >, mature Silicon-based technology to create a interlayers, the optimised STO layers are new industry of i • High voltage integrated about 120 A thick, with the silicon dioxide inter- #-"0 • Mature integration semiconductor capability layer thickness reduced to 7 angstroms. circuits • Memories I Following the deposition of the STO layer, at • Microprocessors least 2000A of a gallium arsenide seed layer are Integration at the digital/electromagnetic deposited to form the pseudo substrate, suitable (computation/communications) interface for gallium arsenide device layer growth and pos- sibly other III-V materials on silicon. Rather fortu- itously, a thin silicon dioxide layer, which is com- products to a minimum.According to Thomas The best of both worlds pliant and forms between the silicon and the Hierl, the CTO of IQE plc, the process is produc- STO layer.The STO has a stable cubic structure tion capable, but development volumes are need- ed to corroborate the initial data for repro- above 70 ° Kelvin and it allows the stresses, the ducibility, yields and costs.With suitable demand, thermal interlayer mismatches and the associated scale up to production volumes would be possi- cracking to be eliminated. It also creates the pos- ble by Q1 2003. sibility for lattice engineering, which could be the enabler for new device structures. Currently, With deposition uniformities already similar to only solid sources are used in this MBE deposi- those attained from gallium arsenide on gallium tion process, requiring high temperature arsenide processes (homo-epitaxy), a ramp up to Knudsen Cells to produce the vapourised metals commercial volumes could be accomplished and good control of the gas injection, creating a within one year.The target price for the 6" galli- challenge for solid source MBE technology. um arsenide on silicon wafers is $200 for 6" diameter pseudo substrates versus a reported For process development, IQE used a Gen-2000 price of $300 for 6" gallium arsenide wafers MBE reactor with a 7 x 6" wafer capacity and although pseudo-wafer costs in the development separate III-V and oxide deposition chambers phase are believed to be in the $400 to $600 where the oxide inter-layer and the seed galli- um arsenide layer are grown separately.Various silicon substrate resistivities have been used and 1 tolO ohm-cm material can make good RF power Transistors RF devices. However, the higher resistivity Today's Power Amplifier NITRONEX (1000 to 5000 ohm-cm) float zone silicon sub- Transistors (made in silicon) GaN on Silicon strates may be preferable for high frequency + Limited RF Power ........... 6X to 15X devices, but they have not yet been evaluated. -- In~ufficiem Coverage A~a Power Process uniformities are good with the deposit- + Heat+driven Operating (.'o,ts ed STO layer thicknesses and GaAs MESFET • Ten, of Millions $US spent annual b ........... 2X across the wafer resistivities exhibiting better To Cool Ba~ $laliorls Efficiency than 1% uniformities. + St~lchcd Beyon+l Capahility To realize its low cost potential, a high volume • Highest Failu~ Rm¢ ol Any El~'trical ..... 4X process and product is needed that could pro- COl]iponel~t hi B['S Robustness (up to 50V) vide additional customer feed back.The key fac- * Marginal Signal Qualily tors to support a manufacturable process are Limited N~mix.t of U,crs ......... 3X stated to be minimal operator involvement, full in Coventge Area Linearity process computerization, accurate control of (would not need sidebands) material beams and process parameters and a COMPARATIVE PERFORMANCE nitride power transistors and amplifiers can easily need to keep device re-engineering for existing outperform silicon III-Vs REVIEW THE ADVANCED SEM ICONDUCTOR MAGAZINE VOL 15 - NO 4" MAY 2002 Compound Semiconductors on Silicon Motorola has formed a wholly owned sub- 10°] i i tG°.,0002,i sidiary, Thoughtbeam Inc., headed by Padmasree Warrior as General Manager.Although 'q / Thoughtbeam is an R&D operation without a fab, its goal is to combine the best of the III-V and the silicon worlds. Using the MBE grown :~ I,r "1,'~_SL+I pseudo substrates and depositing the active --E 10o~ SL'2 ~,~d ~llt& device layers by MOCVD, Motorola has already 10.~r~ ~ simula,ti°n compared the performance of their gallium -7.30 -7.25 -7.20 -7.15 30 32 34 36 38 arsenide on silicon FETs with similar gallium qx (l/rim) 20 (degree) arsenide based devices and shown them to have similar characteristics including, mobilities, satu- Reciprocal-space map around the GaN (20ff4) reflection (left) and (9-20 scan (righO show- rated velocities, gate/drain breakdown voltages, ing measurement and simulation. As can be clearly seen in the reciprocal space map the superlattice (5L) peaks are slightly shifted in qx with respect to the main GaN reflection indi- transconductances and RF performance. MES- cating a different a-lattice constant (vertical dashed line) but no relaxation (partial relaxation: FET power amplifiers based on this technology diagonal dashed line). The (9-2(9 scan shows, in addition to the superlattice peaks, Pendell~sungs fringes from the SL and the cap layer, indicating the high quality of the with equivalent power efficiencies have already InGaN/GaN interfaces. been evaluated in cellphone handsets in the Chicago area and were found to be indistin- guishable from those on gallium arsenide range. FETs have already been demonstrated wafers. Future plans include the testing of HBTs based on this process and it is now being and lasers. extended to heterobipolar-devices.To promote high interest levels and participation in their Gallium Nitride gallium arsenide on silicon technology and to reduce development costs for interested The potential for gallium nitride devices covers a parties, Motorola has agreed to allow interested wide range of application areas and includes companies to proceed with process develop- those listed below.