FCCM20 Endorsement

public class FullAdder extends Logic 4K series devices as it is the main device that we are using { in our applications3. This turned out to be only the first step /* Define the ports for a 1-bit full adder */ A CAD Suite for High- public static CellInterface cell˙interface[] = and many other significant changes were made to JHDL { Performance FPGA Design in(”a”, 1), in(”b”, 1), in(”cin”, 1), over the last year to accommodate those using JHDL as a out(”s”, 1), out(”co”, 1) Braddesign Hutchings, tool on Adaptive Peter Computing Bellows, Systems (ACS) appli- ; } Josephcations Hawkins, found in the DARPA Scott community. Hemmert, These changes were made to make JHDL easier to use, more terse, faster, public FullAdder(Wire a, Wire b, Wire ci, Wire s, Wire co) { Brentand Nelson, more general. Mike Rytting /* Connect wires to my ports */ In its current state, JHDL is a complete structural design connect(‘‘a’’, a); connect(‘‘b’’, b); connect(‘‘ci’’, ci); environment, including debugging, netlisting and other de- connect(‘‘s’’, s); connect(‘‘co’’, co); Yearsign of aids.publication: Circuits are described 1999 by writing Java code that Area:programmatically Languages and builds Compute the circuit via Models the JHDL libraries. /* Instantiate the logic functions */ Once constructed, these circuits can be debugged and ver- or o( and(a,b), and(a,ci), and(b,ci), co ); /* co is output */ xor o( a, b, ci, s ); /* s is output */ It's funnyified withhow the languages design browser, and tools a circuit get verification established, and de- spreadbugging and become tool. When standard the designer. For isdecades satisfied now, with the digital func- /* Map the gates to LUTs, and place. */ hardwaretionality in ASICs of the circuit, and FPGAs an EDIF 2.0has net-list been ofdesigned the circuit in can map( a, b, ci, s ); place( s, ‘‘R0C0.F’’ ); languagesbe generated originally and this defined can be for passed documentation to various backends for map( a, b, ci, co ); place( co, ‘‘R0C0.G’’ ); place and route (or just routing if the entire circuit has been (VHDL)manually and simulation placed). JHDL ( currently). supports ASIC e Xilinxngineers and HP } put upChess with [8]these devices. languages The remainder and the ofir thissynthesis paper will foibles now despitereport the onfact the neither current statuswas conceived of JHDL. or defined to be a design language.Figure. 1:We JHDL still Full use Adder the ASIC Example model and languages for FPGAs in FCCMs, even though FPGAs don't even have logic gates, and a "silicon turn" takes minutes. Out of a number of effortswe wereto escape explicitly from creating this and every design cell and every wire our- FPGA6s in JHDL FPGA Design terms, arguably Strategy the most successful was JHDL,selves. Thea landmark code almost in looksFPGA behavioral, design. and is quite easy to read and understand. Furthermore, the circuit descrip- JHDL startedJHDL isas a a structural design designtool for tool reconfigurable in which each circuit systems el- thattion change is platform-independent, over time, supporting because run we didn’t- specify a time andement partial is represented reconfiguration by a unique, as Java originally object. JHDLreported cir- in anparticular excellent library FCCM from 1998 which paper to select (with the gates. "JHDL"cuit in objects the title, inherit that from paper core classesis often that cited set up for the this netlist paper's work). JHDL's major impact came with fandurther simulation development model. Circuitsinto the are unified, created graphical by calling theFPGA Targetingtool suite platform-specificreported in this paper primitive. libraries constructor for the corresponding JHDL object and passing You designWire objects in JHDL as constructor by writing arguments a program to be in connected a well-known to language,This suggests Java an, using important library question: objects Now that JHDL for hardwarethe ports ofcomponents the circuit. For. JHDL example, is constructive a statement like andnew parametric.supports Higher some- levellevel of design device independence,and how then do instanceand specializationo(a, b, q) might createcomes a newnaturally 2-input from AND object with a and-orientedI targetprogramming my circuit. for Y aou particular construct platform? your The answer is designb aass inputsa hierarchy and q as of the objects output. instantiated We target a specific with FPGAconstructorthe parameters companion. to What Logic, you which write is the is TechMapperwhat class. you get,technology avoiding by pitfal selectingls and the uncertainty AND from the of rightsynthesis, library and providingAs illustrated fine in Figure control 2, theover Logic all classlevels uses a TechMap- per to select gates from the library that is currently be- of theof FPGA primitives implementation (e.g. new byucc.jhdl..XC4000.and, including placement. vs.This is particularly important for datapaths new byucc.jhdl..Flex10k.and). However, we found ing targeted. For example, when the full-adder construc- and computingthat this style applications of design tends where to be automated very tedious tools and ver-often failtor to (see fin Figured the 1)mappings calls the xor theo() designermethod, Logic asks the knowsbose the inFPGA practice; can therefore, realize. the Executing core structural your design Java class, programcurrent generates system its TechMapper netlist or toruns fetch its an xor gate. If the cur- simulation.Logic class, Since provides JHDL adesign quick-hardware and simulation API to build are cir-unified rentin a TechMappersimple graphical is a XC4000TechMapper, toolset, shifting it will go to the betweencuits editing efficiently. and Fortesting example, is ins wetant cananeous design. aIt 1-bit happens full- so fastXC4000 it's addictive library; similarly, and fun. a Flex10kTechMapper JHDL also 4 would makesadder it easy as shown to switch in Figure between 1. software simulation and hardwarego to its correspondingexecution in library.the same In othertool. words, for each Note specifically how we build the adder logic with method available in Logic, the TechMapper decides what BYU methodreleased calls, JHDL not constructors in open-source (e.g. or3(and(a,b), form, so it ...came co )). into widethe appropriate use by FCCM action isresearchers for its target and technology. This is a students.These BYU are methods faculty inherited and students from the provided Logic class strong that call supportpowerful through approach several that FPGA allows generations. much of the tedium and ver- A substantialthe appropriate number constructors of reconfigurable for us (they docomputing not evaluate projects a bositywere ofdeveloped structural design in JHDL, to be hiddenand it insidehad an intelligent a stronglogic influence function!). on Each high method-level returnsFPGA the and output FCCM wire desi for gn toolsTechMapper. to follow. Also, This because put it the in TechMapperthe top is a JHDL system-level property, the user can retarget an entire system tier ofthe FCCM new gate, citations which. allowsJHDL us is to one nest of these the methodmost important calls, and effective design methodologies to as shown in the example. Building circuits with nested for a new platform (well, those parts that were created with come methodout of the calls first makes twenty the code years much of FCCM. less verbose than if Logic methods) simply by changing the system TechMap- per before constructing the circuit. Mike Butts3At the time of the code rewrite, JHDL only supported the Xilinx 6200. RIP. 4Altera is not currently supported in JHDL. DOI: http://dx.doi.org/10.1109/FPGA.1999.803663