EL68E Sistemas Embarcados

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EL68E Sistemas Embarcados EL68E Sistemas Embarcados Prof. Douglas RENAUX © Prof. Dr. Douglas Renaux Arquitetura ARM Prof. Douglas RENAUX © Prof. Dr. Douglas Renaux ARM – Histórico Ano Evento Desenvolvimento do primeiro RISC comercial na Acorn Computers Ltd (Cambridge – UK) 1984-1985 ARM = Acorn RISC Machine 1990 Fundação da ARM (Advanced RISC Machines Ltd.) 1995 ARM7TDMI Desenvolvimento do ARM8 em conjunto com a DEC 1996-1998 (adquirida pela Intel que fez o StrongARM) 1997 ARM9 1999 ARM10 2003 ARM11 2005 Cortex M3, R4, A8 2007 Cortex A9 – Multicore 2012 Arquitetura v8 – 32/64 bits (Cortex A50) 2014 Cortex M7 – pipeline superescalar © Prof. Dr. Douglas Renaux Acorn BBC Micro 1981 © Prof. Dr. Douglas Renaux Developer Acorn Computers Type 8-bit home computer Release date 1 December 1981 Retail availability 12 years Introductory price £235 Model A, £335 Model B (in 1981) Discontinued 1994 Units sold over 1.5 million Media Cassette tape, floppy disc (optional), hard disc (rare), Laserdisc (BBC Domesday Project) Operating system Acorn MOS Power 50 W CPU 2 MHz MOS Technology 6502/6512 Storage capacity 100–800 kB (DFS) 160–1280 kB (ADFS floppy discs) 20 MB (ADFS hard disc) Memory 16–32 kB (Model A/B) 64–128 kB (Model B+) 128 kB (Master) Plus 32–128 kB ROM, expandable to 272 kB Display PAL/NTSC, UHF/composite/TTL RGB Graphics 640×256, 8 colours (various framebuffermodes) 78×75, 8 colours (Teletext) Sound Texas Instruments SN76489, 4 channels, mono TMS5220 speech synthesiser with phrase ROM (optional) Input Keyboard, twin analogue joysticks with fire buttons, lightpen Connectivity Printer parallel, RS-423 serial, user parallel,Econet (optional), 1 MHz bus, Tube second processor interface © Prof. Dr. Douglas Renaux Acorn Archimedes - 1987 © Prof. Dr. Douglas Renaux ARM Typical MIPS @ ARM Family ARM Core Feature Arch. MHz ARM1 ARMv1 ARM1 First implementation ARMv2 added the MUL (multiply) 4 MIPS @ 8 MHz ARMv2 ARM2 instruction 0.33 DMIPS/MHz ARM2 Integrated MEMC (MMU), Graphics ARMv2a ARM250 and IO processor. ARMv2a added the 7 MIPS @ 12 MHz SWP and SWPB (swap) instructions. 12 MIPS @ First integrated memory cache. ARM3 ARMv2a ARM3 25 MHz 4 KB unified 0.50 DMIPS/MHz ARMv3 first to support 32-bit memory 10 MIPS @ ARM60 address space (previously 26-bit) 12 MHz As ARM60, cache and coprocessor bus 28 MIPS @ ARM600 ARM6 ARMv3 (for FPA10 floating-point unit). 33 MHz 17 MIPS @ ARM610 As ARM60, cache, no coprocessor bus. 20 MHz © Prof. Dr. Douglas Renaux 0.65 DMIPS/MHz ARM700 40 MHz ARM7 ARMv3 ARM710 As ARM700, no coprocessor bus. 40 MHz 40 MHz ARM710a As ARM710 0.68 DMIPS/MHz 15 MIPS @ 16.8 MHz ARM7TDMI(-S) 3-stage pipeline, Thumb 63 DMIPS @ 70 MHz As ARM7TDMI, cache 8 KB unified, ARM710T 36 MIPS @ 40 MHz ARM7TDMI ARMv4T MMU As ARM7TDMI, cache 8 KB unified, ARM720T 60 MIPS @ 59.8 MHz MMU ARM740T As ARM7TDMI, MPU 5-stage pipeline, Thumb, Jazelle DBX, ARM7EJ ARMv5TEJ ARM7EJ-S Enhanced DSP instructions © Prof. Dr. Douglas Renaux Pipeline Fonte: ARM © Prof. Dr. Douglas Renaux ARM Cortex © Prof. Dr. Douglas Renaux ARM Cortex © Prof. Dr. Douglas Renaux © Prof. Dr. Douglas Renaux ARM Cortex © Prof. Dr. Douglas Renaux © Prof. Dr. Douglas Renaux Microcontroller profile, most Thumb + some Optional cache, Cortex- Thumb-2,[10] hardware multiply instruction 0.84 no TCM, no M0[9] (optional small), optional system timer, optional DMIPS/MHz MPU bit-banding memory Microcontroller profile, most Thumb + some Optional cache, Cortex- Thumb-2,[10] hardware multiply instruction no TCM, 0.93 M0+[11] (optional small), optional system timer, optional optional MPU DMIPS/MHz ARMv6-M bit-banding memory with 8 regions 136 DMIPS Microcontroller profile, most Thumb + some Optional cache, @ Thumb-2,[10] hardware multiply instruction 0-1024 KB I- 170 MHz,[13]( Cortex- Cortex- (optional small), OS option adds SVC / banked TCM, 0- 0.8 DMIPS/M M M1[12] stack pointer, optional system timer, no bit- 1024 KB D- Hz FPGA- banding memory TCM, no MPU dependent)[1 4] Optional cache, Microcontroller profile, Thumb / Thumb-2, Cortex- no TCM, 1.25 ARMv7-M hardware multiply and divide instructions, M3[15] optional MPU DMIPS/MHz optional bit-banding memory with 8 regions Microcontroller profile, Thumb / Thumb-2 / DSP / Optional cache, 1.25 Cortex- optional VFPv4-SP single-precision FPU, no TCM, ARMv7E-M DMIPS/MHz M4[16] hardware multiply and divide instructions, optional MPU (1.27 w/FPU) optional bit-banding memory with 8 regions ARM ARM Family ARM Core Feature Cache (I/D), MMU Typical MIPS @ MHz Architecture © Prof. Dr. Douglas Renaux Thumb-2 Densidade de código melhora em até 35% em relação ao código ARM. Thumb-2: “melhor de dois mundos” independe de código ARM © Prof. Dr. Douglas Renaux Fonte: ARM © Prof. Dr. Douglas Renaux Baixo Custo x 8 bits © Prof. Dr. Douglas Renaux • http://www.embedded-systems.com/underthehood/210101486 © Prof. Dr. Douglas Renaux © Prof. Dr. Douglas Renaux © Prof. Dr. Douglas Renaux ARMv8-A (64 bits) © Prof. Dr. Douglas Renaux © Prof. Dr. Douglas Renaux © Prof. Dr. Douglas Renaux © Prof. Dr. Douglas Renaux © Prof. Dr. Douglas Renaux Exynos 5250 com Cortex-A15 dual core © Prof. Dr. Douglas Renaux © Prof. Dr. Douglas Renaux 64-bits - AMD Hierofalcon will pack four to eight 64-bit ARM A57 cores clocked up to 2GHz. In addition to new ARM cores, the 28nm chips also feature 10Gbit Ethernet and PCI Express 3.0 on board, which means they should be a good fit for data centres. 21-Out-2013 © Prof. Dr. Douglas Renaux NVIDEA: 192 GPU 4x A15 ou 2x A57 Tegra K1 Lançado em 2014 © Prof. Dr. Douglas Renaux Tegra X1 - 2015 © Prof. Dr. Douglas Renaux NVidia - 2016 © Prof. Dr. Douglas Renaux Qualcomm's Growing 64-bit SoC Lineup Marketing Name Snapdragon 615 Snapdragon 610 Snapdragon 410 Internal Model Number MSM8939 MSM8936 MSM8916 Manufacturing Process 28nm LP 28nm LP 28nm LP CPU 8 x ARM Cortex A53 4 x ARM Cortex A53 4 x ARM Cortex A53 1.2GHz+ ISA 32/64-bit ARMv8 32/64-bit ARMv8 32/64-bit ARMv8 GPU Qualcomm Adreno 405 Qualcomm Adreno 405 Qualcomm Adreno 306 H.265 Decode Yes Yes No Memory Interface 1 x 64-bit LPDDR2/3 1 x 64-bit LPDDR2/3 1 x 64-bit LPDDR2/3 Integrated Modem 9x25 core, LTE 9x25 core, LTE 9x25 core, LTE Category 4, DC- Category 4, DC- Category 4, DC- HSPA+, DS-DA HSPA+, DS-DA HSPA+, DS-DA Integrated WiFi Qualcomm VIVE Qualcomm VIVE Qualcomm VIVE 802.11ac 802.11ac 802.11ac eMMC Interface 4.5 4.5 4.5 © Prof. Dr. Douglas Renaux © Prof. Dr. Douglas Renaux Fev 29, 2016 – Raspberry Pi 3 © Prof. Dr. Douglas Renaux Cortex-M7 (lançamento 24-Set-2014) © Prof. Dr. Douglas Renaux © Prof. Dr. Douglas Renaux © Prof. Dr. Douglas Renaux © Prof. Dr. Douglas Renaux © Prof. Dr. Douglas Renaux RISC x CISC © Prof. Dr. Douglas Renaux Histórico Computadores Computador = um dispositivo que computa (calcula, processa dados) © Prof. Dr. Douglas Renaux Gerações de Computadores Geração Descrição 0 Máquinas Mecânicas e Eletromecânicas solução de equações 1 40’s – Válvula ENIAC, Zuse 2 50’s – Transistores Universidade de Manchester IBM 350 3 60’s – Circuitos integrados SSI (portas lógicas) Apolo Guidance Computer (embarcado) IBM System/360 Digital VAX 4 70’s – Microprocessador 5 20?? – ótico, orgânico, computação quântica ??? IA © Prof. Dr. Douglas Renaux Computação Quântica - 5-Out-2015 © Prof. Dr. Douglas Renaux Primeira Geração Colossus - UK ENIAC - USA © Prof. Dr. Douglas Renaux Segunda Geração PDP-1 © Prof. Dr. Douglas Renaux Terceira Geração VAX 11/780 © Prof. Dr. Douglas Renaux De que forma os projetistas de computadores (arquitetos) utilizaram o aumento significativo de transistores disponibilizados pela evolução rápida da tecnologia de fabricação de circuitos integrados ? © Prof. Dr. Douglas Renaux CISC Complex Instruction Set Computer o conjunto de instruções inicialmente simples avanços tecnológicos (transistores, CIs) permitiram a manufatura de computadores com mais transistores a menor custo projetistas optaram por conjuntos de instruções cada vez mais complexos © Prof. Dr. Douglas Renaux CISC Como tornar as instruções mais complexas: aumentar o número de modos de endereçamento endereçamento indireto em memória [[R]] instruções com elevado grau semântico Exemplos do 68000 SBCD: Subtract Decimal with Extend SWAP: Swap register Words CMP2: Compare Register against Upper and Lower Bounds © Prof. Dr. Douglas Renaux © Prof. Dr. Douglas Renaux Date of Transistor Manufactu Processor introductio Process Area count rer n Intel 4004 2,300 1971 Intel 10 µm 12 mm² Intel 8008 3,500 1972 Intel 10 µm 14 mm² Motorola 68,000 1979 Motorola 3.5 μm 44 mm² 68000 Intel 80286 134,000 1982 Intel 1.5 µm 49 mm² Pentium 3,100,000 1993 Intel 0.8 µm 294 mm² ARM 7 578977[9] 1994 ARM 0.5 µm 68.51 mm² ARM 26,000,000[ 2007 ARM 65 nm Cortex-A9 12] AMD 463,000,00 K10 quad- 2007 AMD 65 nm 283 mm² 0[11] core 2M L3 Quad-Core + 1,400,000,000 2012 Intel 22 nm 160 mm² GPU Core i7 Xbox One 5,000,000,000 Microsoft/AMD Main SoC 2013 28 nm 363 mm² Perguntas Qual é, afinal, o objetivo primordial do arquiteto / projetista de computadores ? Dada uma tecnologia de fabricação e uma área de silício (custo), como fazer o melhor aproveitamento possível ? Quais são as conseqüências de um conjunto de instruções complexo ? © Prof. Dr. Douglas Renaux RISC x CISC RISC CISC Conjunto de instruções reduzido Conjunto de instruções extenso Instruções muito simples Instruções complexas Instruções de tamanho fixo Instruções de tamanho variável Decodificação simplificada Decodificação complexa (tabela) (microcódigo) Execução regular Cada instrução executa a sua maneira Instruções requerem o mesmo Grande variação no número de número de clocks para executar clocks por instrução Possibilita o uso de pipeline Extremamente difícil / impossível o uso de pipeline © Prof.
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