Design and Performance of a Pinned Photodiode CMOS Image Sensor Using Reverse Substrate Bias †

Article Design and Performance of a Pinned Photodiode CMOS Image Sensor Using Reverse Substrate Bias †

Konstantin D. Stefanov * ID , Andrew S. Clarke, James Ivory and Andrew D. Holland Centre for Electronic Imaging, The Open University, Walton Hall, Milton Keynes MK7 6AA, UK; [email protected] (A.S.C.); [email protected] (J.I.); [email protected] (A.D.H.) * Correspondence: [email protected]; Tel.: +44-1908-332116 † This paper is an expanded version of our published paper: Stefanov, K.D.; Clarke, A.S.; Ivory, J.; Holland, A.D. Fully Depleted, Monolithic Pinned Photodiode CMOS Image Sensor Using Reverse Substrate Bias. In Proceedings of the 2017 International Image Sensor Workshop, Hiroshima, Japan, 30 May–2 June 2017.

Received: 30 October 2017; Accepted: 28 December 2017; Published: 3 January 2018

Abstract: A new pinned photodiode (PPD) CMOS image sensor with reverse biased p-type substrate has been developed and characterized. The sensor uses traditional PPDs with one additional deep implantation step to suppress the parasitic reverse currents, and can be fully depleted. The first prototypes have been manufactured on an 18 µm thick, 1000 Ω·cm epitaxial silicon wafers using 180 nm PPD image sensor process. Both front-side illuminated (FSI) and back-side illuminated (BSI) devices were manufactured in collaboration with Teledyne e2v. The characterization results from a number of arrays of 10 µm and 5.4 µm PPD pixels, with different shape, the size and the depth of the new implant are in good agreement with device simulations. The new pixels could be reverse-biased without parasitic leakage currents well beyond full depletion, and demonstrate nearly identical optical response to the reference non-modified pixels. The observed excessive charge sharing in some pixel variants is shown to not be a limiting factor in operation. This development promises to realize monolithic PPD CIS with large depleted thickness and correspondingly high quantum efficiency at near-infrared and soft X-ray wavelengths.

Keywords: CMOS image sensors (CIS); pinned photodiode; full depletion; reverse bias; thermionic emission

1. Introduction Pinned photodiode (PPD) monolithic CMOS image sensors (CIS) are the dominant devices in today’s high performance and consumer imaging due to several key characteristics. The use of charge transfer between the PPD and the sense node separates the functions of charge collection and charge-to-voltage conversion [1] and allows the sense node to be optimized separately and to be much smaller than the PPD. Optimal correlated double sampling can be implemented for suppression of kTC noise, and together with the very low sense node capacitance makes it possible to routinely achieve sub-electron read noise [2]. In addition, the dark current in PPD pixels is very low because of the nearly complete suppression of the surface electron-hole generation by the shallow pinning layer [3], which also helps to significantly reduce the image lag [4]. For applications requiring high quantum efficiency (QE) in the near-infrared (NIR) and soft X-ray (<10 keV) bands, the active sensor volume should be tens or even hundreds of micrometers thick due to the large absorption length of silicon [5]. To prevent deterioration of the modulation transfer function (MTF) this volume should be fully depleted and even over-depleted [6] in order to increase the carrier drift velocity and to minimize the charge diffusion during the drift time. High QE devices are normally back-side illuminated and made on very high resistivity (≈10 kΩ·cm) bulk silicon, however their normal operating voltages are not sufficient to achieve full depletion beyond approximately 50 µm.

Sensors 2018, 18, 118; doi:10.3390/s18010118 www.mdpi.com/journal/sensors Sensors 2018, 18, x FOR PEER REVIEW 2 of 14 Sensors 2018, 18, 118 2 of 14 however their normal operating voltages are not sufficient to achieve full depletion beyond Forapproximately example, the 50 channel µm. For potential example, in the Charge channel Coupled potential Devices in Charge (CCDs) Coupled is in the rangeDevices 10–15 (CCDs V, and) is inin CMOSthe range devices 10–15 the V, diode and bias in CMOS rarely exceedsdevices 5 the V. To diode overcome bias ra thisrely limitation, exceeds 5 a V. separate To overcome reverse bias this islimitation, applied across a separate the substrate, reverse bias and is its applied magnitude across depends the substrate, on the and resistivity its magnitude and the thicknessdepends on of thethe activeresistivity semiconductor. and the thickness of the active semiconductor. ReverseReverse biasingbiasing isis easilyeasily achievableachievable withwith hybridhybrid CIS oror CCDs,CCDs, butbut isis aa challengechallenge forfor monolithicmonolithic PPDPPD devices devices due due to to the the in-pixel in-pixel well well containing containing the readout the readout transistors. transistors. One PPD One example PPD example [7] achieves [7] fullachieves depletion full depl at theetion expense at the expense of adding of anotheradding anotherpn junction pn junction and significantly and significantly modifying modifying the pixel. the PPDpixel. layouts PPD layouts and doping and doping profiles profiles are usually are usually highly optimizedhighly optimized for good for performance, good performance, and any changesand any shouldchanges be should carefully be consideredcarefully considered and simulated. and simulated. Ideally, the Ideally, structure the of structur the PPDe shouldof the PPD not be should modified not whenbe modified adding when new elementsadding new for reverseelements biasing, for reverse and thisbiasing, has beenand this our has goal been as well. our goal as well. AsAs shownshown inin Figure Figure1 for1 for n-type n-type PPD, PPD, the the front front side side p-wells p-wells are electricallyare electrically connected connected to the to p-type the p- type active layer. Since the p-wells are at device ground, applying negative substrate bias VBSB in active layer. Since the p-wells are at device ground, applying negative substrate bias VBSB in order to increaseorder to theincrease depletion the depletion depth under depth the under PPD wouldthe PPD result would in large result currents in large flowing currents from flowing the front from side the p-wellsfront side to thep-wells backside to the p backside++ contact, p++ as contact, the p+/p as− the/p ++p+/pstructure−/p++ structure would would conduct conduct resistively. resistively.

FigureFigure 1.1. Cross section of a typical pinned photodiode (PPD)(PPD) pixel showing the conductive path from ++ ++ thethe front-sidefront-side p-wellsp-wells toto thethe pp++ substrate (for(for front-sidefront-side illuminatedilluminated devices),devices), oror toto thethe shallowshallow pp++ backback sideside implantimplant (for(for back-sideback-side illuminatedilluminated devices).devices). TheThe transistors T1T1 and T2 are physically located inin thethe p-well.p-well.

IfIf thethe leakage current can be eliminated, eliminated, the the full full active active thickness thickness of of the the device device 푡t푎a cancan bebe depleteddepleted withwith thethe beneﬁtsbenefits ofof shortshort chargecharge collectioncollection timetime andand goodgood MTF.MTF. ThisThis paperpaper describesdescribes aa methodmethod forfor achievingachieving this this in in a PPD a PPD CIS, CIS, details details of the of design the design and the and results the from results the from characterization the characterization of prototype of devices,prototype signiﬁcantly devices, significantly expanding expanding from the presentation from the presentation given in [8 ].given in [7].

2.2. Operating Principles TheThe mainmain ideaidea isis toto makemake allall thethe individualindividual depletiondepletion regionsregions fromfrom adjacentadjacent PPDsPPDs mergemerge underunder thethe p-wells,p-wells, thusthus cuttingcutting offoff thethe parasiticparasitic front-to-backfront-to-back substratesubstrate current.current. ThisThis conditioncondition isis notnot metmet naturallynaturally inin PPDPPD CIS CIS due due to to the the size size and and the the depth depth of theof the p-well p-well and and the lowthe PPDlow PPD pinning pinning voltage voltage Vpin, whichVpin, which is usually is usually in the in range the range between between one and one two and volts. two volts. InIn thethe new design ( (FigureFigure 2) an additional deep deep n n-type-type implant implant is is introduced introduced under under the the pixel pixel p- p-wells,wells, while while keeping keeping the the PPD PPD structure structure unchanged. unchanged. This This implant implant has has been been dubbed “deep depletion extension”extension” (DDE), does does not not connect connect to to the the PPD PPD and and has has lower lower dopant dopant concentration. concentration. In operation In operation,, the theDDE DDE becomes becomes depleted depleted and and helps helps merge merge the the diode diode depletion depletion regions regions laterally laterally under under the the p-wells,p-wells, creatingcreating aa pinch-off.pinch-off. The DDE regions acquire their potentials from the adjacent PPDs, and depending onon theirtheir potentialpotential thethe DDEDDE potentialpotential willwill varyvary acrossacross thethe device.device. The size, shape, depth and doping concentration of the DDE were derived and optimized using commercial 2D and 3D TCAD tools. The goal was to create a potential distribution in which the DDE

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SensorsThe 2018 size,, 18, shape,x FOR PEER depth REVIEW and doping concentration of the DDE were derived and optimized using3 of 14 commercial 2D and 3D TCAD tools. The goal was to create a potential distribution in which the is less positive than the PPDs in order not to interfere with normal charge collection, while DDE is less positive than the PPDs in order not to interfere with normal charge collection, while simultaneously forming a substantial potential barrier under the pixel p-wells to prevent parasitic simultaneously forming a substantial potential barrier under the pixel p-wells to prevent parasitic flow of holes to the substrate. This is easier to achieve if the semiconductor resistivity and Vpin are ﬂow of holes to the substrate. This is easier to achieve if the semiconductor resistivity and V are high because the size of the depleted region is approximately proportional to the square root ofpin their high because the size of the depleted region is approximately proportional to the square root of their product, using the considerations for an abrupt pn junction [9]. At the same time, the pixel p-well product, using the considerations for an abrupt pn junction [9]. At the same time, the pixel p-well should be as shallow and narrow as possible in order to reduce the distance which has to be bridged. should be as shallow and narrow as possible in order to reduce the distance which has to be bridged.

Figure 2. Cross section of the new design in a front-side illuminated (FSI) variant, showing the deep Figure 2. Cross section of the new design in a front-side illuminated (FSI) variant, showing the deep depletion extension (DDE) implant, the guard ring surrounding the pixel array, p-wells and n-wells for depletion extension (DDE) implant, the guard ring surrounding the pixel array, p-wells and n-wells off-pixel transistors, and the edge p-well and its guard space for applying the reverse substrate bias for off-pixel transistors, and the edge p-well and its guard space for applying the reverse substrate from the front. bias from the front.

FigureFigure2 2shows shows some some of of the the other other important important features features in in the the design. design. A A deep deep n-well n-well is is introduced introduced toto shield shield the the transistor transistor p-wells, p-wells, and and this this allows allows both both n-type n-type and and p-type p-type Metal-Oxide-Semiconductor Metal-Oxide-Semiconductor (MOS)(MOS) transistors transistors to to be be implemented implemented on on chip. chip. TheThe reversereverse substratesubstrate biasbias isis provided provided fromfrom the the front front usingusing the the wide wide undepletedundepleted siliconsilicon alongalong thethe chipchip periphery,periphery, and and a a guard guard space space is is provided provided to to avoid avoid junctionjunction breakdown. breakdown. In In backside backside illuminated illuminated (BSI) (BSI) variant variant the substrate the substrate is ground is ground away and away a shallow and a ++ pshallowdopant p++ is dopant implanted is implanted into the backinto the surface. back Thesurface. same The metal same pads metal are usedpads forare connectionsused for connections for both FSIfor andboth BSI FSI variants, and BSI but variants, for BSI but chips for the BSI silicon chips aroundthe silicon the padsaround is etchedthe pads away is etched for wire away bond for access wire frombond the access back from side. the back side. FigureFigure3 3displays displays the the potential potential distribution distribution in in a a simplified simplified 2D 2D PPD PPD model model with with DDE DDE implants, implants, containingcontaining 33 pixels.pixels. The The line line A A–A’–A’ shows shows the the magnitude magnitude of of the the potential potential barrier barrier under under the the pixel pixel p- p-wellwell and and the the potential potential down down to the to theback back side side of the of device. the device. The line The B line–B’ illustrates B–B’ illustrates the pinning the pinning voltage voltageVpin at the Vpin PPDat the center PPD and center also and a region also a regionof low ofelectric low electric field (near field zero (near potential zero potential gradient) gradient) in this inparticular this particular direction. direction. Simulations Simulations show that show if the that DDE if the doping DDE is doping too high is tooor its high size or is its too size large, is too the large,potential the potentialdistribution distribution under the underp-well the cou p-wellld form could a shallow form potential a shallow pocket. potential When pocket. the DDE When region the DDEbecomes region more becomes positive more than positive the surrounding than the surrounding semiconductor semiconductor some electrons some get electrons diverted get to divertedthe DDE toand the eventually DDE and drained eventually away drained without away reaching without the reaching PPDs. On the the PPDs. other On hand, the too other low hand, DDE too doping low DDEwould doping not create would thenot necessary create thepotential necessary barrier potential for prevention barrier of for substrate prevention currents. of substrate Some parameter currents. Someoptimization parameter is necessary optimization to tune is necessary the behavior to tune of thethe behaviorDDE, but of this the is DDE, greatly but helped this is greatlyby the fact helped that bythe the potential fact that barrier the potential can be adjusted barrier can electrically be adjusted by electricallythe applied byreverse the applied bias. reverse bias. BothBoth the the PPD PPD potential potential and and the the barrier barrier under under the pixel the pixel p-well p are-well influenced are influenced by the appliedby the reverseapplied biasreverse because bias theybecause are they isolated are space-chargeisolated space regions-charge andregions not and tied not to a tied fixed to potential. a fixed potential. Figure4 Figureshows 4 thatshows the that barrier the under barrier the under p-well theV PWp-wellis influenced VPW is influenced more strongly more strongly by the VBSB by thethan V theBSB than pinning the voltagepinning Vvoltagepin. The V reversepin. The biasreverse pulls bias down pulls both down potentials both potentials almost linearly, almost andlinearly, from and the datafrom in the Figure data4 in we Figure can = = calculate4 we cand calculateV pin/dV BSBdVpin⁄d0.02VBSBand = 0.02dVpw and/dV dBSBVpw⁄d0.056VBSB =. The 0.056 stronger. The stronger influence influence on VPW onis due VPW tois thedue to the much greater depth of the DDE implant and its weak coupling to the PPDs, and is an important factor for device operation. The consequence of the decrease of Vpin shown in Figure 4a is a reduction

Sensors 2018, 18, 118 4 of 14 muchSensorsSensors greater2018 2018, 18,, 18x depth FOR, x FOR PEERof PEERthe REVIEW REVIEW DDE implant and its weak coupling to the PPDs, and is an important4 of4 14of factor 14 for device operation. The consequence of the decrease of Vpin shown in Figure4a is a reduction of the fullof ofthe well the full full capacity well well capacity capacity (FWC), (FWC), however(FWC), however however this maythis this may not may benot not detrimental be bedetrimental detrimental if the if the outputif the output output signal signal signal is limitedis limitedis limited by the sensebyby the the node sense sense capacitance, node node capacitance, capacitance, as is typical as asis typicalis fortypical sensors for for sensors sensors with with high with high conversion high conversion conversion gain. gain. gain.

FigureFigure 3 3.. Potential3Potential. Potential distribution distribution distribution in in ina a2Da 2D2D simulation simulationsimulation model model reverse reverse biased biased biased at at− at5 −V,−5 5V,and V, and andthe the potential the potential potential proﬁlesprofilesprofiles along along two two lines: lines: lines: A A–A’– AA’– A’is is ais avertical a vertical vertical line line line crossing crossing crossing a p a a- p-wellwellp-well perpendicular perpendicularperpendicular to device’s to device’s surface; surface; surface; B– B B–B’– startsB’ startsB’ starts from from from the the potential the potential potential peak peak peak in in the thein the PPD PPD PPD atat 0.45 0.45at 0.45 µµmm µm below below the the the surface surface surface and and and cuts cuts cuts through through through the thethe middle middlemiddle of theof of the DDE the DDE implant. DDE implant. implant. The The two The two lines two lines intersect lines intersect intersect at 2 atµm at2 along µm 2 µm along A–A’ along A and – AA’– 5.25A’ and andµ 5.25m 5.25 along µm µm B–B’.along along The B– B’. B simulation– B’. The The issimulation forsimulation 1000 Ωis · forcm,is for 1000 18 1000µ Ω·cmm Ω·cm thick, 18, epitaxial18µm µm thick thick siliconepitaxial epitaxial and silicon 10siliconµ mand pixels.and 10 10µm µm pixels. pixels.

FigureFigure 4 4.. 4SimulatedSimulated. Simulated potentials potentials potentials through through through the the center center of of aof PPD a a PPD PPD (a ); ( (aa and);); and and though though though a p a- awell p- p-wellwell with with with DDE DDE DDE underneathunderneath it (itb )( b asas) aasa functionfunction a function ofof theofthe the appliedapplied applied reversereverse reverse biasbias bias VVBSBBSB V.BSB .The The. The simulation simulation simulation is is foris for for 1000 1000 1000 Ω·cm,Ω Ω·cm,·cm, 18 18 18µ m thickµmµm thick epitaxial thick epitaxial epitaxial silicon silicon silicon and and 10 and 10µm 10µm pixels. µm pixels. pixels.

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For 1000 Ω·cm, 18 µm thick epitaxial silicon and Vpin = 1.8 V full depletion is achieved For 1000 Ω·cm, 18 µm thick epitaxial silicon and Vpin = 1.8 V full depletion is achieved approximately at VBSB = −4 V, and further increase of the reverse voltage leads to over-depletion which approximately at VBSB = −4 V, and further increase of the reverse voltage leads to over-depletion which cancan be be beneficialbeneficial for for reducingreducing thethe electronelectron driftdrift timetime andand minimizingminimizing thethe PointPoint SpreadSpread FunctionFunction (PSF).(PSF). BecauseBecause most most of of the the reversereverse bias bias drops drops across across the the active active epitaxial epitaxial silicon silicon below below the the PPD, PPD, the the principleprinciple ofof operationoperation isis applicableapplicable toto muchmuch thickerthicker sensorsensor substrates,substrates, whichwhich requirerequire higherhigher voltagesvoltages forfor fullfull depletion.depletion. RegardlessRegardless of of the the thickness, thickness, the the changes changes to to the the PPD PPD and and p-well p-well potentials potentials will will be similarbe similar to theto the ones ones shown shown in Figure in Fig4ure. 4. AtAt sufficientlysufficiently highhigh reversereverse voltagevoltage thethe potentialpotential barrierbarrier belowbelow thethe p-wellp-well willwill bebe eventuallyeventually reducedreduced toto a a level level where where hole hole current current will will start start to to flow flow via via thermionic thermionic emission emission [[99].]. However,However, if if this this occursoccurs well well above above full full depletion depletion the the condition condition will will not not have have to to be be reached,reached, and and the the devicedevice willwill functionfunction asas desired. desired. TheThe PPDPPD potentialpotential isis reducedreduced when charge is collected, collected, and and since since the the barrier barrier under under the the p p-well-well is isderived derived from from the the PPDs PPDs around around it, it,the the barrier barrier will will be bereduced reduced too. too. To make To make sure sure that that this thisdoes does not lead not leadto undesirable to undesirable signal signal-dependent-dependent substrate substrate currents, currents, the the DDE DDE has has to to be be designed designed so that sufficientsufficient barrierbarrier height height is is maintained maintained beyond beyond full full well well capacity. capacity.

3.3. PrototypePrototype DeviceDevice AA prototype prototype device device using using the the DDEDDE conceptconcept waswas designeddesigned byby usus andand manufacturedmanufactured byby TowerJazzTowerJazz SemiconductorSemiconductor on on a a 180 180 nm nm image image sensor sensor CMOS CMOS process. process. The The device, device, dubbed dubbed BSB1, BSB1, uses uses 1000 1000Ω Ω·cm·cm 1818µ µmm thick thick epitaxial epitaxial silicon silicon and and contains contains eight eight arrays arrays with with 32 32 (V) (V)× ×20 20(H) (H) pixelspixelseach. each. HalfHalf thethe arraysarrays areare mademade ofof 1010µ µmm square square pixels pixels and and the the other other half half of of 5.4 5.4µ µmm pixels, pixels, with with each each array array implementing implementing DDE differentdifferent lengthlength ofof the the DDE DDE implant implantL LDDE.. InIn sevenseven pixelpixel variantsvariants thethe shapeshape ofof thethe DDEDDE followsfollows thethe shapeshape ofof thethe pixelpixel p-wellp-well asas shownshown inin Figure Figure5 a,b,5a,b and, and overlaps overlaps it it in in increasing increasing steps. steps. The The shape shape withoutwithout a a notch notch around around the the sense sense node node in in Figure Figure5 b5b was was used used when when the the design design rules rules for for high high energy energy implantsimplants did did not not allow allow the the manufacture manufacture of of this this narrow narrow feature. feature. In In one one of of the the 5.4 5.4µ µmmpixel pixelvariants variants the the DDEDDE onlyonly partiallypartially coverscovers thethe p-wellp-well asas inin Figure Figure5 c.5c. This This was was deemed deemed promising promising after after signiﬁcant significant narrowingnarrowing ofof the the p-well p-well between between the the side side edgesedges ofof the the PPD, PPD, which which inin simulationsimulation waswas ableable toto achieveachieve pinch-offpinch-off naturally. naturally. Table Table1 lists1 lists the the design design types types used used in in the the eight eight pixel pixel arrays. arrays.

Figure 5. Simpliﬁed pixel layouts showing fully overlapping DDE over the p-well with (a) and without Figure 5. Simplified pixel layouts showing fully overlapping DDE over the p-well with (a) and (b) notch around the sense node; and partially overlapping DDE (c). The sense node and the three without (b) notch around the sense node; and partially overlapping DDE (c). The sense node and the transistors are not shown for simplicity. three transistors are not shown for simplicity. Table 1. Summary of the pixel design variants with layouts shown in Figure5. Table 1. Summary of the pixel design variants with layouts shown in Figure 5. µ µ VariantVariant 1010m µm 5.4 5.4m µm 1 a c 12 a a b c 23 a a b b 34 a a b b 4 a b

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Three process variants with different depth of the DDE were manufactured: “shallow”, “medium”Three processand “deep”, variants in combination with different with depth two of different the DDE pinning were manufactured: voltages: 1.5 to “shallow”, 1.6 V (low “medium” Vpin) and 1.7and to “deep”, 1.8 V (high in combination Vpin). One wafer with type two with different high pinningVpin did not voltages: receive 1.5 the to DDE 1.6 V implant (low V pinand) andwas 1.7used to 1.8as a V reference, (high Vpin as). the One pixels wafer on type it did with not high receiveVpin anydid modifications. not receive the DDE implant and was used as a reference,Each asrow the is pixelsselected on by it dida simple not receive combinational any modiﬁcations. decoder controlling the row select gate and two analogueEach switches row is selected to the transfer by a simple and the combinational reset gates. decoderThe outputs controlling from the the eight row pixel select arrays gate andare multiplexedtwo analogue to switches common to source the transfer followers and and the connected reset gates. directly The outputs to chip from pads. the Only eight the pixel middle arrays 16 columnsare multiplexed (out of 20) to commonare read out. source followers and connected directly to chip pads. Only the middle 16 columnsBSB1 was (out designed of 20) are to read be out.compatible with backside thinning and illumination by using large bondBSB1 pads was and designedthe biasing to bestructure compatible shown with in backsideFigure 2. thinningTwo wafers and were illumination processed by usingby Teledyne large bond e2v padsand thinned and the to biasing 12 µm structure epitaxial shown thickness, in Figure with2 .the Two silicon wafers around were processedthe pads etched by Teledyne away e2vfor wire and bondingthinned to from 12 µ m the epitaxial back side, thickness, as is typical with the for silicon such around technology. the pads The etched backside away of for the wire sensor bonding was implantedfrom the back with side, a shallow as is typical p++ dopant for such which technology. passivates The the backside surface ofand the provides sensor wasa low implanted resistance with path a forshallow the reverse p++ dopant bias to which propagate passivates across the all surface of the anddevice provides area. Figure a low resistance6 shows photographs path for the reverseof both BSB1bias to variants. propagate across all of the device area. Figure6 shows photographs of both BSB1 variants.

Figure 6. Photographs of the BSB1 chip: (a) front-side illuminated (FSI) variant; (b) back-side Figure 6. Photographs of the BSB1 chip: (a) front-side illuminated (FSI) variant; (b) back-side illuminated (BSI) variant. Die size is 5 mm × 5 mm. illuminated (BSI) variant. Die size is 5 mm × 5 mm.

4. Experimental Results 4.1. Leakage Current under Reverse Bias in Darkness 4.1. Leakage Current under Reverse Bias in Darkness The most important part of the sensor characterization was to establish that the DDE cuts off the The most important part of the sensor characterization was to establish that the DDE cuts off the leakage current under reverse substrate bias as intended. Initial results reported in [10] demonstrated leakage current under reverse substrate bias as intended. Initial results reported in [10] demonstrated that in all chip variants the reverse current was suppressed. The current was measured for the whole that in all chip variants the reverse current was suppressed. The current was measured for the whole device and included the contributions from the eight pixel variants in parallel, together with the device and included the contributions from the eight pixel variants in parallel, together with the offoff-pixel digital and analog circuitry. pixel digital and analog circuitry. To characterize each DDE variant and measure its reverse current, the individual pixel arrays were To characterize each DDE variant and measure its reverse current, the individual pixel arrays designed with their own substrate connections. The pixel array substrates connect through diodes, were designed with their own substrate connections. The pixel array substrates connect through part of the electrostatic discharge (ESD) protection, to the digital substrate as shown in Figure7a. diodes, part of the electrostatic discharge (ESD) protection, to the digital substrate as shown in Figure The effect is that the worst-performing pixel type can dominate the leakage current when its protection 7a. The effect is that the worst-performing pixel type can dominate the leakage current when its diode becomes forward biased, and this can limit the voltage applied to the whole chip. protection diode becomes forward biased, and this can limit the voltage applied to the whole chip. Figure8 shows the experimentally measured total substrate current I BSB and the individual substrate currents from the eight pixel arrays per chip. The I–V curves were taken while the sensor was continuously read out at 10 fps in darkness, and the current limits were set to 100 µA. This and ◦ all other measurements in this work were carried out at 23 ± 1 C. At low VBSB values the two currents are dominated by the reverse pn junction currents I1 and I2 as illustrated in Figure7b. At the threshold substrate voltage VBSB = Vthr the potential barrier under the p-well is overcome and the substrate current I3 starts ﬂowing in the opposite direction to I2. This leads to the change of sign in the current measured by A2, manifesting as “dips” in the I–V curves when the absolute current value becomes zero.

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Figure 7. Simplified electrical diagram for the reverse current measurements (a) and the current

components (b). The total substrate current IBSB is measured by the current meter A1 and the substrate

current of the individual arrays by A2.

Figure 8 shows the experimentally measured total substrate current IBSB and the individual substrate currents from the eight pixel arrays per chip. The I–V curves were taken while the sensor was continuously read out at 10 fps in darkness, and the current limits were set to 100 µA. This and all other measurements in this work were carried out at 23 ± 1 °C. At low VBSB values the two currents are dominated by the reverse pn junction currents I1 and I2 as illustrated in Figure 7b. At the threshold substrate voltage VBSB = Vthr the potential barrier under the p-well is overcome and the substrate currentFigure I3 starts 7. Simpliﬁed flowing in electrical the opposite diagram direction for the reverseto I2. This current leads measurements to the change (a of) and sign the in currentthe current Figure 7. Simplified electrical diagram for the reverse current measurements (a) and the current measuredcomponents by A2 (,b manifesting). The total substrate as “dips” current in theIBSB I–isV measured curves when by the the current absolute meter Acurre1 andnt the value substrate becomes components (b). The total substrate current IBSB is measured by the current meter A1 and the substrate zero.current of the individual arrays by A2. current of the individual arrays by A2.

Figure 8.8. Substrate current for the whole chip and individual array substrate currents for 10 µµmm pixel (a) and 5.4 µm pixel variants (b) from a high Vpin, medium DDE wafer. The absolute current values (a) and 5.4 µm pixel variants (b) from a high Vpin, medium DDE wafer. The absolute current values are plottedare plotted due todue the to change the change of sign of of sign the pixelof the array pixel currents. array currents. The plot The with plot the with chip removedthe chip removed indicates theindicates sensitivity the sensitivity of the current of the measurement current measurement using the sourceusing the measure source unit measure model unit U2722A. model U2722A.

The dominant current is from the 5.4 µm array 1, which is the only one using the design in Figure The dominant current is from the 5.4 µm array 1, which is the only one using the design in 5c. The currents from the other seven arrays, which all use the fully overlapping design in Figure 5a Figure5c. The currents from the other seven arrays, which all use the fully overlapping design in or Figure 5b, are orders or magnitude lower. The length LDDE (shown in Figure 2) increases in equal Figure5a or Figure5b, are orders or magnitude lower. The length L (shown in Figure2) increases steps of 0.2 µm following the number of the pixel array. DDE in equal steps of 0.2 µm following the number of the pixel array. Beyond the threshold voltage Vthr the leakage current increases exponentially with the reverse Beyond the threshold voltage V the leakage current increases exponentially with the reverse voltage and can be described by thermionicthr emission of holes over a potential barrier, with an voltageFigure and 8 can. Substrate be described current by for thermionic the whole chip emission and individual of holes over array a substrate potential currents barrier, for with 10 anµm additional pixel additional current 퐼2 from the reverse-biased pn junction. The absolute value of the array substrate current(a) Iandfrom 5.4 µm the pixel reverse-biased variants (bpn) fromjunction. a high TheVpin, absolutemedium DDE value wafer. of the The array absolute substrate current current valuesIr can current 퐼2 can be expressed from [9] as: be expressedare plotted푟 from due [ 9to] as:the change of sign of the pixel array currents. The plot with the chip removed indicates the sensitivity of the current measurement using the source measure unit model U2722A. ∗ 2 mh VPW + βVBSB |Ir| = |I3 − I2| = AT S exp − − I2 , (1) The dominant current is from the 5.4 µm arraym0 1, which iskT the/q only one using the design in Figure 5c. The currents from the other seven arrays, which all use the fully overlapping design in Figure 5a where A is the Richardson’s constant for free electrons, S is the total area of the pixel p-well, m0 is or Figure 5b, are orders or magnitude lower. The length LDDE (shown in Figure 2) increases in equal the free electron mass, m∗ is the effective hole mass in p-type silicon, V is the potential barrier steps of 0.2 µm following hthe number of the pixel array. PW height under the p-well at zero reverse bias, and β < 0 is a proportionality coefﬁcient describing the Beyond the threshold voltage Vthr the leakage current increases exponentially with the reverse approximately linear decrease of the barrier height with increasing V . In (1) the absolute value of voltage and can be described by thermionic emission of holes overBSB a potential barrier, with an VBSB is used even if in practice it is negative with respect to ground. Good estimates for VPW and β are additional current 퐼2 from the reverse-biased pn junction. The absolute value of the array substrate obtained from the simulations in Figure4b by ﬁtting a straight line to the peak potential under the current 퐼푟 can be expressed from [9] as:

Sensors 2018, 18, x FOR PEER REVIEW 8 of 14

∗ 2 푚ℎ 푉푃푊+훽푉퐵푆퐵 |퐼푟| = |퐼3 − 퐼2| = |퐴푇 푆 exp (− ) − 퐼2|, (1) 푚0 푘푇⁄푞

where 퐴 is the Richardson’s constant for free electrons, 푆 is the total area of the pixel p-well, 푚0 is ∗ the free electron mass, 푚ℎ is the effective hole mass in p-type silicon, 푉푃푊 is the potential barrier height under the p-well at zero reverse bias, and 훽 < 0 is a proportionality coefficient describing the Sensors 2018, 18, 118 8 of 14 approximately linear decrease of the barrier height with increasing VBSB. In (1) the absolute value of

VBSB is used even if in practice it is negative with respect to ground. Good estimates for 푉푃푊 and 훽 p-wellare obtained as a function from oftheV BSBsimulations. The absolute in Figure value 4b of by the fitting threshold a straight voltage line can to bethe expressed peak potential from (1)under at the p-well as a function of VBSB. The absolute value of the threshold voltage can be expressed from (1) the point when the thermionic current equals I2 and gives at the point when the thermionic current equals 퐼2 and gives 2 ∗ 1 kT AT S2m ∗ |V | = − 1 푘푇 퐴푇 푆 푚hℎ − V thr |푉푡ℎ푟| = − ln{ ln ( ) − 푉푃푊PW}. . (2)(2) β q훽 푞 I2 퐼2 m푚00

FigureFigure9 shows9 shows the the measured measured threshold threshold voltages voltages in in all of the the 10 10 µmµ m pixel pixel variants. variants. The experimental data indicates the trend for the Vthr to increase with the length and the depth of the DDE The experimental data indicates the trend for the Vthr to increase with the length and the depth of the DDEimplant, implant, and and qualitatively qualitatively agrees agrees with with the the TCAD TCAD simulations. However, a a reliable reliable quantitative quantitative comparisoncomparison is is difﬁcult difficult to to obtain obtain due due to to the the several several simpliﬁcations simplifications that that had had to to be be made made in in order order to to modelmodel a 3a ×3 ×3 3 pixel pixel array array in in 3D. 3D.

FigureFigure 9. 9Experimentally. Experimentally measured measured threshold threshold voltages voltages in in the the 10 10µm µm pixel pixel variants variants with with high highVpin Vpin (closed(closed symbols, symbols, solid solid lines) lines) and and lowlow VVpinpin (open(open symbols, symbols, dashed dashed lines) lines) for for the the three three DDE DDE depths. depths. The Theerror error bars bars indicate indicate the the spread spread in inVthrV thrcalculatedcalculated from from the the available available samples. samples.

InIn all all pixel pixel variants variants except except those those using using the the shallow shallow DDE DDE implant implant the the threshold threshold voltage voltage exceeds exceeds 4 V even for the shortest LDDE. This result indicates that devices with medium and deep DDE can be 4 V even for the shortest LDDE. This result indicates that devices with medium and deep DDE can be over-depleted for both low and high Vpin. over-depleted for both low and high Vpin.

4.2.4.2. Electro-Optical Electro-Optical Performance Performance

4.2.1.4.2.1 Photo. Photo Response Response Electro-opticalElectro-optical characterization characterization was was carried carried out out by by taking taking multiple multiple images images at at increasing increasing illuminationillumination levels, levels, from from which which the the photon photon transfer transfer curves curves (PTC) (PTC) [11 [11] at] at different different conditions conditions are are obtained.obtained.The The PTC PTC is is a a powerful powerful characterization characterization tool tool which which can can reveal reveal hidden hidden aspects aspects of of pixel pixel operationoperation through through its its sensitivity sensitivity to to deviations deviations from from the the ideal ideal Poisson Poisson noise noise distribution. distribution. FigureFigure 10 10 shows shows the the PTCs PTCs obtained obtained from from the the same same 10 10µ mµm pixel pixel design design in in FSI FSI and and BSI BSI variants, variants, togethertogether with with the the reference reference pixel pixel which which was made was made only in only FSI variant. in FSI variant. The ﬁve The sets of five data sets are of virtually data are indistinguishable,virtually indistinguishable, and show identical and show charge-to-voltage identical charge conversion-to-voltage gain conversion of 78 µV/e − gain(obtained of 78 from µV/e− the(obtained slopes at from low signalthe slopes values) at low and FWC.signal Applyingvalues) and reverse FWC. substrate Applying bias reverse beyond substrate full depletion bias beyond does notfull result depletion in any does detrimental not result effects in anyon the detrimental characteristics effects of the on sensor.the characteristics In addition, of measurements the sensor. In ofaddition, the sensor’s measurements linearity and of imagethe sensor’s lag have linearity shown and that image there lag is negligiblehave shown difference that there between is negligible the reference and the new pixel designs, and that this does not change under reverse bias. The readout noise was below 5 e− RMS. Sensors 2018, 18, x FOR PEER REVIEW 9 of 14

difference between the reference and the new pixel designs, and that this does not change under Sensorsreverse2018 bias., 18, The 118 readout noise was below 5 e− RMS. 9 of 14

Figure 10.10. Photon transfer curves (PTCs)(PTCs) (“mean-variance”(“mean-variance” type with frame differencing) of a 10 µµmm

pixelpixel variantvariant #1#1 inin FSIFSI andand BSIBSI implementationimplementation withwith highhigh VVpinpin andand medium medium DDE. One ADU is 305 µV.µV.

InterestinglyInterestingly enough,enough, eveneven largelarge substratesubstrate leakageleakage currentscurrents reachingreaching hundredshundreds ofof microampsmicroamps dodo not visibly visibly change change the the photo photo response response of the of sensor. the sensor. While While the PPD the is PPDcollecting is collecting electrons, electrons, the substrate the currentsubstrate consists current of consists holes, and of holes, the two and carriers the two do carriers not interact. do not Of interact. course, inOf any course, practical in any application practical theapplication substrate the current substrate must current be kept must to negligible be kept levelsto negligible or the reverse levels voltageor the reverse applied voltage to the sensorapplied will to bethe severely sensor will limited. be severely limited. The resultsresults fromfrom thethe 5.45.4 µµmm pixelpixel variantsvariants exhibitexhibit differentdifferent characteristicscharacteristics andand areare discusseddiscussed furtherfurther on.on.

4.2.2. Reverse Currents under StrongStrong IlluminationIllumination When the PPD collectscollects charge, thethe peak diode voltage decreases duedue to the compensation of the positivelypositively charged donor atoms by thethe storedstored electrons.electrons. The potential barrier created by the DDE is closely linkedlinked toto thethe diodediode voltage,voltage, andand itit willwill decreasedecrease too.too. UnderUnder strongstrong illuminationillumination thisthis couldcould cause the barrier to collapse and lead to a sharp increase of the reverse current. To investigate this, thethe reverse reverse current current of of the the whole whole chip chip and and the the individual individual pixel pixel arrays arrays were were measured measured under under high levels high levelsof illumination. of illumination. The light The stimu lightlus stimulus was generated was generated by a LED by pulse a LED immediately pulse immediately following following a readout, a readout,thus ensuring thus ensuringthat the collected that the charge collected is stored charge in is the stored PPDs in for the the PPDs entire for duration the entire of duration the integration of the integrationtime. Because time. the Because integration the integration time was time much was longer much than longer the than readout the readout time (100 time ms (100 and ms 2 and ms, 2respectively), ms, respectively), this is this equivalent is equivalent to constant to constant illumination illumination with the with desired the desired intensity. intensity. Figure 1111 shows shows the the measured measured currents currents in a in 10 µ a m 10 pixel µm variant pixel variant and reveals and a reveals shift in a the shift threshold in the voltagethreshold with voltage increasing with illumination increasing illumination levels. This levels.is a clear This indication is a clear that indication the potential that barrier the potential under thebarrier p-well under decreases the p-well when decreases charge iswhen stored charge in the is PPD,stored as in expected. the PPD, However,as expected. even However, at signal even levels at reachingsignal levels 10 times reaching FWC, 10V thrtimesremains FWC, well Vthr above remains the well voltage above needed the voltage to maintain needed full depletion.to maintain full depletion.The chip area outside the pixel arrays is covered with deep n-well as shown in Figure2 and is effectively a large reverse-biased pn junction. At low substrate voltages (below Vthr of the worst-performing pixel variant) the substrate current of the whole chip should behave as in a typical photodiode, and increase linearly with the light ﬂux. This is indeed observed in curves (b) and (c) in Figure 11, and can be used to verify the illumination levels beyond PPD saturation.

Sensors 2018, 18, x FOR PEER REVIEW 10 of 14

SensorsSensors2018 2018,,18 18,, 118 x FOR PEER REVIEW 1010 ofof 1414

Figure 11. Whole chip (open symbols) and array substrate (closed symbols) currents in a 10 µm pixel

design variant #3 with high Vpin and medium DDE.

The chip area outside the pixel arrays is covered with deep n-well as shown in Figure 2 and is effectively a large reverse-biased pn junction. At low substrate voltages (below Vthr of the worst- performing pixel variant) the substrate current of the whole chip should behave as in a typical photodiode,FigureFigure 11.11 and. WholeWhole increase chipchip (open (openlinearly symbols)symbols) with theandand light arrayarray flux. substratesubstrate This (closed (closedis indeed symbols)symbols) observed currentscurrents in curves inin aa 1010 µ(b)µmm pixelandpixel (c) in

Figuredesigndesign 11, and variantvariant can #3 #3be withwith used highhigh to verify VVpinpin and the medium illumination DDE. levels beyond PPD saturation.

4.2.3.4.2.3.The Full chip Well area LimitingLimiting outside the pixel arrays is covered with deep n-well as shown in Figure 2 and is effectively a large reverse-biased pn junction. At low substrate voltages (below Vthr of the worst- InIn somesome 1010 µµmm andand inin nearlynearly allall 5.45.4 µµmm pixelpixel variantsvariants wewe observedobserved signiﬁcantsignificant reductionreduction ofof thethe performing pixel variant) the substrate current of the whole chip should behave as in a typical FWCFWC under under zero zero or lowor low reverse reverse bias, whichbias, which fully or fully partially or partially recovers once recoversVBSB onceis increased VBSB is sufﬁciently. increased photodiode, and increase linearly with the light flux. This is indeed observed in curves (b) and (c) in Thesufficiently. effect is The mirrored effect inis mirrored the PTC asin well,the PTC and as an well, example and an from example a 5.4 µfromm pixel a 5.4 variant µm pixel is shownvariant inis Figure 11, and can be used to verify the illumination levels beyond PPD saturation. Figureshown 12 in. TheFigure FWC 12. gradually The FWC increases gradually until increases it is fully until restored it is tofully the restored level seen to in the the level reference seen pixels,in the andreference this occurs pixels, at and a reverse this occurs bias below at a thereverse threshold bias below voltage. the This threshold “recovery” voltage. is observed This “recovery” in all 10 µ mis 4.2.3. Full Well Limiting andobserved most 5.4in allµm 10 pixel µm variants and most showing 5.4 µm FWC pixel limiting. variants The showing effect is FWC more limiting. prominent The in effect pixel variantsis more withprominent deeperIn some in DDE 10pixel µm and variants and lower in nearlywithVpin, deeper as all summarized 5.4 DDE µm pixel and in lowervariants Table V2pin. we, as observedsummarized significant in Table reduction 2. of the FWC under zero or low reverse bias, which fully or partially recovers once VBSB is increased sufficiently. The effect is mirrored in the PTC as well, and an example from a 5.4 µm pixel variant is shown in Figure 12. The FWC gradually increases until it is fully restored to the level seen in the reference pixels, and this occurs at a reverse bias below the threshold voltage. This “recovery” is observed in all 10 µm and most 5.4 µm pixel variants showing FWC limiting. The effect is more prominent in pixel variants with deeper DDE and lower Vpin, as summarized in Table 2.

FigureFigure 12.12. Photo responseresponse ((aa)) andand aa PTCPTC ((bb)) ofof aa 5.45.4µ µmmpixel pixelvariant variant #2 #2with with low lowV Vpinpin and deepdeep DDEDDE

forfor sixsix VVBSB values.values. The The threshold threshold voltage voltage VVthrthr forfor this this pixel pixel is is 11.8 11.8 V. V.

Figure 12. Photo response (a) and a PTC (b) of a 5.4 µm pixel variant #2 with low Vpin and deep DDE

for six VBSB values. The threshold voltage Vthr for this pixel is 11.8 V.

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Table 2. Pixel variants in which full well capacity (FWC) limiting has been observed are indicated by a gray-ﬁlled box.

High Vpin Low Vpin 10 µm Shallow Medium Deep Medium Deep 1 2 3 4 5.4 µm 1 2 3 4

Simulations indicate that FWC limiting is caused by parasitic charge sharing between pixels, when the electrostatic potential in the DDE region is more positive than in the surrounding silicon at the same depth, and a potential pocket is formed as discussed in Section2. Due to the mesh-like structure of the DDE implant, the collected charge can propagate to adjacent pixels and eventually gets drained away by the n+ guard ring terminating the pixel array next to the last DDE implant (Figure2). The conditions for charge sharing can occur when the DDE doping concentration is too high and it cannot be fully depleted, or when its size is too large so that it begins to significantly overlap the PPD. As shown in the simulation in Figure4b, with increasing substrate bias the potential barrier under the p-well is lowered faster than the PPD pinning voltage and the DDE region becomes less attractive to electrons. At the same time, any potential pockets are gradually reduced and the mechanism for parasitic charge sharing is eliminated. Under flat field illumination and FWC limiting the photo response exhibits a distinct roll-off at the edges of the image array, which is attributed to the hypothesized charge drainage by the n+ guard ring. The observed reduction of the photo response at the edges is approximately 20% and vanishes once the FWC is restored. Due to design rule limitations for high energy implants, even the minimum length DDE occupies substantial part of a 5.4 µm pixel and extends over the p-well beyond the optimal implant size derived by simulations. This is largely avoided in the 10 µm pixels simply due to the difference in their size. As a consequence, most of the 5.4 µm pixel variants need reverse bias in order to eliminate the parasitic charge sharing.

4.3. X-Ray Response Low energy X-rays generate well deﬁned signal charges within the semiconductor volume, and offer an excellent characterization method for image sensors. This is used for measurements of the conversion gain, image lag, charge sharing and many other parameters. 55 Figure 13 shows the acquired spectrum from a Fe source, emitting characteristic Mn-Kα (5.9 keV) and Mn-Kβ (6.5 keV) X-rays, with a 10 µm pixel variant. The pixel exhibits approximately four percent lower FWC at VBSB = 0 V compared to −10 V, and its Vthr is above −15 V. Despite the limited FWC showing in the suppressed signal variance, the X-ray spectra at the different substrate voltages differ very little, with a hint of higher fraction of split X-ray events at lower VBSB. The system gain calibration obtained from the X-ray spectrum was 2.1 e−/ADU, which matches well the gain calculated from the PTC (2.0 e−/ADU). Sensors 2018, 18, x FOR PEER REVIEW 12 of 14 Sensors 2018, 18, 118 12 of 14 Sensors 2018, 18, x FOR PEER REVIEW 12 of 14

Figure 13. Data from a high Vpin, deep DDE 10 µm pixel size variant #4: (a) 55Fe X-ray spectrum taken

with VBSB = 0 V and −10 V; (b) PTC of the same pixel array showing FWC limiting.55 One ADU is 160.2 Figure 13.13. Data from a high VVpin,, deep deep DDE DDE 10 10 µmµm pixel size variant #4: (a) FeFe X X-ray-ray spectrum spectrum taken µV. with VBSB == 0 0V Vand and −10− 10V; ( V;b) (PTCb) PTC of the of thesame same pixel pixel array array showing showing FWC FWC limiting. limiting. One ADU One ADUis 160.2 is 160.2µV. µV. 4.4. Depletion Depth Measurements and PSF 4.4.4.4. Depletion Provided Depth that thereMeasurements is negligible and PSFleakage current, the chip design in Figure 2 ensures that the reverseProvided bias reaches that there every is part negligible of the device. leakage Nevertheless,current, the chip additional design measurementsin Figure 22 ensures ensures were that thatcarried thethe outreverse to verify biasbias reachesthis,reaches and every every to establish part part of of thethat the device. thedevice. device Nevertheless, Nevertheless, can indeed additional beadditional fully depleted. measurements measurements were were carried carried out toout verify toDespite verify this, thethis, and high and to establish resistivityto establish that epitaxial that the devicethe layer, device can the indeedcan resista indeed bence fully be of fully the depleted. frontdepleted.-to-back connection is low due toDespite the 600 the µm high-wide resistivity edge p-well epitaxial on a dielayer, with the size resistanceresista 5 mmnce × of5 mm. the front-to-backfrontThe -calculatedto-back connection resistance is of low 17 Ωdue is into athe reasonable 600 µmµm-wide-wide agreement edge edge p p-wellwith-well the on on measurement,a a die die with with size size which5 5mm mm ×gave ×5 mm.5 mm.21 ΩThe. The calculated calculated resistance resistance of 17 of 17Ω isΩ Ininis FSIa in reasonable a chips reasonable the darkagreement agreement current with is with dominated the the measurement, measurement, by defects which in which the gave bulk gave 21 silicon 21Ω.Ω .because the surface states are almostIn FSI fully chips suppressed the dark current by the is pinning dominated implant by defects [3], and in the bulkdark siliconcurrent because increase the is surface proportional states toare the almost depletion fully depth suppressed as shown by the in pinningthe diagram implant in Figure [3], and 14 the . Increasing dark current the reverse increase bias is proportional beyond full depletionto the depletion does not depth lead as to shown further in increase the diagram of the in dark Figure current, 14.. Increasing and the measurements the reverse bias in beyond Figure full14 [depletion10] from doesdoes two not 10not µm leadlead pixel to to further further variants increase increase confirm of of the the this. dark dark The current, current, results and areand the inthe measurements a measurements good agreement in Figure in Figure with 14 [ the10 14] expectationfrom[10] from two 10 two ofµm achieving 10 pixel µm variants pixel full depletion variants conﬁrm this. confirmat VBSB The = this.results−4 V, Thebased are results in on a goodthe are resistivity agreement in a good and with agreementthe the thickn expectation ess with of the the of epitaxial silicon. achievingexpectation full of depletion achieving at fullVBSB depletion= −4 V, basedat VBSB on = − the4 V, resistivity based on and the theresistivity thickness and of the the thickn epitaxialess silicon. of the epitaxial silicon.

FigureFigure 14 14.. DarkDark current current measurements measurements in in two two FSI FSI 10 10 µmµm pixels pixels and and a a diagram diagram illustrating illustrating the the principle principle of the measurement. ofFigure the measurement. 14. Dark current measurements in two FSI 10 µm pixels and a diagram illustrating the principle of the measurement. InIn BSI BSI devices devices,, the the dark dark current current is is a a factor factor of of five ﬁve larger, larger, and and is is most most likely likely due due to to imperfect imperfect paspassivationsivationIn BSI devices of of the back, the surface. dark current Because Because is a the thefactor dark dark of current currentfive larger, is is no no and longer longer is most dominated dominated likely due by by to bulk bulk imperfect silicon silicon defects,defects,passivation the the method methodof the back used used surface. for for the BecauseFSI devices the is dark not current feasible. is Instead, Instead, no longer spot spot dominated illumination illumination by bulkat at different different silicon wavelengthswavelengthsdefects, the method using a precisionused for thepinhole FSI devicesplaced on is notthe back feasible. sur surfaceface Instead, of the spot device illumination was used. atThe The different size size of of thethewavelengths imaged imaged spot spot using is is affected affecteda precision by by chargepinhole charge diffusion diffusionplaced on and and the can canback be be sur used usedface as asof an anthe indicator indicator device was of of theused. the extent extent The sizeof of the the of fieldﬁeld-freethe imaged-free region spot inis the affected device, by as charge shown diffusion in Figure and 15[ [can87].]. be used as an indicator of the extent of the field-free region in the device, as shown in Figure 15 [7].

Sensors 2018, 18, 118 13 of 14 Sensors 2018, 18, x FOR PEER REVIEW 13 of 14

Figure 15 15.. MeasurementMeasurement of of the the size size of ofa spot a spot illumination illumination in a in BSI a BSIdevice device with with high high Vpin, Vmediumpin, medium DDE atDDE five at wavelengths, ﬁve wavelengths, and a anddiagram a diagram illustrating illustrating the illustrating the illustrating the principle the principle of the of measurement. the measurement. The Thediameter diameter of the of pinhole the pinhole is 10 isµm. 10 µ m.

Short wavelengths (for example 470 nm, 0.6 µm absorption length in silicon) are absorbed near Short wavelengths (for example 470 nm, 0.6 µm absorption length in silicon) are absorbed near the back side, and if this region is field-free the charge will undergo some diffusion before collection. the back side, and if this region is field-free the charge will undergo some diffusion before collection. However, if the depletion reaches the back of the device there will be less diffusion, and the projected However, if the depletion reaches the back of the device there will be less diffusion, and the projected spot will appear sharper. Much longer wavelengths (for example 940 nm, 54 µm absorption length) spot will appear sharper. Much longer wavelengths (for example 940 nm, 54 µm absorption length) are absorbed throughout the thickness of the device and the charge spread is much less sensitive to are absorbed throughout the thickness of the device and the charge spread is much less sensitive to the the extent of depletion, in particular in our relatively thin 12 µm BSI devices. From these extent of depletion, in particular in our relatively thin 12 µm BSI devices. From these considerations considerations we expect the spot size to be less sensitive to the depletion depth (and by proxy on we expect the spot size to be less sensitive to the depletion depth (and by proxy on the reverse bias) as the reverse bias) as the illumination wavelength increases from 470 nm to 940 nm. the illumination wavelength increases from 470 nm to 940 nm. Figure 15 shows the measured spot sizes at five different wavelengths as a function of the reverse Figure 15 shows the measured spot sizes at five different wavelengths as a function of the reverse bias in a 10 µm pixel array. The cross section of the spot image in the horizontal direction was fitted bias in a 10 µm pixel array. The cross section of the spot image in the horizontal direction was fitted with a Gaussian curve and the standard deviation is plotted. with a Gaussian curve and the standard deviation is plotted. The data is consistent with an increase of the depletion depth with the applied reverse bias VBSB. The data is consistent with an increase of the depletion depth with the applied reverse bias VBSB. The size of the light spot levels off as the depletion edge reaches the back surface. The change of the The size of the light spot levels off as the depletion edge reaches the back surface. The change of the spot size is less prominent for longer wavelengths, as discussed above. spot size is less prominent for longer wavelengths, as discussed above.

55.. Conclusions and Outlook The characterization results from the newly developed reverse reverse-biased-biased PPD CMOS image sensor show successful operation. The device uses a new new method method for for leakage leakage current current suppression suppression by creating creating a “soft”, electricallyelectrically adjustableadjustable potential potential barrier barrier below below the the p-wells p-wells in in the the pixel pixel by by the the introduction introduction of anof anadditional additional deep deep n-type n-type implant. implant. This This allows allows reverse reverse bias to bias be appliedto be applied to the p-typeto the substratep-type substrate without withoutundesirable undesirable leakage currents,leakage currents, so that the so that active the semiconductor active semiconductor material material can be fully can be depleted. fully depleted. The operating principle creates new phenomena in PPD CIS such as signal-dependentsignal-dependent leakage current which increases exponentially above above a a threshold threshold reverse reverse bias, bias, and and charge charge sharing sharing effects. effects. However, wewe demonstratedemonstrate that that when when the the device device is is correctly correctly designed designed and and operated operated these these effects effects do notdo posenot pose serious serious limitations. limitations. The new The pixel new design pixel exhibits design exhibits nearly identical nearly performanceidentical performance to the traditional to the traditionalPPD pixelit PPD is based pixel on, it is with based the on, very with important the very difference important that difference the active that semiconductor the active semiconductor material can materialbe fully depletedcan be fully and depleted over-depleted. and over-depleted. This paper paper demonstrates demonstrates an an image image sensor sensor in inan an 18 18µmµ tmhick thick epitaxial epitaxial high high resistivity resistivity silicon, silicon, but thebut theprinciple principle of operation of operation allows allows much much greater greater depleted depleted thicknesses thicknesses to to be be achieved. achieved. The The upper thickness limit is most likely to be determined by the practicalities of applying high voltage to the device and the deterioration of the MTF due to the increased carrier transit time. Full depletion of the sensor has been demonstrated in both FSI and BSI chips using two different methods.methods. This development has the potential to greatly increase the quantum efficiency efﬁciency of PPD CIS at nearnear-IR-IR and soft soft X X-ray-ray wavelengths, wavelengths, due due to to the the potential potential to to realize realize sensors sensors with with sensitive sensitive thickness thickness in excessin excess of 100 of 100 µm.µ m.Likely Likely applications applications are arein sensors in sensors for astronomy, for astronomy, machine machine vision, vision, hyperspectral hyperspectral and highand high speed speed imaging, imaging, spectroscopy, spectroscopy, micro microscopyscopy and and surveillance, surveillance, as as well well as as for for consumer consumer nearnear-IR-IR imaging. Soft X-ray (<10 keV) imaging at synchrotron light sources and free electron lasers is also likely to use this technology.

Sensors 2018, 18, 118 14 of 14 imaging. Soft X-ray (<10 keV) imaging at synchrotron light sources and free electron lasers is also likely to use this technology. Future work will involve manufacturing of a large area CIS using one of the described pixel variants in a thicker epitaxial silicon, and also making a device on bulk silicon with thickness of at least 100 µm.

Acknowledgments: This work was supported by the UK Space Agency (UKSA) under grant RP10G0348A01. The cost for open access publication is covered by the International Image Sensor Society. The authors would like to thank Amos Fenigstein, Tomer Leitner, Keren Machluf and Efraim Aharoni from TowerJazz Semiconductor for their support during the design phase, and Simran Sawhney, Jean-Charles Nortier and Paul Jerram from Teledyne e2v for the back-thinning. Author Contributions: K.D.S. invented the operating principle of the device, performed TCAD simulations, led the chip design and characterization and wrote the paper; A.S.C. designed the chip and the support electronics; J.I. performed electro-optical characterization and data analysis; A.D.H. contributed to the project conception, management and academic supervision. Conﬂicts of Interest: The authors declare no conﬂict of interest.

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