High-Performance and Energy-Efficient Irregular Graph Processing on GPU Architectures

High-Performance and Energy-Efficient Irregular Graph Processing on GPU architectures Albert Segura Salvador Doctor of Philosophy Department of Computer Architecture Universitat Politècnica de Catalunya Advisors: Jose-Maria Arnau Antonio González July, 2020 2 Abstract Graph processing is an established and prominent domain that is the foundation of new emerging applications in areas such as Data Analytics, Big Data and Machine Learning. Appli- cations such as road navigational systems, recommendation systems, social networks, Automatic Speech Recognition (ASR) and many others are illustrative cases of graph-based datasets and workloads. Demand for higher processing of large graph-based workloads is expected to rise due to nowadays trends towards increased data generation and gathering, higher inter-connectivity and inter-linkage, and in general a further knowledge-based society. An increased demand that poses challenges to current and future graph processing architectures. To effectively perform graph processing, the large amount of data employed in these domains requires high throughput architectures such as GPGPU. Although the processing of large graph-based workloads exhibits a high degree of parallelism, the memory access patterns tend to be highly irregular, leading to poor GPGPU efficiency due to memory divergence. Graph datasets are sparse, highly unpredictable and unstructured which causes the irregular access patterns and low computation per data ratio, further lowering GPU utilization. The purpose of this thesis is to characterize the bottlenecks and limitations of irregular graph processing on GPGPU architectures in order to propose architectural improvements and extensions that deliver improved performance, energy efficiency and overall increased GPGPU efficiency and utilization. In order to ameliorate these issues, GPGPU graph applications perform stream compaction operations which process the subset of active nodes/edges so subsequent steps work on compacted dataset. Although this optimization is effective, we show that GPGPU architectures are inefficient at performing stream compaction due to the data movements it entails, and end up representing a significant part of the execution time. After identifying these issues, we propose to offload this task to a programmable Stream Compaction Unit (SCU) hardware extension tailored to the requirements of these operations, while the remaining steps of the graph-based algorithm are efficiently executed on the GPU cores. The SCU is a small unit tightly integrated in the GPU that efficiently gathers the active nodes/edges into a compacted array in memory. We further extend the SCU to perform pre-processing of the data by filtering and reordering elements processed. Besides the benefits achieved with offloading, this pre-processed SCU-prepared data improves GPU efficiency by reducing workload and achieving larger memory coalescing. We evaluate our SCU design with a wide variety of state-of-the-art graph applications and extended GPGPU architectures. The results show that for High-Performance and for Low-Power GPU systems the SCU achieves speedups of 1.37x and 2.32x, 84.7% and 69% energy savings, at the cost of a small area increase of 3.3% and 4.1% respectively. Memory divergence remains an important downside for irregular applications which struggle to fully exploit GPGPU performance. Although memory divergence can be improved by carefully considering architecture features and devoting significant programmer effort to modify algorithms with complex optimization techniques, it is far from an ideal solution which in the end shifts 3 programmers priorities. We show that in graph-based GPGPU irregular applications these inefficiencies prevail, yet we find that it is possible to relax the strict relationship between thread and data processed to empower new optimizations. Based on this key idea, we propose the Irregular accesses Reorder Unit (IRU). The IRU is a novel hardware extension tightly integrated in the GPGPU pipeline that reorders data processed by the threads on irregular accesses which significantly improves memory coalescing. Additionally, the IRU is capable of filtering and merging duplicated irregular accesses which reduces the application workload. These optimizations improve overall memory hierarchy and deliver increased performance and energy efficiency. Programmers can easily utilize the IRU with a simple API, or compiler optimized generated code with the extended ISA instructions provided. We evaluate our proposal for a wide variety of state-of-the-art graph-based algorithms. The IRU achieves a memory coalescing improvement of 1.32x and a 46% reduction in the overall traffic in the memory hierarchy, which results in 1.33x and 13% improvement in performance and energy consumption respectively, while incurring in a 5.6% area overhead. The increased need for greater data processing efficiency establishes high-throughput architectures, such as GPGPUs, as crucial devices in order enable efficient graph processing. Although efficient GPGPU graph processing faces many challenges, in our previous contributions we separately explore stream compaction offloading and improved coalescing of irregular access to ameliorate graph-based workload efficiency. While the SCU achieves significant speedups and large energy savings, it incurs in high contention in the Network-on-Chip (NoC). On the other hand, the IRU achieves more modest energy savings, but its optimizations are highly efficient at reducing contention in the NoC, showing up to a factor of 46% lower NoC traffic. We find that it is possible to leverage the strengths of both approaches to achieve synergistic performance improvements and higher graph processing efficiency. We do so by proposing a new unit, the IRU-enhanced SCU (ISCU). The ISCU employs the efficient mechanisms of the IRU to improve SCU stream compaction efficiency and throughput limitations. We first characterize the bottlenecks of our SCU contribution concluding that its major limitation is the large NoC traffic due to the pre-processing operations, i.e. filtering and grouping. With this insight we realize we can leverage the IRU hardware utilizing its strengths to efficiently perform the pre-processing. Consequently, the ISCU leverages both the powerful stream compaction offloading achieved by the SCU and the efficient filtering mechanism of the IRU employed to deliver pre-processing optimizations. We evaluate the ISCU for a wide variety of state-of-the-art graph-based algorithms and applications. Our final proposal achieves a 2.2x performance improvement and 90% energy savings which enable a 10x increase in energy-efficiency, improvements derived from a high reduction of 78% memory accesses, while incurring in 8.5% area overhead. 4 Keywords GPGPU, GPU, Graph Processing, Graph Exploration, Graph Applications, Data Analyt- ics, Stream Compaction, Stream Compaction Unit, SCU, Energy-Efficient, High-Performance, Irregular Applications, Irregular Accesses, Irregular Graph Processing, GPGPU Graph Pro- cessing, Irregular accesses Reorder Unit, IRU, ISCU, IRU-Enhanced SCU, Workload Filtering, Reordering, Accelerator, Hardware Accelerator, Custom Hardware, Tailored Hardware, Pro- grammability, Memory Divergence, Memory Coalescing, Memory Contention, Sparse Accesses, Branch Divergence, Control-Flow Divergence, Graphics Processing Unit, Computer Architecture. 5 Acknowledgements First and foremost, I would like to thank my advisors Professor Antonio González and Dr. Jose-Maria Arnau for their invaluable guidance through out my PhD study and research, their patience, motivation and many teachings. I would like to recognize their invaluable assistance, feedback and their involvement in my day-to-day work, for which I feel very grateful. I would like to thank my defense committee; Tor M. Aamodt, Jordi Tubella Murgadas and Julio Sahuquillo Borrás, for their valuable feedback and comments. It is an honor to have such prestigious committee. I wish to thank all the members and lab-mates of ARCO (the “The D6ers”) which I was lucky enough to share many moments during my PhD and be part of this amazing group of people. Special thanks to Gem Dot, Enrique de Lucas, Martí Torrents, Josue Quiroga with whom I shared the beggining of my PhD. I was lucky to share the majority of my stay at ARCO with Hamid Tabani, Reza Yazdani, Martí Anglada, Marc Riera, Franyell Silfa and Syeda Azmath thank you for all the good moments that we shared at UPC. Finally, I would like to wish good luck to the newcomers Dennis Pinto, Diya Joseph, Pedro Exenberger, Jorge Sierra, Raúl Taranco and Mehdi Hassanpour, I am sure will do an amazing work. I would also like to thank university colleagues, campus mates and friends with whom I shared many years, projects, difficulties and successes over the course of my stay in the University. Special thanks to Pedro Benedicte, Constantino Gomez, Cristóbal Ortega and David Trilla (the “Cache Miss” group) for the many experiences shared. And thanks to the many others with which I have cross path during this endeavor. Finally, I would like to thank close friends and my family for their unconditional support and encouragement. To my parents for their love and support enabling me from the very beginning to pursue my passion for computers, electronics and education. To my brother and sister for the encouragement and for enduring me. And to my grandparents and extended family for their love, support and endorsement that has undoubtedly led me to where I am today. Finally, the last words I have saved for my partner with whom I closely

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