DLP-2232H-SF Module Is a Low-Cost, Compact Prototyping Tool That Can Be Used for Rapid Proof of Concept Or Within Educational Environments

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FEATURES:

• Microsemi/Actel SmartFusion™ Customizable System-on-Chip (cSoC) FPGA • Internal 100MHz, 32-Bit ARM® Cortex™-M3 Microcontroller Subsystem (MSS) • Internal 100MHz RC Oscillator--1% Accurate • 256Kbytes Embedded, Nonvolatile Flash Memory; 64Kbytes Embedded SRAM Memory • Cypress 4-Mbit (256K x 16) SRAM Memory--PCB Supports up to 64-Mbit SRAM • MSS Peripherals Include: UART, SPI, I2C, Timers, RTC, 8-Channel DMA • 10/100 Ethernet MAC with RMII Interface and External 50MHz Oscillator • Two Configurable 8/10/12-Bit SAR ADC’s with Sample Rates up to 600KSPS • Two Configurable 8/16/24-Bit Input Sigma-Delta DAC’s • Two Active Bipolar Prescaler Analog Inputs (ABPS); Supports Voltages in Excess of 10 Volts

Rev. 1.0 (December 2012) 1 © DLP Design, Inc. • Internal 2.56V Reference or Optional External Reference • FPGA Fabric Includes 4,608 Tiles and 36,864 Bits of Block RAM • 14 Analog Inputs; 2 Analog Outputs; 16 MSS/GPIO I/O’s, 10 MSS/FPGA I/O’s • Analog Compute Engine (ACE) Supports Digital Filtering, Transformations and Threshold Flags • Complete Combined USB Microcontroller-FPGA Reference Design Provided • USB Port Powered or 5V External Power Barrel Jack • USB 1.1- and 2.0-Compatible Interface • Small Footprint: 3.0 x 1.2-Inch PCB and Standard 50-Pin, 0.9-Inch DIP Interface

APPLICATIONS:

• Rapid Prototyping • Educational Tool • Industrial/Process Control • Data Acquisition/Processing • Embedded Processor

1.0 INTRODUCTION

The DLP-2232H-SF module is a low-cost, compact prototyping tool that can be used for rapid proof of concept or within educational environments. The module is based on the Microsemi SmartFusionTM cSoC microcontroller-FPGA and Future Technology Devices International’s FT2232H dual-channel high-speed USB IC. The DLP-2232H-SF provides both the beginner as well as the experienced engineer with a rapid path to developing FPGA-based designs. When combined with the Libero™ SoC and SoftConsole™ IDE tools from Microsemi, this module is more than sufficient for creating anything from basic logical functions to a highly complex system controller.

The DLP-2232H-SF is fully compatible with the free Libero™ SoC and SoftConsole™ IDE tools from Microsemi. Libero™ SoC is used to configure the ARM® Cortex™-M3 Microcontroller Subsystem (MSS) and the FPGA fabric design. Libero™ supports HDL synthesis and simulation, implementation, timing verification, device fitting and JTAG programming. SoftConsole™ is based on the Eclipse IDE and is used to compile, download and debug the C/C++ source code that runs on the MSS.

The DLP-2232H-SF has on-board voltage regulators that generate all required power supply voltages from a single 5-volt source. Power for the module can be taken from either the host USB port or from a user-supplied, external 5-volt power supply via an onboard standard barrel connector:

Connection to user electronics is made via a 50-pin, 0.9-inch wide, industry-standard 0.025-square inch post DIP header on the bottom of the board. The bottom-side, 50-pin header provides access to 42 of the SmartFusion™ cSoC MSS and FPGA input/output pins. This connector header mates with a user-supplied, standard, 50-pin, 0.9-inch spaced DIP socket.

Rev. 1.0 (December 2012) 2 © DLP Design, Inc.

DIP Socket

Other on-board features include a 256K x 16 SRAM external memory IC for use by the MSS through its External Memory Controller (EMC), a JTAG port connector for debug and programming, a JTAG mode-select header, an external battery header and a voltage-reference selection header.

2.0 REFERENCE DESIGN

A working reference design is available for the SmartFusion™ cSoC FPGA on the DLP-2232H-SF to those who purchase the module. A README file is included with the download file that explains the use of the project and the tools in detail. The hardware design is written in VHDL and built using the free Libero™ SoC tools. The software design is written in C and built using the free SoftConsole™ IDE. The reference design consists of the following blocks:

Rev. 1.0 (December 2012) 3 © DLP Design, Inc.

The reference design can be divided into MSS configuration and software and FPGA fabric portions. The MSS configuration uses the internal RC oscillator to derive the 100MHz clock used by the processor. It utilizes the Analog Compute Engine (ACE) to initialize both ADC’s in 12-bit mode and both DAC’s in 8-bit mode. ADC0 is configured to use the Programmable DMA (PDMA) controller to transfer 8,192 raw samples at 83.2 KSPS to the internal memory. ADC1 and the two DAC’s are configured for single-sample operation.

The MSS uses internal Flash memory to store the executable code and the internal SRAM to store variables such as the ADC0 samples mentioned above. The External Memory Controller (EMC) is used to control the external 256K x 16 SRAM memory. It is configured for asynchronous RAM, byte enable used, half word port, with a read latency of 1. The MSS also uses the Fabric Interface configured as a master, the GPIO controller, UART 1 when debug is enabled and the timer peripheral.

The FPGA fabric design uses just over 46% of the available logic resources in the A2F200M3F device. To allow the MSS to connect to the FPGA fabric, an AHB Lite Interface Core is used. It is configured so that the MSS is master and the FPGA fabric is slave. The entire FPGA fabric design is clocked by the 50MHz clock provided by the AHB Lite Interface so that it is synchronized with the MSS.

The FPGA fabric design contains a USB Data Interface, a USB State Machine, an AHB Lite Data Interface, shared memory for communication between the FPGA and the MSS and a Pin State Machine. Several support blocks are required to count wait states and data transfers in order to generate the AHB Ready pulse due to its unique timing requirements and to provide a watchdog timer in case the MSS stops responding.

The USB interface captures, interprets and returns command and data bytes sent from the host PC through the FTDI USB interface to the FPGA. Commands include Ping, Return Status, Loopback Data, Set or Clear an I/O Pin, Read an I/O Pin, Test External Memory, Configure the DAC’s and Acquire Samples from the ADC’s. (Section 11 explains these in detail.)

The DLP-2232H-SF module supports user access to 43 of the SmartFusion™ cSoC pins via the J1 Connector on the bottom of the module. Of these 43 pins, 16 have analog functionality, 17 are connected to the MSS and can support GPIO or MSS functions and 10 can be connected to the FPGA fabric or the Ethernet MAC peripheral. One of the MSS pins is dedicated to the internally pulled up/ active low MSS Reset Pin. In addition, one of the MSS GPIO pins is used to control the module's D3 LED. The analog pins include 14 that can be analog inputs and 2 that can be analog outputs. Eight of the analog inputs can also be digital inputs. The functionality of these pins is configured by the project loaded into the SmartFusion™ cSoC device.

The reference design loaded into the DLP-2232H-SF module configures the user access on the J1 Connector as follows:

Of the 16 possible analog pins, 8 are configured as analog inputs and can be connected internally to the two ADC’s under MSS control, 2 are analog outputs and are connected to the 2 DAC’s and 6 are configured as digital inputs. Of the remaining pins, 16 are configured as MSS GPIO, 8 are configured as digital inputs, 2 are configured as digital inputs and 1 pin is used as the MSS Reset input.

Rev. 1.0 (December 2012) 4 © DLP Design, Inc. The reference design occupies the following device resources on the DLP-2232H-SF module’s A2F200M3F:

More reference designs are planned. Please contact DLP Design with any specific requests.

3.0 FPGA SPECIFICATIONS

The device used on the DLP-2232H-SF is the Microsemi SmartFusion™ A2F200M3F-1FGG256

• Part Number: A2F200M3F-1FGG256 • ARM® Cortex™-M3: 1 • Flash (Kbytes): 256 • SRAM (Kbytes): 64 • 10/100 Ethernet MAC: 1 • UART: 2 • I2C: 2 • SPI: 2 • ADC’s (8-, 10-, 12-bit SAR): 2 • DAC’s (12-Bit Sigma-Delta): 2 • FPGA System Gates: 200,000 • FPGA Tiles (D Flip-Flops): 4,608 • FPGA Block RAM Bits: 36,864

Rev. 1.0 (December 2012) 5 © DLP Design, Inc. 4.0 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed here may cause permanent damage to the DLP-2232H-SF:

Operating Temperature: 0-70°C

Voltage on Digital Inputs with Respect to Ground: -0.5V to +4.1 V

Sink/Source Current on Any I/O: 8mA (MSS I/O) 12mA (FPGA I/O 3.3V LVTTL/LVCMOS)

5.0 WARNINGS

• Unplug from the host PC and power adapter before connecting to I/O pins on the DLP-2232H-SF.

• Isolate the bottom of the board from all conductive surfaces.

• Observe static precautions to prevent damage to the DLP-2232H-SF module.

6.0 EEPROM SETUP / MPROG

The DLP-2232H-SF has a dual-channel USB interface to the host PC. Channel A is used exclusively to connect the host PC to the FPGA fabric on the SmartFusion™ cSoC device. Channel B is connected to the SmartFusion™ device’s JTAG programming port and debug port (J2) for future use. A 93LC56B EEPROM connected to the USB interface IC is used to store the USB port setup for the two channels. The parameters stored in the EEPROM include the Vendor ID (VID), Product ID (PID), serial number, description string, driver selection (VCP or D2XX) and port type (UART serial or FIFO parallel).

To use the reference design, D2XX drivers and 245 FIFO mode must be selected in the EEPROM for Channel A. Channel B is currently configured to also use the 245 FIFO mode, but it can use either the VCP or D2XX drivers as this port is not currently being utilized. The VCP drivers make the DLP-2232H-SF appear as an RS232 port to the host application. The D2XX drivers provide faster throughput, but they require working with a *.lib or *.dll library in the host application.

The operational modes and other EEPROM selections are written to the EEPROM using the MPROG utility. This utility and its manual are available for download from the bottom of the page at www.dlpdesign.com.

7.0 JTAG INTERFACE

To program and debug the SmartFusion™ cSoC device, a JTAG header (J2) is provided on the DLP-2232H-SF. (A FlashPro4 programming cable is required. This cable is available for purchase from Microsemi.) Connect the ribbon cable to the DLP-2232H-SF module as follows:

Rev. 1.0 (December 2012) 6 © DLP Design, Inc. 8.0 TEST PROGRAMMING FILE

The DLP-2232H-SF module comes pre-programmed with the reference design discussed in Section 2 of this datasheet. (This test programming file is also provided as a download from the DLP Design website to those who purchase the module.) The reference design provides access to the MSS and I/O features of the DLP-2232H-SF. The following USB command features are provided for the host PC’s use:

• Ping • Read ARM Status Registers • Drive I/O Pins High/Low or Read their High/Low State • Test the External Memory • Configure the DAC Outputs • Read the ADC Inputs

The command structure that supports these features is explained in Section 11.

9.0 USB DRIVERS

USB drivers for the following operating systems are available for download from the DLP Design website at www.dlpdesign.com:

OPERATING SYSTEM SUPPORT Windows 7 32-bit Windows 7 64-bit Windows Vista, Vista x64 Mac OSX Windows XP, XP x64 Mac OS9 Windows Server 2008, x64 Mac OS8 Windows Server 2003, x64 Linux Windows 2000 Windows CE 4.2-6.0

Note: If you are utilizing the dual-mode drivers from FTDI (CDM2.x.x) and you want to use the Virtual COM Port (VCP) drivers, then it may be necessary to disable the D2XX drivers first via Device Manager. To do so, right click on the entry under USB Controllers that appears when the DLP-2232H-SF is connected, select Properties, select the Advanced tab, check the option for Load VCP and click OK. Then unplug and replug the DLP-2232H-SF, and a COM Port should appear in Device Manager under Ports (COM & LPT).

Rev. 1.0 (December 2012) 7 © DLP Design, Inc. 10.0 HEADER DEFINITIONS

The DLP-2232H-SF has five user-accessible headers. The first is J1 which is located on the bottom side of the module, and the remaining four are J2 to J5, which are located on the top:

Individual header pinouts are described in the following tables:

TABLE 1 J1: User I/O Test DLP-2232H- A2F200 A2F200 App I/O SF J1 Pin Pin Block Signal Description Number J1 Pin 1 R3 MSS Analog ABPS0: Active Bipolar Prescaler Input 0 J1 Pin 2 R11 MSS Analog ABPS4: Active Bipolar Prescaler Input 4 J1 Pin 3 GND Power Ground J1 Pin 4 R2 MSS Analog SDD0: DAC 0 Output J1 Pin 5 T12 MSS Analog SDD1: DAC 1 Output J1 Pin 6 M5 MSS Analog/ 0x03 ADC3: ADC Direct Input 3 or Digital Input Digital In J1 Pin 7 R6 MSS Analog/ 0x01 ADC1: ADC Direct Input 1 or Digital Input Digital In J1 Pin 8 T5 MSS Analog/ ADC0: ADC Direct Input 0 or Digital Input Digital In J1 Pin 9 R9 MSS Analog/ 0x07 ADC7: ADC Direct Input 7 or Digital Input Digital In J1 Pin 10 P9 MSS Analog/ 0x06 ADC6: ADC Direct Input 6 or Digital Input Digital In J1 Pin 11 P7 MSS Analog/ 0x02 ADC2: ADC Direct Input 2 or Digital Input Digital In J1 Pin 12 M9 MSS Analog/ ADC4: ADC Direct Input 4 or Digital Input Digital In

Rev. 1.0 (December 2012) 8 © DLP Design, Inc. J1 Pin 13 N9 MSS Analog/ 0x05 ADC5: ADC Direct Input 5 or Digital Input Digital In J1 Pin 14 P6 MSS Analog CM1: Current Monitor/Comparator Input 1 J1 Pin 15 N6 MSS Analog TM1: Current Monitor/Comparator/Temperature Input 1 J1 Pin 16 N10 MSS Analog CM3: Current Monitor/Comparator Input 3 J1 Pin 17 P10 MSS Analog TM3: Current Monitor/Comparator/Temperature Input 3 J1 Pin 18 GND Power Ground J1 Pin 19 N16 MSS Digital 0x16 DO0/GPIO16: SPI 0 Data Output/MSS GPIO 16 J1 Pin 20 M13 MSS Digital 0x19 SS0/GPIO19: SPI 0 Slave Select/MSS GPIO 19 J1 Pin 21 M16 MSS Digital 0x17 DI0/GPIO17: SPI 0 Data Input/MSS GPIO 17 J1 Pin 22 M15 MSS Digital 0x18 CK0/GPIO18: SPI 0 Clock/MSS GPIO 18 J1 Pin 23 +5V IN Power +5V Input to the DLP-2232H-SF J1 Pin 24 +5V Power +5V Supplied by Host PC USB Port USB J1 Pin 25 GND Power Ground J1 Pin 26 GND Power Ground J1 Pin 27 K15 MSS Digital 0x29 RX1/GPIO29: UART 1 Transmit/MSS GPIO 29 J1 Pin 28 K14 MSS Digital 0x28 TX1/GPIO28: UART 1 Receive/MSS GPIO 28 J1 Pin 29 K16 MSS Digital 0x20 TX0/GPIO20: UART 0 Transmit/MSS GPIO 20 J1 Pin 30 K12 MSS Digital 0x21 RX0/GPIO21: UART 0 Receive/MSS GPIO 21 J1 Pin 31 J16 MSS Digital 0x30 SD1/GPIO30: I2C 1 Serial Data Input/Output/ MSS GPIO 30 J1 Pin 32 J14 MSS Digital 0x31 SC1/GPIO31: I2C 1 Serial Clock Output/MSS GPIO 31 J1 Pin 33 J13 MSS Digital 0x22 SD0/GPIO22: I2C 0 Serial Data Input/Output/ MSS GPIO 22 J1 Pin 34 J12 MSS Digital 0x23 SC0/GPIO23: I2C 0 Serial Clock Output/MSS GPIO 23 J1 Pin 35 L13 MSS Digital 0x27 MSS GPIO 27 J1 Pin 36 L15 MSS Digital 0x25 MSS GPIO 25 J1 Pin 37 L14 MSS Digital 0x26 MSS GPIO 26 J1 Pin 38 K4 MSS Reset Active Low MSS Reset Input (internal pull-up) J1 Pin 39 GND Power Ground J1 Pin 40 L12 MSS Digital 0x24 MSS GPIO 24/LED D3 J1 Pin 41 E3 FPGA Fabric 0x68 FPGA Fabric I/O J1 Pin 42 L3 FPGA Fabric 0x21 CSDV: RMII Carrier Sense/Receive Data Valid/ FPGA Fabric I/O J1 Pin 43 K1 FPGA Fabric 0x23 MDIO: RMII Management Data Input/Output/ FPGA Fabric I/O J1 Pin 44 K2 FPGA Fabric 0x24 MDC: RMII Management Clock/FPGA Fabric I/O J1 Pin 45 L2 FPGA Fabric 0x20 TXEN: RMII Transmit Enable/FPGA Fabric I/O J1 Pin 46 M1 FPGA Fabric 0x16 TXD0: RMII Transmit Data Bit 0/FPGA Fabric I/O J1 Pin 47 M2 FPGA Fabric 0x17 TXD1: RMII Transmit Data Bit 1/Receive Data Valid/FPGA Fabric I/O J1 Pin 48 N1 FPGA Fabric 0x19 RXD1: RMII Receive Data Bit 1/Receive Data Valid/FPGA Fabric I/O

Rev. 1.0 (December 2012) 9 © DLP Design, Inc. J1 Pin 49 M3 FPGA Fabric 0x18 RXD0: RMII Receive Data Bit 0/Receive Data Valid/FPGA Fabric I/O J1 Pin 50 L4 FPGA Fabric 0x22 RERR: RMII Receive Error/FPGA Fabric I/O

TABLE 2 J2: JTAG Port DLP- A2F200 A2F200 2232H-SF Pin Block Signal Description J2 Pin J2 Pin 1 G15 JTAG JTAG_TCK: JTAG Test Clock J2 Pin 2 GND Power Ground J2 Pin 3 H13 JTAG JTAG_DOUT: JTAG Test Data Output J2 Pin 4 Not Connected J2 Pin 5 G14 JTAG JTAG_TMS: JTAG Test Mode Select J2 Pin 6 +3.3V Power +3.3V Power J2 Pin 7 Power Pull-up to +3.3V (not installed) J2 Pin 8 G13 JTAG JTAG_TRST: JTAG Test Reset J2 Pin 9 H14 JTAG JTAG_DIN: JTAG Test Data Input J2 Pin 10 GND Power Ground

TABLE 3 J3: JTAG Select DLP- A2F200 A2F200 2232H-SF Pin Block Signal Description J3 Pin J3 Pin 1 GND Power Pull-down to Ground JTAGSEL: JTAG Controller Select Input

J3 Pin 2 H15 JTAG 0=Debug Cortex-M3 1=Program SmartFusion™ J3 Pin 3 +3.3V Power Pull-up to +3.3V

TABLE 4 J4: Voltage Reference Input DLP- A2F200 A2F200 2232H-SF Pin Block Signal Description J4 Pin J4 Pin 1 N12 MSS Analog VREF_OUT: Internal Voltage Reference Output (+2.5V) J4 Pin 2 T6 MSS Analog VAREF0_IN: Voltage Reference Input 0 J4 Pin 3 GND Power Ground J4 Pin 4 N12 MSS Analog VREF_OUT: Internal Voltage Reference Output (+2.5V) J4 Pin 5 T9 MSS Analog VAREF1_IN: Voltage Reference Input 1 J4 Pin 6 GND Power Ground

Rev. 1.0 (December 2012) 10 © DLP Design, Inc. TABLE 5 J5: External Battery Input DLP- A2F200 A2F200 2232H-SF Pin Block Signal Description J5 Pin P14 VDDBAT: External Battery Connection to the Low-Power J5 Pin 1 MSS Digital RTC and Battery Switch Over Circuit J5 Pin 2 GND Power Pull-Down to Ground

11.0 USING THE DLP-2232H-SF

Select a power source via J1 Header Pins 23 and 24, and connect the DLP-2232H-SF to the PC to initiate the loading of USB drivers. The easiest way to do this is to connect Pins 23 and 24 to each other. This will result in operational power being taken from the host PC. Once the drivers are loaded, the DLP-2232H-SF is ready for use. (All commands issued consist of one or two bytes.)

You can either utilize the Test Application available from www.dlpdesign.com/test.shtml with the DLP-2232H-SF (as described in Section 12), or you can write your own program in your language of choice.

If you are using the VCP drivers, begin by opening the COM Port, and send multi-byte commands as shown in Table 6 below. There is no need to set the baud rate because the DLP-2232H-SF uses a parallel interface between the USB IC and the FPGA. (The Ping Command can be used to locate the correct COM Port used for communicating with the DLP-2232H-SF, or you can look in Device Manager to see which port was assigned by Windows.) If you are using the D2XX drivers as with the Test Application, no COM Port selection is necessary.

Rev. 1.0 (December 2012) 11 © DLP Design, Inc.

TABLE 6 Command Packets Command Hex Description Byte Return/Comments Packet Value FPGA Ping Issues 0 0x00 FPGA Ping Command - 0x4D (ASCII "M") will be FPGA Ping returned indicating that the DLP-2232H-SF is found Request on the selected port. Read Accesses 0 0x10 Read Version/Status Registers Command Version the Internal Version 1 0xnn Register Address: 0xnn

0x00=Board ID 0x01=FPGA Type ID: 0xF2=A2F200M3F 0x02=Design Version ID 1 (Design Month) 0x03=Design Version ID 2 (Design Day) 0x04=Design Version ID 3 (Design Year) 0x05=Design Version ID 4 (Design Version)

Loopback Returns the 0 0x20 Loopback Command Data Byte Received 1 0xnn The byte sent to the DLP-2232H-SF (0xnn) will be returned back. Loopback Returns the 0 0x21 Loopback Compliment Command Compliment Compliment of Data Byte 1 0xnn The byte sent to the DLP-2232H-SF (0xnn) will be Received complimented and returned back. Read Pin Reads 0 0x30 Read FPGA Input Pin Command FPGA the State of Input One of the 1 0x01 (The FPGA fabric valid input pin numbers are FPGA described in Table 7.) Pin 0x02 Fabric Input 0x03 FPGA Input Pin 0xnn is read and returns: Pins 0x05

0x06 0x00=User I/O pin 0xnn is low 0x07 0x01=User I/O pin 0xnn is high 0x21 0x23

Clear Forces the 0 0x40 Clear FPGA Output Pin Command FPGA Selected Output FPGA 1 0x16 The FPGA fabric valid output pin numbers are Output Pin described in Table 7. Pin : Low 0x20 FPGA Output Pin 0xnn is cleared, and the specified 0x22 user output pin number is returned. 0x24 0x68

Set Forces the 0 0x41 Set FPGA Output Pin Command FPGA Selected Output FPGA 1 0x16 The FPGA fabric valid output pin numbers are Output Pin : described in Table 7.

Rev. 1.0 (December 2012) 12 © DLP Design, Inc. Pin High 0x20 0x22 FPGA Output Pin 0xnn is set, and the specified user 0x24 output pin number is returned. 0x68

Write Writes the 0 0x5n Write to the shared memory location "n": Shared Specified Memory Shared 0x50=Shared Memory Byte 0, To Host Status Location Memory 0x51=Shared Memory Byte 1, To Host Command Location 0x52=Shared Memory Byte 2, To Host Data 0 (shared 0x53=Shared Memory Byte 3, To Host Data 1 between 0x54=Shared Memory Byte 4, From Host Status ARM and 0x55=Shared Memory Byte 5, From Host Command FPGA 0x56=Shared Memory Byte 6, From Host Data 0 fabric) 0x57=Shared Memory Byte 7, From Host Data 1

1 0xnn Value to be written to specified location; the command byte sent is returned.

Read Returns the 0 0x6n Reads the shared memory location "n", and the Shared Value in the value in the specified location is returned: Memory Specified Location Shared 0x60=Shared Memory Byte 0, To Host Status Memory 0x61=Shared Memory Byte 1, To Host Command Location 0x62=Shared Memory Byte 2, To Host Data 0 (shared 0x63=Shared Memory Byte 3, To Host Data 1 between 0x64=Shared Memory Byte 4, From Host Status ARM and 0x65=Shared Memory Byte 5, From Host Command FPGA 0x66=Shared Memory Byte 6, From Host Data 0 fabric) 0x67=Shared Memory Byte 7, From Host Data 1

ARM Ping Issues ARM 0 0x70 ARM Ping Command returns: Ping Request 0xC3 indicates ARM Cortex-M3 is running 0xE8 indicates ARM Cortex-M3 is stopped

Note: Watchdog timeout occurs after about 2 seconds of ARM core inactivity.

Rev. 1.0 (December 2012) 13 © DLP Design, Inc. ARM Returns the 0 0x8n ARM Status Read returns the value of the following: Status Read Specified ARM Status 0x80=MSS Status Register (MSS_SR) Register Bit 5=PLLLOCKLOSTINT Value Bit 4=PLLLOCKINT Bits 3-0 same as Users Guide 0x81 =MSS Device Status Register (DEVICE_SR) 0x82=MSS PLL Status Register (MSS_CCC_SR) 0x83=MSS Soft Reset Register (SOFT_RST_CR) Bit 7=FPGA_SR Bit 6=EXT_SR Bit 5=UART_1_SR Bit 4=UART_0_SR Bits 3-0 same as Users Guide 0x84=Fabric Interface Register (FAB_IF_CR) 0x85=Fabric Interface Configuration Register (FAB_AHB_HIWORD_DR) 0x86=AHB Bus Matrix Register (AHB_MATRIX_CR) 0x87=UART 1 Line Control Register (LCR) 0x88=UART 1 Line Status Register (LSR) 0x89=GPIO 16 Configuration Register (GPIO_16_CFG) 0x8A=SW Build Number (set as #DEFINE in "main.c")

Refer to the SmartFusionTM MSS Users Guide master, UART and GPIO register map for bit definitions. (Bits 7-0 match Users Guide except as noted above.)

Read Pin Reads 0 0x90 Read FPGA Input Pin Command ARM the State of MSS One of the 1 0x16 The ARM MSS valid I/O pin numbers are described ARM MSS in Table 7. The range of valid values is 16 through I/O : I/O Pins 0x31 31. Pin MSS I/O Pin 0xnn is read and returns:

0x00=User I/O pin 0xnn is low 0x01=User I/O pin 0xnn is high

Clear Clears the 0 0xA0 Clear ARM MSS I/O Pin Command ARM State of MSS One of the 1 0x16 The ARM MSS valid I/O pin numbers are described ARM MSS in Table 7. The range of valid values is 16 through I/O : I/O Pins 0x31 31. Pin ARM MSS Pin 0xnn is cleared. The specified user output pin number is returned.

Rev. 1.0 (December 2012) 14 © DLP Design, Inc. Set Sets the 0 0xA1 Set ARM MSS I/O Pin Command ARM State of MSS One of the 1 0x16 The ARM MSS valid I/O pin numbers are described ARM MSS in Table 7. The range of valid values is 16 through I/O : I/O Pins 0x31 31. Pin ARM MSS Pin 0xnn is cleared. The specified user output pin number is returned.

Test Performs a 0 0xB0 The Test External Memory Command writes all 256K External Test on the word locations with a known pattern, and then it Memory External reads all locations to verify the memory's 265Kx16 functionality. Returns: SRAM 0x00=Memory test failed 0x01=Memory test passed

DAC 0 Loads and 0 0xC0 Configure DAC 0 Command Configure Enables DAC 0 1 0xnn 0xnn=Load value between 0x00 and 0xFF. DAC output range: 0-2.56V.

The value 0xnn is returned.

Note: DAC is configured as 8 bits in the reference design, but can be configured for 16- or 24-bit operation.

DAC 1 Loads and 0 0xC1 Configure DAC 1 Command Configure Enables DAC 1 1 0xnn 0xnn=Load value between 0x00 and 0xFF. DAC output range: 0-2.56V.

The value 0xnn is returned.

Note: DAC is configured as 8 bits in the reference design, but can be configured for 16- or 24-bit operation.

DAC 0 Turns Off 0 0xC2 Disable DAC 0 Command Disable DAC 0 DAC 1 Turns off 0 0xC3 Disable DAC 1 Command Disable DAC 1 ADC0 Input Returns mV 0 0xD0 Single analog sample read from input ADC0 (J1 Pin Single Converted 8) using convertor ADC 0. Result converted to mV. Sample ADC (mV) Sample Returns 16-bit mV sample--MS byte first, followed by LS byte.

Rev. 1.0 (December 2012) 15 © DLP Design, Inc. ADC4 Input Returns mV 0 0xD1 Single analog sample read from input ADC4 (J1 Pin Single Converted 12) using convertor ADC 1. Result converted to mV. Sample ADC (mV) Sample Returns 16-bit mV sample--MS byte first, followed by LS byte.

ADC0 Input Returns 0 0xD2 Single analog sample read from input ADC0 (J1 Pin Single Raw ADC 8) using convertor ADC 0. Raw count returned. Sample Sample (raw) Returns 12-bit raw sample right justified to 16 bits-- MS byte first, followed by LS byte.

ADC4 Input Returns 0 0xD3 Single analog sample read from input ADC4 (J1 Pin Single Raw ADC 12) using convertor ADC 1. Raw count returned. Sample Sample (mV) Returns 12-bit raw sample right justified to 16 bits-- MS byte first, followed by LS byte.

ABPS0 Returns 0 0xD4 Single analog sample read from input ABPS0 (J1 Pin Input Single Raw ADC 1) using convertor ADC 0. Raw count returned. Sample Sample (raw) Returns 12-bit raw sample right justified to 16 bits-- MS byte first, followed by LS byte.

ABPS4 Returns 0 0xD5 Single analog sample read from input ABPS4 (J1 Pin Input Single Raw ADC 2) using convertor ADC 1. Raw count returned. Sample Sample (raw) Returns 12-bit raw sample right justified to 16 bits-- MS byte first, followed by LS byte.

CM1 Input Returns 0 0xD6 Single analog sample read from input CM1 (J1 Pin Single Raw ADC 14) using convertor ADC 0. Raw count returned. Sample Sample (raw) Returns 12-bit raw sample right justified to 16 bits-- MS byte first, followed by LS byte.

CM3 Input Returns 0 0xD7 Single analog sample read from input CM3 (J1 Pin Single Raw ADC 16) using convertor ADC 0. Raw count returned. Sample Sample (raw) Returns 12-bit raw sample right justified to 16 bits-- MS byte first, followed by LS byte.

TM1 Input Returns 0 0xD8 Single analog sample read from input TM1 (J1 Pin Single Raw ADC 15) using convertor ADC 0. Raw count returned. Sample Sample (raw) Returns 12-bit raw sample right justified to 16 bits-- MS byte first, followed by LS byte.

Rev. 1.0 (December 2012) 16 © DLP Design, Inc. TM3 Input Returns 0 0xD9 Single analog sample read from input TM3 (J1 Pin Single Raw ADC 17) using convertor ADC 0. Raw count returned. Sample Sample (raw) Returns 12-bit raw sample right justified to 16 bits-- MS byte first, followed by LS byte.

Internal Returns 0 0xDA Single analog sample read from ADC 0 based on DAC0 to Raw ADC internal connection to DAC 0. Raw count returned. ADC0 Test Sample (raw) Returns 12-bit raw sample right justified to 16 bits-- MS byte first, followed by LS byte.

Internal Returns 0 0xDB Single analog sample read from ADC 1 based on DAC1 to Raw ADC internal connection to DAC 1. Raw count returned. ADC1 Test Sample (raw) Returns 12-bit raw sample right justified to 16 bits-- MS byte first, followed by LS byte.

The I/O Pin Read/Set/Clear Commands I/O number mapping to the physical I/O pins on the DLP-2232H-SF board are described in the following table:

Rev. 1.0 (December 2012) 17 © DLP Design, Inc. TABLE 7 MSS and User I/O J1 Pin U5 Pin I/O (Bottom- (SmartFus Schematic Source Description Code Side ionTM Net Name Connector) Device) MSS 0x16 19 N16 DO0_MSS_GPIO MSS multipurpose pin: SPI 0 (0x90, 16 Data Output or GPIO Bit 16. 0xA0, Configured as GPIO. 0xA1) 0x17 21 M16 DI0_MSS_GPIO1 MSS multipurpose pin: SPI 0 7 Data Input or GPIO Bit 17. Configured as GPIO. 0x18 22 M15 CK0_MSS_GPIO MSS multipurpose pin: SPI 0 18 Clock or GPIO Bit 18. Configured as GPIO. 0x19 20 M13 SS0_MSS_GPIO MSS multipurpose pin: SPI 0 19 Slave Select or GPIO Bit 16. Configured as GPIO. 0x20 29 K16 TX0_MSS_GPIO MSS multipurpose pin: UART 20 0 Transmit Out or GPIO Bit 20. Configured as GPIO. 0x21 30 K12 RX0_MSS_GPIO MSS multipurpose pin: UART 21 0 Receive In or GPIO Bit 21. Configured as GPIO. 0x22 33 J13 SD0_MSS_GPIO MSS multipurpose pin: I2C 0 22 Serial Data I/O or GPIO Bit 22. Configured as GPIO. 0x23 34 J12 SC0_MSS_GPIO MSS multipurpose pin: I2C 0 23 Serial Clock or GPIO Bit 23. Configured as GPIO. 0x24 40 L12 MSS_GPIO24_L MSS multipurpose pin: EDn Connects to LED and GPIO Bit 24. Configured as GPIO. A logic "0" turns on the LED. 0x25 36 L15 MSS_GPIO25 MSS multipurpose pin: GPIO Bit 25. 0x26 37 L14 MSS_GPIO26 MSS multipurpose pin: GPIO Bit 26. 0x27 35 L13 MSS_GPIO27 MSS multipurpose pin: GPIO Bit 27. 0x28 28 K14 TX1_MSS_GPIO MSS multipurpose pin: UART 28 1 Transmit Out or GPIO Bit 28. Configured as GPIO. 0x29 27 K15 RX1_MSS_GPIO MSS multipurpose pin: UART 29 1 Receive In or GPIO Bit 29. Configured as GPIO. 0x30 31 J16 SD1_MSS_GPIO MSS multipurpose pin: I2C 1 30 Serial Data I/O or GPIO Bit 30. Configured as GPIO. 0x31 32 J14 SC1_MSS_GPIO MSS multipurpose pin: I2C 1 31 Serial Clock or GPIO Bit 31. Configured as GPIO.

Rev. 1.0 (December 2012) 18 © DLP Design, Inc. FPGA 0x01 7 R6 ADC1 ADC Direct Input 1 configured (0x30, as LVTTL Input. 0x40, 0x02 11 P7 ADC2 ADC Direct Input 2 configured 0x41) as LVTTL Input. 0x03 6 M5 ADC3 ADC Direct Input 3 configured as LVTTL Input. 0x05 13 N9 ADC5 ADC Direct Input 5 configured as LVTTL Input. 0x06 10 P9 ADC6 ADC Direct Input 6 configured as LVTTL Input. 0x07 9 R9 ADC7 ADC Direct Input 7 configured as LVTTL Input. 0X16 46 M1 TXD0_FPGA_M1 MSS multipurpose pin: MAC RMII Transmit Data Out Bit 0 or FPGA I/O. Configured as FPGA Digital Output 16. 0x17 47 M2 TXD1_FPGA_M2 MSS multipurpose pin: MAC RMII Transmit Data Out Bit 1 or FPGA I/O. Configured as FPGA Digital Output 17. 0x18 49 M3 RXD0_FPGA_M3 MSS multipurpose pin: MAC RMII Receive Data In Bit 0 or FPGA I/O. Configured as FPGA Digital Output 18. 0x19 48 N1 RXD1_FPGA_N1 MSS multipurpose pin: MAC RMII Receive Data In Bit 1 or FPGA I/O. Configured as FPGA Digital Output 19. 0x20 45 L2 TXEN_FPGA_L2 MSS multipurpose pin: MAC RMII Transmit Enable or FPGA I/O. Configured as FPGA Digital Output 20. 0x21 42 L3 CSDV_FPGA_L3 MSS multipurpose pin: MAC RMII Carrier Sense/Receive Data Valid or FPGA I/O. Configured as FPGA Digital Input 21. 0x22 50 L4 RERR_FPGA_L4 MSS multipurpose pin: MAC RMII Receive Error or FPGA I/O. Configured as FPGA Digital Output 22. 0x23 43 K1 MDIO_FPGA_K1 MSS multipurpose pin: MAC RMII Management Data I/O or FPGA I/O. Configured as FPGA Digital Input 23. 0x24 44 K2 MDC_FPGA_K2 MSS multipurpose pin: MAC RMII Management Data Clock or FPGA I/O. Configured as FPGA Digital Output 24. 0x68 41 M3 FPGA_E3 FPGA I/O: Configured as FPGA Digital Output 68.

Rev. 1.0 (December 2012) 19 © DLP Design, Inc. If there is a problem with the command sent, the DLP-2232H-SF module’s program will return an error code to the host. The error codes always start with a hexadecimal "E". The error codes are explained in the following table:

TABLE 8 Error Code Return Values Explained Error Source Code Description Comments Hex Value (Hex) 0xE0 Invalid Register FPGA A valid version/status register read command (0x10) was Fabric received, but the requested register is out of range (0-5).

0xE1 Invalid FPGA An invalid command byte was sent from the host PC. Command Fabric 0xE2 Invalid Clear FPGA A valid pin clear command (0x40) was received, but the Pin Number Fabric pin specified does not match a valid pin number (see Table 1).

0xE3 Invalid Set Pin FPGA A valid pin set command (0x41) was received, but the pin Number Fabric specified does not match a valid pin number (see Table 1).

0xE4 Invalid Read FPGA A valid pin read command (0x5x) was received, but the Pin Number Fabric pin specified does not match a valid pin number (see Table 1).

0xE5 Invalid 8-Bit FPGA An 8-bit shared memory access was requested by the Shared Memory Fabric ARM MSS that specified an invalid location. Access 0xE6 Invalid 16-bit FPGA A 16-bit shared memory access was requested by the Shared Memory Fabric ARM MSS that specified an invalid location. Access 0xE7 Invalid 32-bit FPGA A 32-bit shared memory access was requested by the Shared Memory Fabric ARM MSS that specified an invalid location. Access 0xE8 ARM MSS FPGA The ARM MSS Core did not respond to the host Timeout Fabric command provided by the FPGA fabric within the 2-second limit.

0xE9 Invalid ARM ARM MSS An invalid ARM command value was specified. Command

Users can either design their own host application interface to send USB commands to the DLP-2232H-SF module or utilize the test application tool available from DLP Design. The DLP Test Application is available in a free version for download from the DLP Design website at www.dlpdesign.com/test.shtml. Using this tool, single- and multi-byte commands can be sent to the DLP-2232H-SF board.

Once installed, the test application is used as follows:

The commands used to interface to the DLP-2232H-SF are detailed in Section 11 of this datasheet.

14.0 SCHEMATICS

Schematics for the DLP-2232H-SF are included on the last three pages.

15.0 DISCLAIMER

Neither the whole nor any part of the information contained herein nor the product described in this manual may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder.

Rev. 1.0 (December 2012) 22 © DLP Design, Inc. This product and its documentation are supplied on an as-is basis, and no warranty as to their suitability for any particular purpose is either made or implied. DLP Design, Inc. will not accept any claim for damages whatsoever arising as a result of the use or failure of this product. Your statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury.

This document provides preliminary information that may be subject to change without notice.

16.0 CONTACT INFORMATION

DLP Design, Inc. 1605 Roma Lane Allen, TX 75013

Phone: 469-964-8027 Fax: 415-901-4859 Email Sales: [email protected] Email Support: [email protected] Website URL: http://www.dlpdesign.com

U2 5V0 MCP1726-3302E/MF P3V3 FB2 FB3 MI0805K601R MI0805K601R 1 VIN VOUT 8 2 7 P3V3 P3V3 P3V3 C8 VIN VOUT R21 1 2 VPHY 1 2 VPLL 1.0uF/0603 3 5 100K 10uF/10V D SHDN PWRGD C39 C10 C33 C25 C26 C9 DLP-2232H-SF D 4 6 GND CDELAY 4.7uF .1uF 4.7uF .1uF .1uF DNS v1.1 1000 mA 1000pF C78 POWER-UP DELAY CAP C78 200uS (No cap) to 300mS (0.1uF) Page 1

VPLL P3V3 VPHY P1V8

C2 C4 C6 C77 C46 C47 C48 C49 C14 U1 .1uF .1uF 4.7uF .1uF FT2232HQ .1uF .1uF .1uF .1uF .1uF 4 9 12 37 64 20 31 42 56 DLP-2232H-SF MODULE IO (top view) 5V0 J1 DC:+3.6 to +6.0V D1 VPLL

P3V3 VPHY CONN PCB 25x2 VCCIO VCCIO VCCIO VCCIO

P5V0 VCORE VCORE VCORE 1 50 ABPS0_ADC0_SCB0 1 50 RERR_FPGA_L4 CN2 VREGIN 1 C 3 ABPS4_ADC1_SCB2 2 50 49 RXD0_FPGA_M3 C MBR130T1G R25 2 2 49 16 FTDI_D0 3 49 48 RXD1_FPGA_N1 RMII 1K VREGOUT ADBUS0/TXD/D0/TCK SK 3 17 FTDI_D1 DAC0 4 48 47 TXD1_FPGA_M2 DC BARREL JACK ADBUS1/RXD/D1/TDI DO 4 ETHERNET 18 FTDI_D2 DAC1 5 47 46 TXD0_FPGA_M1 FB1 ADBUS2/RTS#/D2/TDO DI 5 OR FPGA 14 19 FTDI_D3 ADC3 6 46 45 TXEN_FPGA_L2 HZ0805E601R RESET# ADBUS3/CTS#/D3/TMS CS 6 6 REF ADBUS4/DTR#/D4/GPIOL0 21 FTDI_D4 ADC1 7 7 45 44 MDC_FPGA_K2 FABRIC 22 8 44 43 ADBUS5/DSR#/D5/GPIOL1 FTDI_D5 ADC0 8 MDIO_FPGA_K1 IO 5VIN 1 2 23 FTDI_D6 ANALOG ADC7 9 43 42 CSDV_FPGA_L3 R2 ADBUS6/DCD#/D6/GPIOL2 9 24 FTDI_D7 ADC6 10 42 41 FPGA_E3 C1 C34 C3 12K ADBUS7/RI#/D7/GPIOL3 10 FPGA IO PORTVCC ADC2 11 41 40 MSS_GPIO24_LEDn .01 10/10 Tant 11 40 MSS GPIO ACBUS0/TXDEN/RXF#/GPIOH0 26 FTDI_RXF ADC4 12 39 CN1 .1uF 12 39 ACBUS1/WRSTB#/TXE#/GPIOH1 27 FTDI_TXE ADC5 13 38 MSS_RSTn CN-USB R16 27 13 38 ACBUS2/RDSTB#/RD#/GPIOH2 28 FTDI_RD CM1_ADC0_SCB1 14 37 MSS_GPIO26 1 29 R17 27 15 14 37 36 ACBUS3/TXLED#/WR#/GPIOH3 FTDI_WR TM1_ADC0_SCB1 15 MSS_GPIO25 MSS GPIO 2 7 30 FTDI_SI CM3_ADC1_SCB3 16 36 35 MSS_GPIO27 DM ACBUS4/RXLED#/SIWUA/GPIOH4 R23 27 16 3 8 32 FTDI_CLKOUT TM3_ADC1_SCB3 17 35 34 SC0_MSS_GPIO23 DP ACBUS5/-/CLKOUT/GPIOH5 17 34 4 33 FTDI_OE 18 33 SD0_MSS_GPIO22 I2C 0 P3V3 ACBUS6/-/OE#/GPIOH6 18 33 34 DO0_MSS_GPIO16 19 32 SC1_MSS_GPIO31 R3 R6 ACBUS7/-/-/GPIOH7 19 32 SSO_MSS_GPIO19 20 31 SD1_MSS_GPIO30 I2C 1 10K 10K 20 31 BDBUS0/TXD/DO/TCK SK 38 JTAG_CLK SPI 0 DIO_MSS_GPIO17 21 30 RX0_MSS_GPIO21 5 21 30 BDBUS1/RXD/D1/TDI DO 39 JTAG_DIN CK0_MSS_GPIO18 22 29 TX0_MSS_GPIO20 UART 0 22 29 BDBUS2/RTS#/D2/TDO DI 40 JTAG_DOUT 5VIN 23 28 TX1_MSS_GPIO28 R19 23 28 63 BDBUS3/CTS#/D3/TMS CS 41 JTAG_TMS PORTVCC 24 27 RX1_MSS_GPIO29 UART 1 0 62 EECS 43 25 24 27 26 EECLK BDBUS4/DTR#/D4/GPIOL0 JTAG_TRSTn B 61 44 25 26 B EEDATA BDBUS5/DSR#/D5/GPIOL1 BDBUS6/DCD#/D6/GPIOL3 45 46 DNS Y1 BDBUS7/RI#/D7/GPIOL4 R30 0 12MHz 48 MSS_RSTn NOTE: UART, I2C, AND SPI PORTS CAN ALSO BE MSS GPIO BCBUS0/TXDEN/RXF#/GPIOH0 R13 2 OSCI BCBUS1/WRSTB#/TXE#/GPIOH1 52 53 P3V3 C11 BCBUS2/RDSTB#/RD#/GPIOH2 BCBUS3/TXLED#/WR#/GPIOH3 54 U3 27pF 55 RED D2 150 EECS BCBUS4/RXLED#/SIWUB/GPIOH4 8 VCC CS 1 3 OSCO BCBUS5/-/-/GPIOH5 57 7 2 EESK 58 DOWNLOAD NC SK EEDATA C12 BCBUS6/-/-/GPIOH6 R27 6 NC/ORG DIN 3 BCBUS7/PWRSAV#/PWRSAV#/GPIOH7 59 5 4 27pF 24.9K GND DOUT R4 60 PWREN# 93LC46 13 PWREN# 36 TEST SUSPEND# R24 2.2K R22 0 5V0 2.2K PORTVCC 5VIN AGND GND GND GND GND GND GND GND GND R7 10K DNS

C5 10 1 5 11 15 25 35 47 51 P3V3 Q2 .1uF 10K 5% R28 IRLML6402 3 1 VCCSW A A Q4 1 2 C17 C18 C19 MMBT3904L 0.1uF 0.1uF 10/10 Tant 2 3

5 4 3 2 1 5 4 3 2 1

1.5V REGULATOR U5F 1V5 1V5 1.5A Maximum DNS R18 0 A1 1V5_INT D GND C23 U4 L1 Q3 D A9 GND A5 F8 VCCSW 4.7uF ST1S06PU1ZR 3.3uH IRLML6401 A12 VCC F10 C62 C63 C65 C66 C67 C68 C15 0603 4 3 R11 0 GND VIN_SW SW A16 VCC G7 2.2 uF 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.1uF 5 GND VIN_A B2 VCC G9 0603 6 C20 C42 GND INHIBIT B15 VCC H8 2 1 0.1uF 0.1uF GND GND FB C7 VCC H10 0603 0603 GND C13 VCC J7 R29 GND D3 VCC J9 GND E6 VCC K8 GND E8 VCC K10 100 5% GND E10 VCC L7 R14 C22 GND F2 VCC L9 FB4 R15 24.9K 1% 22 uF R12 2.5 mS ramp up GND F7 VCC F16 MI0805K601R 1V5 28.7K 1% TANT F9 GND VCCENVM 220K 5% F11 GND N3 1 2 F15 GND VCC15A P8 G6 GND R8 C27 C29 C31 G8 GND VCC15ADC0 0.1uF 0.01uF 22 uF G10 GND VCC15ADC1 VCCSW VCCSW H1 GND H7 GND FB5 H9 GND R16 MI0805K601R GND C H11 N4 C H16 GND VCC33APVCC33A P2 1 2 J6 GND VCC33SDD0 N14 R8 GND C44 C43 C24 C59 C64 C71 C61 1K J8 R7 U5E J10 GND VCC33SDD1 N8 0.1uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 22 uF GND VCC33ADC0VCC33ADC1 VCCSW K7 T15 JTAG_DIN H14 TDI TDO H13 JTAG_DOUT K9 GND P12 JTAG_TRST G13 TRSTB GND VCCMAINXTAL K11 VCCLPXTAL JTAG_TMS G14 TMS GND K13 JTAG_TCK G15 TCK L1 GND H12 R20 L6 GND VJTAG G12 H15 VCCSW JTAGSEL DNS J2 L8 GND VPP C32 C70

J3 0 L10 GND R1 2.2uF 0.1uF C69 R10 R9 L16 GND JTAG_TCK 1 2 M4 GND 2.2 uF 1K 1K A2F200M3F-1FGG256 3 4 PCAP 0603 JTAG_DOUT N15 GND T1 JTAG_TMS 5 6 GND 1 7 8 JTAG_TRST B16 T6 VAREF0_IN JTAG_DIN 9 10 GNDQ NCAP R5 D4 VAREF0 T9 VAREF1_IN JTAG Select GNDQ 1K D12 N12 VAREF_OUT E5 GNDQ VAREFOUTVAREF1 0 = Debug Cortex-M3 J5 GNDQ HEADER 5X2 F13 GNDQ C50 C37 C40 1 = Program SF M6 10 uF 10 uF 10 uF B N7 GND15ADC0 VCCSW B T7 GND33ADC0GNDQ L2 33nH J4 T8 GND33ADC0 K5 M7 VCCRCOSC C7 0.1uF M8 GND15ADC1GND33ADC1 VAREF_OUT 1 GND33ADC1 J4 VAREF1_IN 2 P13 GNDRCOSC 3 ETHERNET RMII CLOCK 1V5 T14 VAREF_OUT 4 GNDLPXTAL L3 VCCSW Y2 VAREF0_IN 5 G16 GNDMAINXTAL 33nH 6 R1 GNDENVM C2 1 3 EN OUT MAC_CLK T4 VCCPLL C54 M10 0.1uF C55 C76 4 27 VDD D2 22 uF HEADER 6 0.1uF 2 GNDTM0GNDTM1 GND P4 VCOMPLA P11 GNDA J5 FXO-HC735-50MHZ N11 GNDA P5 GNDAQ P14 1 VDDBAT 2 Ext Battery T13 GNDAQ

P1 P3 GNDVAREF A N13 C72 A GNDSDD0 VCC33N 2.2 uF GNDSDD1 A2F200M3F-1FGG256 DLP-2232H-SF V1.1 Page 2

5 4 3 2 1 5 4 3 2 1

VCCSW

C51 U5A 2.2 uF C52 C53 U6 CY7C1041DV33 0603 0.1uF 0.1uF B14 B9 E1 D6 EMC_AB[25]/IO16PDB0V0 EMC_AB[12]/IO10NDB0V0 SRAM_A12 A14 C9 D EMC_AB[24]/IO16NDB0V0 EMC_AB[11]/IO09PDB0V0 SRAM_A11 D D11 D9 A3 EMC_AB[23]/IO15PDB0V0 EMC_AB[10]/IO09NDB0V0 SRAM_A10 SRAM_A1 A0 VDD VDD D10 B8 A4 B1 SRAM_A22_RFU EMC_AB[22]/IO15NDB0V0 EMC_AB[9]/IO08PDB0V0 SRAM_A9 SRAM_A2 A1 I/O0 SRAM_D0 B13 C8 A5 C1 SRAM_A21_RFU EMC_AB[21]/IO14PDB0V0 EMC_AB[8]/IO08NDB0V0 SRAM_A8 SRAM_A3 A2 I/O1 SRAM_D1 A13 D8 B3 C2 SRAM_A20_RFU EMC_AB[20]/IO14NDB0V0 EMC_AB[7]/IO07PDB0V0 SRAM_A7 SRAM_A4 A3 I/O2 SRAM_D2 C12 D7 B4 D2 SRAM_A19_RFU EMC_AB[19]/IO13PDB0V0 EMC_AB[6]/IO07NDB0V0 SRAM_A6 SRAM_A5 A4 I/O3 SRAM_D3 SRAM_A18 B12 EMC_AB[18]/IO13NDB0V0 EMC_AB[5]/IO06PDB0V0 A7 SRAM_A5 SRAM_A6 C3 I/O4 E2 SRAM_D4 C11 B7 C4 A5 F2 SRAM_A17 EMC_AB[17]/IO12PDB0V0 EMC_AB[4]/IO06NDB0V0 SRAM_A4 SRAM_A7 A6 I/O5 SRAM_D5 SRAM_A16 B11 EMC_AB[16]/IO12NDB0V0 EMC_AB[3]/IO05PDB0V0 A6 SRAM_A3 SRAM_A8 D4 I/O6 F1 SRAM_D6 A11 B6 H2 A7 G1 SRAM_A15 EMC_AB[15]/IO11PDB0V0 EMC_AB[2]/IO05NDB0V0 SRAM_A2 SRAM_A9 I/O7 SRAM_D7 A10 A4 H3 A8 B6 SRAM_A14 EMC_AB[14]/IO11NDB0V0 EMC_AB[1]/IO04PDB0V0 SRAM_A1 SRAM_A10 A9 I/O8 SRAM_D8 SRAM_A13 B10 EMC_AB[13]/IO10PDB0V0 EMC_AB[0]/IO04NDB0V0 A3 1 TP1 SRAM_A0 SRAM_A11 H4 A10 I/O9 C6 SRAM_D9 H5 C5 SRAM_A12 A11 I/O10 SRAM_D10 D5 EMC_CLK/GAA0/IO00NDB0V0 SRAM_A13 G3 A12 I/O11 D5 SRAM_D11 D6 G4 E5 SRAM_WEn EMC_RW_N/GAA1/IO00PDB0V0 SRAM_A14 A13 I/O12 SRAM_D12 VCCSW F3 F5 SRAM_A15 A14 I/O13 SRAM_D13 C5 A2 F4 F6 SRAM_CSn EMC_CS0_N/GAB0/IO01NDB0V0 VCCFPGAIOB0 SRAM_A16 I/O14 SRAM_D14 C6 A8 E4 A15 G6 EMC_CS1_N/GAB1/IO01PDB0V0 VCCFPGAIOB0 SRAM_A17 A16 I/O15 SRAM_D15 A15 D3 VCCFPGAIOB0 SRAM_A18 A17 SRAM_LBn C3 VCCFPGAIOB0 C4 B3 EMC_BYTEN[0]/GAC0/IO02NDB0V0 C10 SRAM_UBn EMC_BYTEN[1]/GAC1/IO02PDB0V0 VCCFPGAIOB0 E7 SRAM_CSn B5 VCCFPGAIOB0 CS SRAM_OEn B4 E9 SRAM_WEn G5 B2 PSRAM_UBn EMC_OEN0_N/IO03NDB0V0 VCCFPGAIOB0 WE BHE B5 E11 SRAM_OEn A2 A1 PSRAM_LBn EMC_OEN1_N/IO03PDB0V0 VCCFPGAIOB0 OE BLE C C VSS DLP-2232H-SF NC NC64M+) on (A21 NC32M+) on (A20 NC16M+) on (A19 NC8M+) on (A18 VSS A6 E3 H6 G2 H1 D1 E6 A2F200M3F-1FGG256 NOTE: DLP-2232H-SF MODULE COMES WITH 4-MBIT (256K X 16) SRAM INSTALLED, BUT IS DESIGNED TO v1.1 SRAM_A22_RFU C57 SUPPORT 8, 16, 32 & 64-MBIT SRAMS SRAM_A21_RFU 2.2 uF C38 C45 C35 C13 C58 SRAM_A20_RFU VCCSW 0603 0.01uF 0.1uF 0.01uF 0.1uF 0.1uF Page 3 SRAM_A19_RFU

C80 1V5_INT 2.2 uF C79 C16 0603 0.01uF 0.1uF VCCSW Q1 MMBT3904L U5B U5C U5D 3

FTDI_D0 C14 SRAM_D15 B1 R9 ADC7 MDIO_FPGA_K1 K1 P16 1 GBA2/IO20PPB1V0 EMC_DB[15]/GAA2/IO71PDB5V0 ADC7 MAC_MDIO/IO49RSB4V0 PTBASE FTDI_D1 D13 SRAM_D14 C1 P9 ADC6 MDC_FPGA_K2 K2 GBB2/IO20NPB1V0 EMC_DB[14]/GAB2/IO71NDB5V0 ADC ADC6 MAC_MDC/IO48RSB4V0 FTDI_D2 C15 GCA2/IO23PDB1V0 SRAM_D13 E1 EMC_DB[13]/GAC2/IO70PDB5V0 N9 ADC5 TXEN_FPGA_L2 L2 MAC_TXEN/IO52RSB4V0 C16 E2 DIRECT ADC5 M9 L3 2 FTDI_D3 IO23NDB1V0 SRAM_D12 EMC_DB[12]/IO70NDB5V0 ADC4 CSDV_FPGA_L3 MAC_CRSDV/IO51RSB4V0 D14 F5 INPUT OR ADC4 M5 L4 C60 FTDI_D4 GCB2/IO24PDB1V0 SRAM_D11 EMC_DB[11]/IO69PPB5V0 ADC3 RERR_FPGA_L4 MAC_RXER/IO50RSB4V0 B D15 E4 FPGA ADC3 P7 L5 P15 2.2uF B FTDI_D5 IO24NDB1V0 SRAM_D10 EMC_DB[10]/IO69NPB5V0 ADC2 MAC_CLK MAC_CLK E14 F1 ADC2 R6 M1 PTEM FTDI_D6 SRAM_D9 EMC_DB[9]/GEC1/IO63PDB5V0 INPUT ADC1 TXD0_FPGA_M1 MAC_TXD[0]/IO56RSB4V0 F14 GCB1/IO27PDB1V0 G1 ADC1 T5 M2 FTDI_D7 SRAM_D8 ADC0 TXD1_FPGA_M2 MAC_TXD[1]/IO55RSB4V0 E12 GCB0/1027NDB1V0 G2 EMC_DB[8]/GEC0/IO63NDB5V0 ADC0 M3 R12 C83 27pF FTDI_RXF GCA1/IO28PDB1V0 SRAM_D7 EMC_DB[7]/GEB1/IO62PDB5V0 RXD0_FPGA_M3 MAC_RXD[0]/IO54RSB4V0 MAINXIN DNS FTDI_CLKOUT F12 D16 SRAM_D6 G3 P10 RXD1_FPGA_N1 N1 GCA0/IO28NDB1V0 VCCFPGAIOB1 EMC_DB[6]/GEB0/IO62NDB5V0 TM3 MAC_RXD[1]/IO53RSB4V0 Y2 FTDI_TXE E15 E13 SRAM_D5 H2 M11 TM3_ADC1_SCB3 DNS GDC1/IO29PDB1V0 VCCFPGAIOB1 EMC_DB[5]/GEA1/IO61PPB5V0 CURRENT TM2 20 MHz FTDI_RD E16 G11 SRAM_D4 J1 N6 TM1_ADC0_SCB1 GDC0/IO29NDB1V0 VCCFPGAIOB1 EMC_DB[4]/GEA0/IO61NPB5V0 MONITOR / TM1 SRAM_D3 J2 R4 R10 R13 J3 EMC_DB[3]/GEC2/IO60PDB5V0 COMPARATOR TM0 T10 ABPS7 MAINXOUT C84 27pF SRAM_D2 EMC_DB[2]/IO60NDB5V0 ABPS6 ACTIVE SC0_MSS_GPIO23 J12 M13 SS0_MSS_GPIO19 SRAM_D1 H4 INPUT N10 CM3_ADC1_SCB3 T11 DNS I2C_O_SCL/GPIO_23 SPI_0_SS/GPIO_19 EMC_DB[1]/GEB2/IO59PDB5V0 CM3 ABPS5 BIPOLAR SD0_MSS_GPIO22 J13 M15 CK0_MSS_GPIO18 SRAM_D0 H5 M12 ABPS4_ADC1_SCB2 R11 I2C_O_SDA/GPIO_22 EMC_DB[0]/GEA2/IO59NDB5V0 CM2 ABPS4 PRESCALER C82 27pF SPI_0_CLK/GPIO_18 M16 DI0_MSS_GPIO17 P6 CM1_ADC0_SCB1 N5 R14 CM1 ABPS3 INPUTS LPXIN DNS SC1_MSS_GPIO31 J14 SPI_0_DI/GPIO_17 N16 DO0_MSS_GPIO16 FPGA_E3 E3 T3 R5 I2C_1_SCL/GPIO_31 SPI_0_DO/GPIO_16 GFA2/IO68PDB5V0 CM0 ABPS2 Y3 SD1_MSS_GPIO30 J16 FTDI_OE F3 T2 DNS I2C_1_SDA/GPIO_30 GFB2/IO68NDB5V0 VCCSW ABPS1 32.768 KHz L13 MSS_GPIO27 FTDI_SI G4 ABPS0_ADC0_SCB0 R3 SPI_1_SS/GPIO_27 GFC2/IO67PDB5V0 ABPS0 RX0_MSS_GPIO21 K12 L14 MSS_GPIO26 FTDI_WR G5 D1 R15 UART_0_RXD/GPIO_21 IO67NDB5V0 VCCFPGAIOB5 LPXOUT C81 27pF TX0_MSS_GPIO20 K16 SPI_1_CLK/GPIO_26 L15 MSS_GPIO25 F4 UART_0_TXD/GPIO_20 VCCFPGAIOB5 SPI_1_DI/GPIO_25 L12 MSS_GPIO24_LEDn F6 DAC1 T12 DAC OUTPUTS DNS SPI_1_DO/GPIO_24 VCCSW VCCFPGAIOB5 SDD1 VCCSW RX1_MSS_GPIO29 K15 H3 DAC0 R2 K14 UART_1_RXD/GPIO_29 J11 VCCFPGAIOB5 H6 SDD0 K3 TX1_MSS_GPIO28 VCCMSSIOB4 UART_1_TXD/GPIO_28 VCCMSSIOB2 J15 R26 VCCFPGAIOB5 K6 VCCMSSIOB4 VCCMSSIOB2 L11 T16 N2 K4 VCCMSSIOB2 M14 330 PU_N VCCMSSIOB4 MSS_RSTn VCCMSSIOB2 MSS_RESET_N A2F200M3F-1FGG256 A VCCSW A2F200M3F-1FGG256 A D3 A2F200M3F-1FGG256 HEARTBEATGREEN C73 C21 C41 C56 2.2 uF C28 C30 C74 C75 C36 0.1uF 0.01uF 0.1uF 0603 0.01uF 0.1uF 0.1uF 0.01uF 0.1uF

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