TIMA Laboratory

ANNUAL REPORT 2014

May 2015

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46, Avenue Félix Viallet 38031 Grenoble Cedex France Tel. :+33 4 76 57 45 86 Fax :+33 4 76 57 49 81 http://tima.imag.fr

Foreword

TIMA is a public research laboratory sponsored by Synthesis (SLS), Verification and modeling of Centre National de la Recherche Scientifique (CNRS), Digital Systems (VDS). Grenoble Institute of Technology (Grenoble INP) and Université Joseph Fourier (UJF). TIMA addresses Theme 4: Reliable Mixed-signal / RF circuits and some of the most urgent and ambitious challenges systems (RMS). CAD tools, design-for-test, testing related to the design of tomorrow’s circuits and techniques for mixed-signal, RF, microsystem devices. systems on a chip. The research topics of TIMA cover the specification, design, verification, test, CAD tools The 2014 edition of TIMA annual report presents a and design methods for integrated systems, from brief and synthetic presentation of each research analog and digital components on one end of the theme, followed by a scientific summary of its main spectrum, to multiprocessor Systems-on-Chip projects; each project is well identified with the together with their basic operating system on the other relevant key-words, investigators, cooperation and end. contracts. For detailed scientific information, the reader is referred to the relevant articles. A complete In 2014, TIMA is structured in four research themes, list of publications, classified by category and by topic, according to the domain of expertise and research is also provided at the end of the document. communities of their members. The projects reported in this document are grouped according to these A large part of the research is financed by research themes. grants and contracts. Some are large cooperative projects with industrial and academic partners, at the Theme 1: Architectures for robust and complex national, European or world level; others are bilateral integrated systems (ARIS). Reconfigurable and industrial collaborations, linked to a CIFRE doctoral massively parallel multi-core architectures; fault co-tutorship. Most contracts run for 3 to 4 years. In tolerant and self-adaptive architectures; evaluation of 2014, 34 contracts were in operation, out of which 12 robustness and qualification; secured architectures; new projects were started. Page 101 gives an architectures for nanotechnologies overview of our contractual activity.

Theme 2: Design of integrated devices, circuits Among the highlights of the year, two publications and systems. Design, fabrication and characterization were distinguished in an international conference: for integrated micro and nano systems; energy Sofiane Lagraa and Frédéric Pétrot for their paper scavenging and power management for autonomous "Scalability Bottlenecks Discovery in MPSoC devices; Bio-MEMS; asynchronous circuits and Platforms Using Data Mining on Simulation Traces" systems (asynchronous IPs, NoCs, GALS, etc…); non- obtained a Best Paper Award at DATE 2014, and uniform sampling and signal processing (algorithms, Libor Rufer who co-authored the paper " Active architectures, circuits); reconfigurable asynchronous Electronic Cancellation of Nonlinearity in a High-Q logic; safe and secured circuit design; smart CMOS Longitudinal-Mode Silicon Resonator by Current vision sensors. This theme is further decomposed into Biasing" got a Best Paper Award at EFTF2014. And two groups: Concurrent Integrated Systems (CIS), one patent was filed by Mickael Colin and Skandar Micro and Nano Systems (MNS) Basrour: "Générateur implantable à poutre piézoélectrique" Theme 3: Design and verification of System-on- Chip architectures. Architectures, CAD and Members of TIMA were active in the Technical verification techniques for MPSOC’s and integrated Program Committee of 16 conferences and workshop, NoCs; modeling, simulation techniques and with a particular involvement in the organization of reconfigurable prototyping platform for system PRIME as General Chair, and VTS as Co-Program validation; specification and implementation of Chair. The details of these contributions to the hardware-dependent software; assertion-based scientific community is listed starting page 109. verification and synthesis; automatic generation of hardware checkers; verification of logic and temporal Finally, TIMA takes an active part in the new properties at the system level; formal methods for organization of the research in the Grenoble Alpes robustness analysis. This theme is further University, being linked to the two poles decomposed into two groups: System Level "Mathematics, Informatics and Communication" TIMA Annual Report 2014 - Foreword 3

(MSTIC) and "Physics, Engineering and Materials" Starting January 2015, a reorganization of Themes 1 (PEM). TIMA is also a member of the Carnot LSI and 3 will take place, resulting in a total number of 5 Institute and a member of Persyval Lab. research teams for TIMA.

Dominique Borrione

Further information may be obtained from : D. BORRIONE, TIMA, 46 avenue Félix Viallet, 38031 GRENOBLE Cedex, FRANCE. Tel : +33 4 76 57 45 86, Fax : +33 4 76 57 49 81, E-mail : [email protected], http://tima.imag.fr

4 TIMA Annual Report 2014 - Foreword

4 TIMA Annual Report 2014 - Foreword

Table of Contents

07 87 Theme 1 / ARIS Group Academic and research member Architectures for complex and Robust Integrated Systems 93

Staff members 29 Theme 2 / CIS Group Design of Integrated devices, circuits and 95 Systems Ph.D. candidates

41 99 Theme 2 : MNS Group Other members of TIMA Micro and Nano Systems 101 51 Contracts Theme 3 : SLS Group : Design Design and Verification of Systems on a 119 Chip architectures International activities

61 113 Theme 3 : VDS Group : Verification Educational tasks Design and Verification of Systems on a Chip architectures 115 67 Publications Theme 4 : RMS Group Reliable Mixed-signal / RF circuits and 125 Systems Social life

TIMA Annual Report 2014 - Table of contents 5

6 TIMA Annual Report 2014 - Table of contents Theme 1 / ARIS Group Architectures for complex and Robust Integrated Systems

Themes

Robust massively parallel single-chip architectures Power management from the OS down to silicon Fault tolerant and self-adaptative architectures 3D NOC Robust Architectures Design in Reliability face to aging, process variation and soft errors Evaluation of robustness and qualification : radiation testings, fault injection Secured architectures Architectures for Nanotechnologies

Expertise

Scientific Hardware/software techniques for the design of fault and malicious attacks resistant components and embedded systems Fields of expertise Test, Security, Self-Repair, Fault-tolerance : Methodologies, Tools and Architectures Know-how Multilevel platforms for fault simulation and robustness automatic insertion at several abstraction levels; 3D integration solutions test platform for radiation faults measurement ; SEE error-rate prediction of circuits and systems Industrial transfer Patent pending with SYNOPSYS HIT hardened cell patent transferred to ESA SEU emulation tool transferred to ST

Research keywords

Fault tolerance, security, multi-core systems robustness, 3D circuits, aging, fault-injection

Contact

Raoul VELAZCO Michael NICOLAIDIS CNRS Research Director - TIMA CNRS Research Director – TIMA (+33) 476 57 46 89 (+33) 476 57 46 96 [email protected] [email protected]

TIMA – Annual Report 2014 (ARIS) 7

8 TIMA – Annual Report 2014 (ARIS) The Cells Framework: Overal Description

Members: Michael Nicolaidis, Lorena Anghel, Mounir Benabdenbi, Nacer-Eddine Zergainoh, Michael Dimopoulos, Fabien Chaix, Yi Gang, Panagiota Papavramidou

Keywords: Ultimate CMOS and post-CMOS technologies, high defect densities, reliability, yield, low-power, massively parallel single-chip tera-device computers,

Cooperation: STmicroelectronics, iRoC, Atmel, EADS

Contracts: TOETS, Optimise, ELESIS, 3DIM3

Ultimate-CMOS and post-CMOS technologies single-chip massively parallel processors avoids promise integrating trillions devices in a single die, massive redundancy by using self-tests (hardware leading to single-chip massively parallel architectures implemented or software implemented to detect comprising thousands interconnected processors, and failures and create routing tables that are used enabling the next computation turn. But the subsequently to avoid failed processing nodes or aggressive technology scaling that paves the way to failed routes. However, such approaches could not the ultimate CMOS nodes has dramatic impact to: cope with the issues affecting ultimate CMOS and process, voltage and temperature (PVT) variations; post CMOS technologies as: sensitivity to electromagnetic interferences (EMI), to - In highly defective technologies, the vast majority of atmospheric radiation (neutrons and protons) and to nodes (processing elements and routers) may include alpha particles; and circuit aging. It also imposes one or another kind of faults (e.g. timing faults stringent power dissipation constraints. The resulting produced by process, voltage and temperature high defect levels, heterogeneous behavior of identical variations, EMI, or aging). Thus, declaring defective circuits, accelerated circuit degradation over time, and the nodes affected by any kind of faults will quickly extreme complexity, affect adversely fabrication yield waste the computational resources of the chip. and/or prevent fabricating reliable chips in ultimate -Achieving high fault coverage for timing faults is very CMOS and post-CMOS technologies. These issues difficult. Thus, many of these faults may escape are becoming the main show-stoppers in the path fabrication test and also periodic self-tests and leading to these technologies. produce run-time errors. The Cells framework addresses the severe issues - Faults occurring during application execution can not related to the design of massively parallel tera-device be covered by self-tests. processors affected by high defect densities, in which In this project we develop a comprehensive approach we severe issues have to be addressed such us: enabling using in efficient and reliable manner all parts - After fabrication, all processing and routing nodes able to perform useful computations. Hence, we call may be affected by some temporary faults such as the chips having such capabilities Terminator - Tera- delay faults, or clock skews. device bio-mimetic nanotechnology robust – Chips1 in - Fabrication faults altering persistently the circuit reference to the android, which, after being smashed, behavior may massively affect one or more regular mobilized his last functioning parts to pursue his blocks (RAMs, FIFOs, buses) in a large fraction of mission. nodes. Such faults may also very frequently occur during product life. - Fabrication faults altering persistently the behavior of irregular blocks (thus difficult to repair) may affect a significant portion of nodes. Such faults may also frequently occur during circuit life (e.g. every few days), and thus during application execution. - New timing faults induced by circuit aging, as well as soft errors (SEUs and transients) may frequently occur during circuit life (and thus during application execution). - Circuit degradation is continuous and requires continuous self-regulation of circuit parameters (clock-frequency, voltage levels, body bias), to maintain operational each processor node. Clearly, no existing solution can cope with such massively defective systems, which invalidate even 1 massive redundancy schemes (e.g. duplication, TMR), Nicolaidis, M., Designing Single-Chip Massively Parallel Tera-Device Processors: Towards the Terminator Chip, as all replicated parts may be defective. Such Keynote–Plenary Session, IEEE VLSI Test Symposium, May schemes also induce high area and power penalties. 1-5, 2011, Dana Point, CA. Some approaches targeting the design of reliable TIMA Annual Report 2014 (ARIS) 9 The Cells framework (On-Chip Self-healing Tera- Device Processors) [1-2] comprises several techniques spanning at all levels of the system: circuit, processor/architectural, array/routing, task- scheduling/allocation. Innovations are introduced at all levels of this framework, including its overall architecture, its particular components, and the way the cooperation of these components is architected to optimize the outcome. Developments concerning some of these components are presented in the next sections.

References [1] M. Nicolaidis, L. Anghel, N. E. Zergainoh, D. Avresky, “Designing Single-Chip Massively Parallel Processors Affected by Extreme Failure Rates”, Proc. Design Automation and Test in Europe Conference (DATE), March 12 – 16, 2012, Dresden, Germany [2] M. Nicolaidis, “Biologically Inspired Robust Tera- Device Processors”, IEEE Design & Test of Computers, Volume 29, No 5, September/October 2012

10 TIMA Annual Report 2014 (ARIS) Circuit-level fault-tolerance in the Cells Framework

Members: Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Michael Dimopoulos, Diarga Fall, Yu Hai

Keywords: PVT variability; aging; timing faults; soft errors; design for reliability, yield, and low-power; double- sampling schemes.

Cooperation: iRoC, Atmel, EADS

Contracts: Optimise, ELESIS

In massively parallel processor chips, a possible (and rather straightforward) approach may consist of exploiting the existence of large numbers of processing nodes to implement fault tolerance based on duplication or triple modular redundancy – TMR. This approach has two major flaws: drastic reduction of processing power, and drastic increase of energy per task. Similarly, software implemented fault-tolerance may drastically impact performance and power. Hence, (b) a breakthrough in fault-tolerant design is required to Figure 1: (a) A detection technique using a improve both reliability and power dissipation. redundant latch and a delayed clock. (b) The same technique extended in the RAZOR Significant gains in hardware and power cost are architecture to also perform error correction. achieved in a scheme (referred as double-sampling) we proposed a decade ago2. It avoids both hardware While the idea introduced in the double-sampling replication and operations replication. Instead, it approach and the related schemes in Figure 1 avoid observes output signals of logic blocks at two different massive redundancy, significant area and power instants, by adding a redundant latch and driving it by penalties are still introduced due to the redundant means of a delayed clock signal (Figure 1a). It was latches. Furthermore it suffers from two drawbacks: later extended in the RAZOR architecture 3 to also § To avoid false alarms and miss-corrections, all correct errors: upon error detection it uses the path delays of the combinational circuits must contents of the redundant latch to replace the contents exceed the delay δ of the delayed clock. This may of the functional flip-flop (Figure 1b). Efficient dynamic induce significant cost. voltage scaling was implemented by reducing supply § Due to the same problem, we have to use voltage to very low levels and using RAZOR to detect moderate values for δ, limiting the duration of and correct the errors induced by this action. detectable faults. Circuit-level error detection for enhanced fault- tolerance and reduced power consumption One goal of Cells is to explore new fault tolerant architectures that are exempt of the above problems. These problems are due to the fact that all the stages of a FF-based design compute at the same time. This leaves short stability time to the combinational circuit outputs that we could exploit for error checking. In flip-

flops, when the master latch is transparent, the slave (a) is on memorization and vice versa. Thus, if we

transform a flip-flop-based design (Figure 2a), into its equivalent latch-based design, by moving the slave 2 M.Nicolaidis, "Time Redundancy Based Soft-Error Tolerant Circuits latches of the FFs to the middle of the combinational to Rescue Very Deep Submicron", in Proc. 17th IEEE VTSApril circuits, (as shown in Figure 2b where Ck and Ckb are 1999. L.Anghel, M.Nicolaidis, "Cost Reduction and Evaluation of a replaced by non-overlapping clocks Φ1 and Φ2), we Temporary Faults Detecting Technique", in Proc. IEEE DATE, obtain a design that can work at the same clock March 2000 (BEST PAPER AWARD). Also, chapter in book “The frequency as the original one. In addition, the master Most Influential Papers of 10 Years DATE”, Springer, 2008. and slave latches operate at different phases. Then,

3 the outputs of any combinational block (inputs of D.Ernst et al, "Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation", IEEE Micro, vol. 24(6), pp. 10-20, 2003. latches), are stable during the period in which its adjacent blocks are in computation. Thus, we can

TIMA Annual Report 2014 (ARIS) 11 compare the outputs of the latches against their inputs outputs. Thus, this version of GRAAL induces to detect timing and transient faults of large duration, drastically lower area and power penalties with respect according to the GRAAL architecture (Figure 3) that to any known error detection scheme As shown in a we have introduced few years ago. paper we published at the 2011 European Test Symposium4, based on the GRAAL implementation over the icyflex1 processor from CSEM, the area, power and performance penalties of GRAAL are only 17%, 8%, and 2.4%. Note that though the preferred error detection scheme in Cells is GRAAL, Cells is also compatible with any other error detection scheme. For flip-flop based designs, two double-sampling architectures were developed: - The one, referred a ADDA architecture [1], allows (a) operating the same design in 3 modes: the first is the mode used in earlier double-sampling schemes; the second allows early failure prediction; the third allows detecting transient faults of large duration, that could be encountered in hostile environments like space. - The other, presented in [2], reduces drastically the area and power penalties of the double- sampling architecture, by removing the redundant sampling element. With this solution, the only cost for implementing double-sampling consists in the

(b) comparison of the flip-flop outputs against their inputs. Figure 2: FF-based design a), and latch-based design (b). References This scheme also detects SEUs as well as all kinds of [1] M. Nicolaidis, “ADDA: Adaptive Double- latch faults (transition faults, retention faults). sampling Architecture for Highly Flexible Robust Thorough analysis shows that GRAAL detects delay Design”, Proc. Design Automation and Test in faults with duration up to 100% of the circuit delays Europe Conference (DATE), March 19 – 22, without imposing short path constraints. Thus, it offers 2013, Grenoble, France. comfortable timing margins that can be employed for [2] M. Nicolaidis, “Double-Sampling Design detecting large delay faults, and at the same time Paradigm - a Compendium of Architectures” reduce power dissipation by using the idea introduced IEEE Transactions on Device and Materials by the University of Illinois (reduce Vdd and detect and Reliability, Vol. 15, No. 1, March 2015 correct induced timing errors). Note that, fault multiplicity is not an issue for GRAAL. Faults of any multiplicity are detected as far as their duration does not exceed this value. GRAAL also tolerates clock skews of up to 25% of the clock period, as an inherent property of latch-based designs. In addition, we show that larger clock skews that are not tolerated are always detected (thus they are recoverable by using instruction replay).

Φ1 Φ2 Φ1

CC 1 L1 CC 2 L2 CC 3 L3

Compare 1 Compare 2 Err 1 Err 2 Figure 3: The GRAAL error detection architecture. Our GRAAL architecture can be implemented in two ways. The one version uses redundant latches, which introduce non-negligible area and power penalties. Recently this first version of our GRAAL architecture was used by others in the so-called Bubble Razor implementation. The second version of GRAAL architecture is much more efficient as it does not use of redundant latches. Only a two-input XOR gate is 4 H. Yu, M. Nicolaidis, et al, “Efficient Fault Dectection Architecture added to each latch to compare its inputs against to its Design of Latch-based Low Power DSP/MCU Processor” 16th IEEE ETS, May 23-27, 2011, Trondheim, Norway 12 TIMA Annual Report 2014 (ARIS) Memory and Interconnect Self-Repair for High Defect Densities in the Cells Framework

Members: Michael Nicolaidis, Lorena Anghel, Mounir Benabdenbi, Panagiota Papavramidou, Vladimir Pasca

Keywords: PVT variability; aging; timing faults; soft errors; memory repair; design for reliability, yield, and low-power.

Cooperation: STMicroelectronics

Contracts: TOETS, 3DIM3

Embedded memories occupy the largest part of SoCs drastically reducing power dissipation for both ECC- and include even larger amounts of transistors. As based repair and non-ECC-based repair. For instance, memories are designed very tightly to the technology for a 10-3 defect density (1 faulty cell for every 1000 limits, they are more prone to failures than other memory cells), a reduction of power penalty from circuits. Thus, they concentrate the large majority of 280% to 8.8% is reported. Thus, our recent fabrication defects and may affect yield adversely. In developments on ECC-based memory repair provide a addition, failure rates are expected to be exacerbated comprehensive framework enabling low cost memory as we approach the ultimate limits of CMOS, and repair for high defect densities. Further developments should further worsen in post-CMOS technologies. in our group propose a BIST architecture enabling the Furthermore, low power requirements, which are cooperation of transparent BIST with ECC based stringent in modern electronic systems, will also be repair. Transparent BIST is an approach we exacerbated as we move towards ultimate CMOS and introduced at 1996, and further developed and used by post-CMOS, requiring aggressive reduction of supply numerous authors and fault-tolerant systems. This voltage. Unfortunately, voltage reduction results in approach transforms memory test algorithms into additional failures, as weak memory cells will not reversible processes, which preserve the information operate correctly at reduced voltage levels. stored in the memory. Transparent BIST is essential in Furthermore, as ultimate CMOS and post-CMOS are the context of Cells in order to preserve application expected to exacerbate PVT variability and circuit context during periodic memory self-tests. The aging, the ratio of weak cells will sharply increase. As fundamental problem for making cooperating a consequence, techniques enabling coping with high transparent BIST with ECC-based repair is that defect densities in memories are required in the Cells transparent BIST uses signature analysis allowing framework. determining if a memory is faulty (go-nogo test), while Memories and interconnection buses have very ECC-memory repair requires more subtle diagnosis regular structure and enable easy repair. Various (i.e. determining if there are memory words containing efficient memory and interconnections Built-In Self- multiple faulty cells). While the signature analysis Repair (BISR) schemes have been proposed in the alone does not allow making such diagnosis, and also past, and several of them are already industrial the error detection and correction circuitry alone can practice. However, for high defect densities, also misdiagnose words containing more than two conventional memory repair schemes will induce faulty cells, the new transparent BIST architecture we excessive area and power penalties. Thus, innovative have developed in the context of Cells resolves this solutions are required able to drastically reduce these problem thanks to a subtle cooperation between the penalties. The ECC-based memory repair scheme, signature analysis and the ECC circuitries. introduced by our group, is the only known scheme Integrating these approaches in the Cells project will able to cope with high defect densities. However, while enable healing tera-device processor chips comprising the ECC-based repair scheme drastically reduces area billions of defective memory cells. For instance, a and power penalties with respect to conventional massively parallel tera-device chip comprising schemes, power penalty is still non-negligible. thousands of embedded memories of a 1 Tera-bit total Furthermore, implementing self-diagnosis for the ECC- capacity and affected by a 10-3 defect density, will repair scheme, further increase area and power comprise 109 faulty memory cells (including definitely penalties. Our recent developments have eliminated faulty cells as well as weak cells failing during these issues. In 2012, a new family of memory test aggressive voltage reduction modes). The Cells algorithms was proposed eliminating diagnosis-related project will be able making such a chip operational, area and penalties at the expense of test length. More and last but not least, this unprecedented goal will be recently [1] an iterative diagnosis architecture is achieved at very low area and power penalties. proposed, trading test length with area cost. In another innovation [2] a hardware architecture is proposed

TIMA Annual Report 2014 (ARIS) 13 Interconnections may also represent an important References reliability challenge, especially for 3D systems where the vertical interconnects (TSVs) may be affected by [1] Papavramidou, M. Nicolaidis, “An Iterative Diagnosis high defect densities. Efficient Built-In Self-Repair Approach for ECC-based Memory Repair”, IEEE VTS, schemes for TSV interconnect, using parallel message April 2013. transmission and serial message transmission, allow [2] P. Papavramidou, M. Nicolaidis, “Reducing Power Dissipation in Memory Repair for High Defect Densities” resolving this issue in cost effective way. IEEE ETS, Mai 2013.

14 TIMA Annual Report 2014 (ARIS) Array-Level Approaches in the Cells Framework

Members: Michael Nicolaidis, Lorena Anghel, Mounir Benabdenbi, Nacer-Eddine Zergainoh, Michael Dimopoulos, Gilles Bizot, Fabien Chaix, Yi Gang.

Keywords: Ultimate CMOS and post-CMOS technologies, high defect densities, reliability, yield, low-power, massively parallel single-chip tera-device computers, array level self-adaptive approaches.

Cooperation: Stmicroelectronics

Contracts: Optimise, 3DIM3

Adaptive fault tolerant routing Variability awareness In complex grids comprising thousands of nodes, In further developments we extended the algorithm to routing algorithms based on routing tables are enable variability aware and power aware task congestion prone and have low adaptability to new scheduling and allocation. Again we use a distributed failures. Hence, we developed distributed algorithms non-deterministic approach to handle computation using local opportunistic decisions (get another path complexity. One of the developed schemes maps when a node/router/link is faulty or congested). Our different groups of tasks into different regions of the simulation results show that they easily scale for grids grid according to the energy dissipated by each group comprising thousands nodes; tolerate multiple faulty and the power-dissipation characteristics of the nodes/routers/links; avoid congestions; and cope with regions. Then, the leader of each region maps task new failures occurring at any time. But, as they are clusters into sub-regions, and the leader of each sub- based on local decisions, they are deadlocks prone. region maps each task to a node, by using similar To cope with we use virtual networks and pertinent power dissipation considerations. The clock frequency rules acting at the local level. required for meeting the deadline of each task and the power/reliability priorities of the task are encapsulated Adaptive fault tolerant task scheduling and in the header of each task. Each node knows its allocation and error recovery frequency/Vdd operating domains for various error At a first step we integrate in a single algorithm our FT occurrence rates (by monitoring its concurrent error routing approach (discussed above) with distributed detection signal). Thus, it can determine its clock FT scheduling and allocation. We also integrate in the frequency and Vdd level to reach the task deadline, same algorithm check-point-free rollback recovery. minimize the energy dissipated, and achieve the target This is done by an approach which: uses an reliability level (in terms of error occurrence rate). hierarchical task organization into parent-children Thus, circuit parameters (clock frequency and Vdd) trees; maintains this hierarchy during execution; and if are continuously regulated to minimize power, a persistent fault occurs in a resource executing a preserve reliability and adapt to circuit degradation child it goes back to the parent to redistribute the induced by aging. workload in fault-free resources. This way we avoid saving the internal states of the grid to external media Our work on array level self-adaptive algorithms was (no check-pointing), which would congest the grid I/Os, presented in numerous articles published in various and we can recover correct operation even after the international conferences during the past few years, occurrence of any multiple fault (by going up in the including: IEEE International Symposium on Network tree until a fault-free parent, which redistributes the Computing and Applications; Design Automation and aborted workload to fault-free resources). Test in Europe Conference; IEEE International Error recovery algorithms based on check-pointing Symposium on Circuits and Systems; IEEE were also implemented. A basic issue is related to the International On-line Testing Symposium. Our current fact that as the state of the system is huge; we have to efforts concern the integration of these algorithms perform check-pointing for partial states of the system (together with the other techniques used in Cells), in a (e.g. states of tasks), while preserving its overall unified framework implemented in the GEM5 simulator coherence. To cope with this issue a check-pointing and the Structural Simulation Toolkit (SST). algorithm for parallel processors maintaining system coherence was developed.

TIMA Annual Report 2014 (ARIS) 15

16 TIMA Annual Report 2014 (ARIS) Design of secured crypto-processors

Key-words: security, cryptographic systems, fault-based attacks, side-channel attacks, countermeasures

Members : P. Maistri, R. Leveugle, S. Pontié, A. Mkhinini

Cooperations: STMicroelectronics, LIRMM, ENSMSE/CEA, Institut Fourier, Faculté des Sciences de Monastir (Tunisia), Univ. Massachusetts (USA)

Contracts: EMAISeCi (ANR), LIESSE (ANR)

Context and goals laser attacks on such circuits and (2) evaluate the The current trend for many products, and in efficiency of the implemented counter-measures. particular for consumer products, is toward an Work is also on-going on several types of new increasing need of security, in the form of counter-measures implemented in our AES IPs. In confidentiality, data integrity, and/or parallel, a new approach has been proposed to authentication. These services rely on secure evaluate the effect of electromagnetic attacks [2] protocols and algorithms, which can be in the context of the EMAISeCi project also implemented in software or hardware according to supported by ANR [3]. the performance requirements, and to the cost A hardware design of AES has been fully constraints. Cryptography is at the heart of those implemented in composite fields. Unlike other systems. solutions in the literature, where the focus is on Many current secure implementations rely on the performance/cost ratio, for the first time the specific hardware blocks to implement the main composite fields are used as a countermeasure cryptographic functions. These functions can be against side channel analysis on AES [4]. The tampered by various attacks, either active (fault- representation field is chosen randomly at runtime based attacks) or passive (side-channel attacks: at each encryption, thus the correlation between computation time analysis, power analysis, the power consumption and the key changes observation of electromagnetic emissions…). So- continuously. Simulation results show that the called hardware attacks target the implementation correct key cannot be found anymore, as it is rather than the algorithm itself and are today a indistinguishable from all the other (wrong) significant threat for security, in addition to hypotheses, as seen in Figure 1. Work is ongoing software- or network-based attacks. in order to reduce the overhead required by the The work done in the team aims at (1) better different representations. characterizing and modelling the effect of attacks, in particular fault-based attacks by various means, and (2) propose innovative countermeasures (i.e., protections) against the different types of attacks. Our countermeasures are mainly implemented at RT-Level, even when targeting low-level characteristics such as power consumption analysis. A lot of work has been focused on the development and validation of robust re-usable cores (IPs) for cryptography. Previous and on- going studies cover symmetric (mainly AES, but also PRESENT for lightweight implementations) and asymmetric (RSA, ECC) cryptosystems. Figure 1. DPA attack on the AES design protected Recent outcomes by dynamic composite field. Part of the recent work has been focused on the development of cores for the widespread AES Work on ECC crypto-processors is on-going, on algorithm, taking into account various constraints both attack and counter-measure sides [5]. We from low- or medium-performance applications to have designed and implemented an improved highly demanding implementations for networking, version of the windowing algorithm, where the and various types of attacks. Several AES crypto- size of each window used during the computation processors have been manufactured by our is randomly chosen at runtime. In order to protect partner STMicroelectronics in 28 nm bulk and also against timing attacks and to hide the size of FDSOI technologies, in the context of the LIESSE the windows, dummy point additions are inserted project supported by ANR [1]. Experiments have randomly in the design. The number of operations started in order to (1) characterize the effect of is chosen in order to perform the same number of

TIMA Annual Report 2014 (ARIS) 17 operations as in the worst case, i.e. choosing References always the smallest possible window. The dummy [1] R. Leveugle, P. Maistri, P. Vanhauwaert, F. Lu, operations can be inserted anytime. G. Di Natale, M.-L. Flottes, B. Rouzeyre, This approach increases the number of ways by A. Papadimitriou, D. Hély, V. Beroulle, G. Hubert, which the scalar coefficient can be partitioned, S. De Castro, J.-M. Dutertre, A. Sarafianos, N. Boher, M. Lisart, J. Damiens, P. Candelier, thus increasing the number of possible ways to C. Tavernier, "Laser-induced fault effects in compute the scalar multiplication. The number of security-dedicated circuits", 22nd IFIP/IEEE possible configurations, as a function of the International Conference on Very Large Scale minimal and maximal window sizes, is shown in Integration (VLSI-SoC), 2014, pp. 201-206 Figure 2. It is interesting to observe that [2] D. Alberto, P. Maistri, R. Leveugle, increasing the larger constraint does not give any "Electromagnetic attacks on embedded devices: a significant advantage over a certain limit, from the model of probe-circuit power coupling", 9th point of view of robustness and performance, International Conference on Design & Technology which is on the other hand largely affected by the of Integrated Systems in Nanoscale Era" (DTIS), 2014, pp. 23-28 lower parameter. [3] P. Maistri, R. Leveugle, L. Bossuet, A. Aubert, V. Fischer, B. Robisson, N. Moro, P. Maurine, J.-M. Dutertre, M. Lisart, "Electromagnetic analysis and fault injection onto secure circuits", 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2014, pp. 195-200 [4] M. Bollo, P. MAISTRI, “Composite Fields against Side Channel Analysis for the Advanced Encryption Standard,” 21st IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 542-545, (2014). [5] S. Pontié, P. Maistri, R. Leveugle, “An Elliptic Curve Crypto-Processor Secured by Randomized Windows”, 17th Euromicro Conference on Digital System Design (DSD), 2014, pp. 535-542.

Figure 2. Number of window partitionings for a 163- bit scalar coefficient, as a function of the minimum and maximum window size.

Figure 3 shows a partial power trace obtained from a random key. Two different patterns can be easily recognized, corresponding to the point addition and doubling. A simple power analysis could be mounted, but the attacker cannot know if an addition is real or dummy. Work is ongoing on ECCs with unified formulas, where point additions and doublings are no longer distinguishable. This is part of the work made in collaboration with Institut Fourier in the context of the Persyval Labex. Hardware implementation of homomorphic encryption is also part of this collaboration, targeting Cloud applications. Collaboration is also on-going on this subject with Faculté des Sciences de Monastir (Tunisia) in the context of a co-advised PhD.

Figure 3. Partial trace of the consumed power on a 256-bit elliptic curve.

18 TIMA Annual Report 2014 (ARIS) Irradiation of advanced integrated circuits performed at the high- energy neutron facility GENEPI-2 (Grenoble)

Members: R. Velazco, W. Mansour, F. Pancher, P. Ramos Key-words: Accelerated radiation tests, high energy neutron, SEE, SEU, MCU, MBU, SER Cooperation: LPSC, ONERA-DESP, UCM (Univ. Complutense de Madrid) Contract: e2v

Context and goals Since neutrons propagate in the whole Ionization resulting from charged particles present experimental room, the DUT test platform in the environment where integrated circuit (hardware platform providing the suitable operate, may result in a wide range of environment to the DUT and the readout consequences gathered under the acronym SEE electronics) also sits in the neutron flux. Therefore (Single Event Effects) and classed as soft and a shield of borated polyethylene was assembled hard errors. Soft errors are the consequences of and used to protect it (see Fig. 2). the modification of memory cell’s contents while hard errors, SEL (Single Event Latchup) may provoke the destruction of the circuit by ground/power-supply short circuits. The soft-error rate (SER) determination is still a challenge to evaluate the technology sensitivity and to extrapolate the trends for future generations of devices. A collaboration between TIMA/ARIS and LPSC (Laboratoire de Physique Subatomique et de Figure 2: DUT facing the neutron source Cosmologie) was started in 2013 aiming at opening the use of a local neutron facility to GENEPI-2 proved to be an efficient irradiation radiation test experiments on advanced ICs. facility to study the neutron impact on integrated GENEPI-2 (GEnérateur de NEutrons Pulsé circuits: relevant statistics on induced SEU can be Intense) is a particle accelerator located at LPSC reached within one hour. Obtained results during (Grenoble, France) dedicated to high energy the tests performed in different kind of circuits neutrons which are produced under the impact of allowed the presentation of the capabilities of a deuteron beam onto a tritium (T) or deuterium GENEPI-2 facility during the 2014th edition of (D) target by fusion reactions (Fig. 1). The beam NSREC (Nuclear and Space Radiation Effects intensity is measured on target continuously and Conference). the 14 MeV neutron production is monitored on line by a silicon detector. Recent Outcomes Three kinds of devices were tested in GENEPI-2: - A low power memory, the advanced LPSRAM, device in which each memory node has an added physical capacitor (stack capacitor) and thus it is supposed to be extremely robust with respect to neutron effects1. - SRAM memories, CYPRESS issued from three successive manufacturing technologies: 130, 90 and 65 nm. - A multiprocessor: the quadri-core Power PC P2041 from e2v. One sample of the Advanced LPSRAM3 was biased at the nominal power supply (3.3 V) and Figure 1: The GENEPI-2 neutron facility written with the checkboard pattern (0x55H). This The device under test (DUT) faces the centre of device, built in 150-nm CMOS technology and the beam line at a distance adjusted to the organized as a 2M×8 bytes (16 Mbit, 20-bit wide desired neutron flux. Typically the DUT is placed to reach a neutron flux of ~3.104 n.s-1.cm-2. Under 1The RENESAS R1LV1616RSA-5SI includes capacitors with two these conditions, the DUT is exposed to a dose of electrodes generated from polysilicon or metal on the upper layer of the ~108 neutrons within one hour. MOS transistors on the silicon substrate to effectively reduce the surface area of the memory cell TIMA Annual Report 2014 (ARIS) 19 addresses) was continuously read during the tested processor. The Serial Port (UART 0) was radiation runs. No protection against latch-up was used to debug the processor and to read the included in the 3.3-V power supply. outputs of any executed program in static and The device was exposed to the 14-MeV neutron dynamic test modes. beam of GENEPI-2 during one hour until reaching A test was performed on the P2041 for 6 hours a total neutron fluency of 1.1×108 n/cm2. Neither targeting the L2 cache. To get a reference, at the bit-flips nor latch-ups were observed. The same time were exposed two Cypress SRAMs calculations showed that the cross section is at (90 nm and 65 nm). The observed areas of these least one or two order of magnitude beneath other memories were reduced to be similar to the similar devices built in standard CMOS P2041observed sensitive area. During these tests technologies. However, the sensitivity to the the neutron fluency was 1x108 neutron/cm2. impact of particles with higher LET (Linear Energy No errors were observed in the L2 cache of the Transfer) such as heavy ions is not guaranteed P2041 during these tests while 39 errors and 8 and its evaluation requires additional tests in other errors were respectively observed for the 90nm facilities. Therefore, the use of these LPSRAM and the 65nm Cypress SRAM. memories remain a potential candidate for critical The obtained results for tested CYPRESS systems devoted to operate in environments memories allow confirming that memory cells in where only neutrons are a challenge, such as SOI are significantly less sensitive to neutron avionics, high-altitude or ground-based systems. effects than those in CMOS. Results obtained on the Power PC P2041 quad- Results obtained for the CYPRESS SRAMs core processor, have shown that no errors were GENEPI-2 was used under the same conditions to detected validating thus the use of error test CYPRESS CMOS SRAM memories, built in correcting/detecting codes (ECC, Error Correcting 65 nm, 90 nm and 130 nm technologies. These Codes) implemented in the L2 cache memory, runs did exhibit huge number of errors of different guaranteeing the required levels of reliability. In kinds: single event upsets, multiple cell upsets the case of L1 cache memory the absence of and multiple bit upsets. The device cross-section errors validates the efficiency of the protection of (expressed in cm2) is defined as the ratio of this memory by means of parity bits. Potentially observed errors over the total particle fluency. destructive errors, such as SEL (Single Event Measured device cross-sections range between Latchups) were not observed, confirming the 10-6 and 2×10-6 cm2 for the 3 tested patterns (all immunity to these events of circuits manufactured 1’s, all 0’s and alternated). These experiments with SOI processes, immunity explained by the provide preliminary evidences concerning absence of parasitic thyristors. enhanced sensitivity of the 65 nm to the effects of A fruitful perspective of this work may be neutrons. The analysis of results clearly shows performing neutron tests and heavy ion tests to that bit interleaving was adopted to deal with get the static cross-section of P2041 different multiple bit upsets (MBU). Indeed, for the 3 tested memory areas and to perform fault-injection memories many multiple cell upsets (MCU) of according to the CEU (Code Emulated Upset) multiplicity 2, 3 and 4 were detected. However, a methodology developed in the past at TIMA, to few MBU were detected both for 65 nm and 90 obtain realistic estimations of the sensitivity to nm memories pointing out the mandatory use of SEU of a real distributed application running under error detecting and correcting codes for high an operating system executed by the cores of the reliability applications. P2041. Results obtained for the P2041 processor References Neutron experiments on the P2041 were realised [1] R. Velazco, W. Mansour, M. Baylac, S. Rey, O. using the P2041RDB-PB development board as a Rosetto, F. Villa, J.A. Clemente, C. Palomar, F. J. test platform. This platform is a motherboard Franco, “Evidence of the robustness of a COTS Soft- organised around a Power PC P2041 with its Error free SRAM to neutron radiation”, IEEE Nuclear peripherals. To program the processor a trial and Space Radiation Effects Conference (NSREC version of CodeWarrior 10.3 from Freescale 2014), Paris (France), 15-18 july 2014. semiconductor was used. The compiled program is stored in an XOR-flash existing on the [2] M. Baylac, S. Rey, O. Rossetto, F. Villa, W. development board. In particular, the CPU JTAG Mansour; R. Velazco, G. Hubert, “Accelerator-based neutron irradiation of integrated circuits at GENEPI-2 (Join Test Action Group) and the CodeWarrior (France)”, IEEE Radiation Effects Data Workshop programmer cable were used to access all the (REDW 2014), held during IEEE Nuclear and Space existing flash devices on the platform as well as Radiation Effects Conference (NSREC 2014), Paris the internal registers and memory caches of the (France), 15-18 july 2014.

20 TIMA Annual Report 2014 (ARIS) Fault Tolerance Capabilities of Multicore Systems

Key-words: Fault Injection, Reliability, Multi-processing, Soft Errors Members: Raoul Velazco, Pablo Ramos, Vanessa Vargas, Nacer-Edinne Zergainoh Cooperations: LPSC, LIG Contracts: e2v

Context and goals cores, the main core performs the fault injection. The new paradigm in computing systems based It randomly selects the core target, the injection on multicore processors affects the traditional instant (in terms of clock cycles), the address criteria in software and hardware technologies. (global array index) and the bit to be altered. The Nowadays, the characteristics of reliability, master core compares the obtained results from dependability, and availability are crucial not only each core and selects the final result based on a for critical applications. majority vote. The complexity of multicore architectures, due to As master core has not access to other core the number of cores, concurrency issues, shared registers, it will perform an indirect fault injection resources and interconnections among cores is a via the set of instructions. This fault-injection potential source of a wide scope of errors. In order method targets processor registers. An to facilitate the handling errors, the manufacturers interruption handler is launched in order to allow have introduced the error reporting architecture by fault-injection. The target registers to be perturbed the machine check error registers to provide by this method are the following: 32 general information of the error sources. purposed register numbered from 0 to 31, and 5 Fault injection in processor-based architectures of the Special Purpose Registers that may cause was a topic largely addressed by scientific critical failures in program execution: community to validate the reliability of critical Save/Restore register SRR0 (that contains the applications. The CEU (Code Emulated Upset) next instruction to execute), Save/Restore register approach, developed at TIMA/ARIS in 2000, SRR1 (that contains the machine state register), based on the assertion of interrupt signals was LR (Link register), CRF (Condition register), and demonstrated by previous researches as being XER (Exception register). very efficient and able to provide error-rate results The multicore processor target was the Quad-core close to those obtained in radiation experiments. P2041 provided by e2v. The P2041 processor is Its application in the past researches to a complex based upon the e500mc core, built on Power processor, the PowerPC4748, allowed validating it Architecture technology. for aeronautics application. Benefiting of the advantages of the multicore In this project, the CEU approach principle was processor platform, for the first fault-injection adapted for the first time to a multicore processor. experiments it was implemented a state-of-the-art The execution of the interrupt handler provokes fault-tolerant architecture: the Triple Modular the selected error (SEU, MBU) in a randomly Redundancy (TMR). The benchmark algorithm chosen target. In the case of multicore- selected for the test was a standard matrix processors, we can benefit of the multiplicity of cores for using one of them as a fault injector multiplication 40x40 sized. while the others run the application. Figure 1 shows an overview of the fault injection campaign in program variables where 50000 Recent outcomes faults were injected. Two test campaigns were performed on a quad- core processor in which a TMR was implemented: a) Fault injection in any variable of a studied application allocated in shared memory. b) Fault injection in processor general purpose registers and some special purpose registers. This method uses a multicore processor in AMP mode without O.S. The synchronization between the cores is guaranteed via the fault-injector core, using a Master-Slave scheme. Other cores act as slaves (targeted) cores and execute in parallel the Figure 1. SEU fault injection in program variables same task. Shared memory is needed for inter- processor communications. Results show that approximately 20% of injected Main core initializes data that is going to be used faults are silent. If one SEU is injected per by other cores. After that, it sends a message execution, TMR method detects the total of errors through an inter-processor interrupt in order to being the error rate 78% and the TMR corrects start the execution of the application in the slave 99.99% of them. cores. While the application is running on slave TIMA Annual Report 2014 (ARIS) 21 There are two errors that cannot be corrected by Due to the low probability of having a fault in TMR because in these cases the fault were processor registers, the TMR could be considered injected in an index variable and the loop as a good alternative for increasing reliability in execution with this value modifies other data in multicore and many-core platforms. Nevertheless, the shared memory that corresponds to another the effectiveness of TMR is an issue to be core. On the other hand, if two SEUs are injected, considered when dealing with applications running the error rate reaches 93% while the error in harsh radiation environment (aerospace, correction factor decreases to 85%. TMR cannot nuclear plants, avionics). provide a right result in the following cases: In on-going work, the fault injection approach will In the second fault-injection campaign, processor be applied to other multi-core and many-core registers were targeted. For this campaign the circuits where the implementation of TMR will be number of injected faults was significant lower due more reasonable. Radiation ground tests will be to the criticality of certain registers such as SRR0 performed to confront experimental results to (program counter), SRR1 (machine state register) those issued from fault injection campaigns. in which faults provoke exceptions. References [1] V. Vargas, P. Ramos, W. Mansour, J-F. Méhaut, R. Velazco, N-E. Zergainoh, “Preliminary results of SEU Fault Injection on Multicore processors in AMP mode”, 20th IEEE International On-Line Testing Symposium (IOLTS 2014), pp. 194-197, Platja d'Aro, (Catalogne, Espagne), 7-9 july 2014. [2] W. Mansour, P. Ramos, R. Ayoubi, R. Velazco, “SEU fault-injection at system level: method, tools and preliminary results, 15th Latin American Test Workshop (LATW), Fortaleza (Brazil), 12-15 march 2014.

Figure 2. SEU consequences in processors’ registers

Results of a second test campaign, where 500 faults were injected, are shown in Figure 2. The error rate is 12,6% and most of faults were corrected by TMR. However, manipulating certain processor registers become critical because it provokes a high rate of timeouts and exceptions. Hence, the performance of the whole system is dramatically affected. Nevertheless, the occurrence of a fault in a processor registers have a low probability since its physical area corresponds to 0.6% of the area occupied by program variables and data. The most critical register is SRR0. This register saves the context of the program before the interruption subroutine. 59% of injected faults in the SRR0 register lead to a timeout and 26% produce exceptions. This can be explained as the program counter contains the next instruction to be executed after the interruption, and perturbing its content will cause a loss of sequence. Another critical register is SRR1. It stores the content of the machine state register when an interruption occurs. A fault injected in this register may produce a timeout when processor state is performing an address translation for instruction and data memory access. On the other hand, the experiment proves that SEU injected in special registers LC, CRF and XER have no incidence in the program execution. As expected the TMR showed a high efficiency for faults injected in variables located in shared memory, while it is dramatically reduced when the faults is injected in particular processor registers. 22 TIMA Annual Report 2014 (ARIS) Method and tools to emulate soft errors in HDL-based designs

Key-words: single event transients, fault injection, hardware description language, soft-errors Members: R. Velazco, W. Mansour Cooperations: Floralis Contracts: Carnot LSI

Context and goals NETFI allows injecting faults at RT-level (Register The advances in VLSI technology may result in an Transfer Level) in circuits implemented on an FPGA. This increase of their sensitivity to soft-errors due to radiation method allow injecting faults, in a fully automated way, in effects. Characterizing the reliability of these circuits and any block RAM (BRAM), memory cell as well as at the systems with respect to the effects of energetic particles output of any LUT of the studied design. It allows (neutrons, protons, heavy ions, ect.) by means of fault- performing the injection of a fault in one clock cycle, injection methods became an interesting and widely randomly in time and location, emulating thus the effect explored field of study. Fault-injection approaches of SEU /SET and also Stuck-at faults in the DUT. The proposed in literature can be classified in two main idea is to modify the built-in FPGA modules which will be categories: hardware and software methods. Two main used by the netlist after synthesizing the design classes of software based fault-injection are: the described at RT-level, thus allowing fault injection. Fully software-implemented fault-injection (SWIFI) and the automating the steps from synthesis to fault injection is fault injection based on simulation. also a feature of the NETFI fault injection method so that In simulation based fault-injection, faults are injected for any HDL circuit that works properly on the FPGA, using circuits models at hardware description languages fault-injection can be performed with minimum time and (HDL). The main advantage of such approaches with effort. Figure 1 depicts the initial block diagram of the respect to other types of fault injection is the larger NETFI method. observability and controllability of soft-errors sensitive area. Fault-injections performed on FPGAs allow good controllability and observability as well as fast experiments. They also allow the injection of particular types of soft-errors: SET (Single Event Transients) and SEU (Single Events Upsets) faults. Since for most of nowadays complex circuits, such as processors, the HDL code may be available, FPGA-based fault injection methods became largely used for the error-rate estimation of integrated circuits, even before their fabrication exploring thus the efficiency of implemented radhard designs. Figure 1. Block diagram of NETFI In this project was explored the possibility of performing SET fault-injections with a tool, so-called NETFI (NETlist The HDL code of the targeted device will be synthesized Fault Injection) developed at TIMA, which allows using the “Synplify Pro” tool from Synplicity, by executing a TCL script choosing the Virtex-IV XC4VLX40 of the automated fault-injection at the netlist level of a given ASTERICS test platform developed in previous projects device under test (DUT). The idea is to modify the built-in at TIMA for radiation ground tests experiments. This FPGA resources which will be used by the netlist after generated Verilog netlist will be an input to the software synthesizing a design described at RTL level, thus tool, so-called MODNET (MODify NETlist), we developed allowing fault injection. The LUTs (Look-Up Tables) are to automate the modification process of the FPGA built-in transformed to the optimal representable combinational library. Some of the main modified components are the circuit that allows SET fault-injection. To illustrate and FD (D Flip-Flop), and its subcategories (FDC, FDE etc), validate this new approach, NETFI was used to estimate the RAM block (BRAMS, RAM16X1D etc…) the LUTs the SET error-rate of a hardware-implemented Hopfield (Look-Up Table), multiplexers and logic gates. The output Neural Network (HNN) executing a benchmark of MODNET is the modified netlist with a large number of algorithm: Pattern Recognition. The results were extra input signals allowing access to all memory cells compared to those obtained by SET fault-injection on and logic blocks of the design, thus allowing both the the same DUT, using the previous version of NETFI. injection of SEUs and SETs. A memory controller is added to the modified netlist to store the results in the SRAM implemented in the test platform. Synthesizing the

TIMA Annual Report 2014 (ARIS) 23 whole design, generating the programming file and Another study was done aiming at comparing the results downloading it to the FPGA, are the main steps issued from NETFI to those issued from a state-of-the- performed before starting the fault-injection experiment. art tool, the FT-Unshades, developed at University of In the case of small microcontrollers, NETFI method is Sevilla. Fault injection campaigns were performed on easy to apply, but if the targeted design is a complex KECCAK, which is a representative benchmark used in processor, the number of targeted memory cells/blocks cryptographic functions. can reach several tens of thousands. NETFI allows serial Table II shows the results issued from fault injection fault-injection in multi-zones of the design. The time experiment with NETFI during which 38820 faults were required to inject a huge number of faults in the injected. These results were compared to those obtained processor remains unchangeable, since we are injecting with FT-Unshades putting in evidence a slight difference relatively small number of faults in each sensitive zone. in the total error-rate (86.97 % for NETFI vs. 90.84 % for MODNET is also responsible to detect the number of flip- flops in the design, compare them to the capacity of the FT-Unshades) certainly due to the difference in the FPGA, and divide the netlist into ‘n’ sub-netlists. The targeted area for both methods (1756 bits for NETFI vs. number of faults injected will be proportional to the 1683 bits for FT-Unshades). number of sub-netlists. TABLE II: RESULTS OF FAULT-INJECTION EXPERIMENTS ON THE KECCAK Test # runs # Errors # Timeouts #converges Recent outcomes The Virtex IV FPGA of ASTERICS motherboard was KECCAK 38820 33669 95(0.24%) 5056(13,02%) configured to implement a benchmark of a Hopfield (86.73%) Neural Network (HNN) devoted to alphabetical pattern Obtained results confirmed the ability of NETFI to inject recognition, with 32-bits input patterns. The HNN was set faults in more critical logic gates that lead to erroneous to reconstruct a correct pattern among three different results or that cannot be re-corrected by a fault-tolerant noisy patterns. The weights of a pattern recognition circuit such as the HNN. These results can also provide a application were pre-calculated and stored with the better feedback of the sensitivity of any design, especially design in the DUT FPGA of ASTERICS. A memory of fault-tolerant designs intended to be implemented on controller was also implemented to write the results of the an ASIC. recognition process in the SRAM memory of the In future work the upgraded version of the NETFI method ASTERICS platform in order to be read out by a will be used to inject faults in more complex circuits such computer supervisor. as processors. The SET faults will be combined with the Various runs, during which huge numbers of SETs were SEU faults in order to better predict the soft-error rate of injected randomly in time and location, were performed. It a DUT. To get a good comparison between the predicted is important to notice that, in each of these runs only one and the measured error-rates, are planned to be SET per execution was injected in logic gates of the performed radiation test experiments in particle modified HNN. In other words, the output of the randomly accelerators, where the circuit will be exposed to selected logic-gate was perturbed within the execution energetic particle’s beams (heavy ions, protons, time of the studied benchmark and at a randomly chosen neutrons,…). cycle.

In the table below are summarized the results of performed fault injection experiments. References [1] W. Mansour, M. A. Aguirre, H. Guzman-Miranda, J. TABLE I: RESULTS OF FAULT-INJECTION EXPERIMENTS ON THE HNN Barrientos, R. Velazco, “Two complementary approaches for Test # runs # Error # Timeout #converges studying the effects of SEUs on HDL-based designs”, 20th HNN 48396 793(1.64%) 621(1.28%) 2842(5.87%) IEEE International On-Line Testing Symposium (IOLTS 2014), pp. 220-221, Platja de Aro (Catalogne, Espagne), 7-9 juillet A detailed analysis of obtained data allows putting in 2014. evidence that the previous version of the NETFI method can hide some errors or timeouts due to the fact that faults that cannot be injected in probable critical logic- gates.

24 TIMA Annual Report 2014 (ARIS) Hardware/Software dependability analysis from RT-Level descriptions

Key-words: dependability evaluation, fault injection, register criticality, high-level error models

Members : R. Leveugle, M. Ben-Jrad, S. Bergaoui, P. Vanhauwaert, K. Chibani, M. Portolan, P. Maistri, A. Chahed

Cooperations: STMicroelectronics, LCIS, Ecole Nationale d'Ingénieurs de Sousse (ENISo, Tunisia)

Contracts: LIESSE (ANR)

Context and goals LIESSE project supported by ANR. A new Significant effort has been targeted since more injection approach on Virtex 5 platforms is also than fifteen years on developing efficient currently evaluated in collaboration with techniques to analyze, at design time and early in A. Ammari, Assistant Professor at ENISo the design flow, the functional consequences of (Tunisia). The use of such platforms is also soft errors. The goal is to precisely identify the soft discussed with several industrial partners, in two errors leading to unacceptable application different contexts: evaluations with respect to disturbances, in spite of all the possible masking natural disturbances (e.g., particles) and with effects due to the circuit architecture or to the respect to fault-based attacks on secure circuits. application characteristics. Targets are mainly In addition, a significant effort is currently targeted synchronous digital circuits. Most of the proposed towards alternative approaches. In 2014, it was techniques start from synthesizable RTL demonstrated that the dependability of software- descriptions. Such descriptions are already close based applications running on complex to the final hardware in terms of cycle accuracy microprocessors can be accurately evaluated and in terms of memory cells identification. Higher without resorting to fault injections [1]. The level descriptions may in some cases be used, approach is based on an executable model of the with limited representation of soft error locations processor micro-architecture, allowing a software and reduced accuracy in terms of propagation engineer to quickly evaluate the impact of any analysis. Software is also taken into account in software modification on the lifetime of information the case of systems based on microprocessors. actually handled by the processor. Critical Robustness evaluations may aim at (1) classifying registers in the processor can also be identified, the soft errors with respect to their functional taking into account the usage of resources for a impact, in order to compute derating factors on given application. The approach was also used to the application failure probability, (2) identifying confirm previous outcomes on the (mainly error propagation paths, (3) identifying critical negative) impact of the compilation optimizations locations or registers, (4) ensure that a given set on the global application dependability [2]. of behavioural properties always hold for a given Work is also on-going in collaboration with LCIS set of soft errors (e.g., a given maximum laboratory in order to better focus injections in the multiplicity of erroneous bits). So-called fault case of local attacks e.g., with lasers [3]. injection techniques are used in most cases. For Further work is currently targeted on the analysis the latter case, the use of formal approaches was of data lifetimes in digital circuits. The goal is to also studied in collaboration with the VDS group in achieve quick evaluations of the register order to avoid exhaustive fault injections. sensitivity for a given application, without any fault A whole set of techniques has been developed to injection campaigns. cover the wide range of analysis objectives and circuit characteristics. New approaches are References currently studied in order to reduce experimental [1] K. Chibani, M. Ben-Jrad, M. Portolan, times that remain significant with faults injections, R. Leveugle, "Fast accurate evaluation of register even in the case of statistical fault injections on lifetime and criticality in a pipelined emulation platforms. microprocessor", VLSI-SoC 2014 [2] K. Chibani, S. Bergaoui, M. Portolan, R. Leveugle,

"Criticality evaluation of embedded software Recent outcomes running on a pipelined microprocessor and impact The more recent fault injection platforms of compilation options", ICECS 2014 developed in the team are based on emulation [3] A. Papadimitriou*, D. Hély*, V. Beroulle*, and take advantage of the partial reconfiguration P. Maistri, R. Leveugle, "A multiple fault injection capabilities of some FPGAs. Maintaining such methodology based on cone partitioning towards platforms is a permanent work. Improvements RTL modeling of laser attacks", DATE 2014 have been made in 2014 in order to make the * LCIS, France approach freely available as scheduled in the

TIMA Annual Report 2014 (ARIS) 25

26 TIMA – Annual Report 2014 (ARIS) RT-Level design for reliability/safety/availability and/or security

Key-words: dependability improvement, control flow checking, functionality checking

Members : R. Leveugle, S. Bergaoui, P. Vanhauwaert, L. Terras

Cooperations: STMicroelectronics, Dolphin Integration

Contracts: SPICA (FUI)

Context and goals checking not only the main application program, Protecting a design against natural perturbations but also the boot phase and the calls to external or malicious attacks can be done at several levels. functions, for which the source code is not We mostly focus here on approaches that can be available (e.g., pre-compiled library functions). No applied at RT-Level, therefore quite early in the assumption is made on the error multiplicity. The design flow and easy to synthesize on several approach is compatible with the norms requiring a physical targets (several ASIC technologies, complete separation between the nominal FPGAs …). Studies also included operating functions and the checking features (e.g., for systems or software modifications but we mainly automotive applications). Prototypes have been focus on hardware protection techniques. Some developed including (1) a specific watchdog protections aim at improving reliability, safety processor (or infrastructure IP) and (2) and/or availability against natural perturbations development tools. The watchdog program is (radiations, particles, electromagnetic fields) and automatically generated at compile time by a other disturbances caused for example by modified version of the GCC compiler. Additional process, voltage and temperature (PVT) tools have been developed to cope with linkage variations. Some others are dedicated at constraints. A prototype has been demonstrated improving security against malicious attacks, on the Leon3 processor [1]. Overheads are either passive (based on power or smaller than those induced by the classical lock- electromagnetic measures) or active (laser-, step duplication. Another advantage with respect glitch- or electromagnetic-based perturbations). to duplication is to ensure diversity, making For protections dedicated to security, see the successful malicious attacks much more difficult section entitled "Design of secured crypto- to achieve. processors"; these aspects will not be developed in this section. We will focus in this part on Work is on-going to transfer the principles of the approaches used for natural perturbations, but approach on ARM, ST and 80x51 processors, in some of them may also be used in a security collaboration with industrial partners. Since the context. goals are not necessarily always exactly the Recent work mainly includes the development and same, depending on the industrial constraints of validation of cores including new protection each partner, additional checks and new schemes, and the development of tools optimizations are currently studied for each automating the use of these cores in a classical particular requirement. design flow. References Recent outcomes [1] S. Bergaoui, P. Vanhauwaert, R. Leveugle, "IDSM: Due to the increasing spatial multiplicity of error an improved disjoint signature monitoring scheme patterns, protecting a circuit with information for processor behavioral checking", 15th Latin- redundancy is more and more difficult. This is American Test Workshop (LATW), Fortaleza, Brazil, March 12-15, 2014 particularly true when malicious attacks are concerned, but the problem exists also for natural perturbations. Another approach consists in using functional checks. In this context, we had proposed in 2008 the bases of a new control-flow checking technique for microprocessor-based systems. This technique, called IDSM, is non- intrusive and does not require a modification of the initial system. Checks include not only the control flow itself, but also the validity of operations and the integrity of critical data, with several possible trade-offs between overheads and error detection. The approach allows TIMA Annual Report 2014 (ARIS) 27

28 TIMA Annual Report 2014 (ARIS)

Theme 2 / CIS Group Design of Integrated devices, circuits and Systems

Themes

Asynchronous circuits and systems (asynchronous IP’s, NoCs, GALS, etc…) Non-uniform sampling and signal processing (algorithms, architectures, circuits) Reconfigurable asynchronous Logic Safe and secured robust asynchronous circuits Smart CMOS vision sensors

Expertise

Scientific Modeling, simulation, verification, asynchronous digital and analog circuit synthesis Fields of expertise Imagers design, asynchronous design tools, asynchronous systems design Know-how Development of a logic-cells library, cameras for CMOS imagers, asynchronous circuits prototyping and manufacturing Industrial transfer 2007 : Creation of the TIEMPO startup company

Research keywords

Asynchronous circuits and systems, CAD tools, CMOS imagers, non-uniformly sampled digital signal processing

Contact

Laurent FESQUET Grenoble INP, Associate Professor -TIMA (+33) 476 57 48 12 [email protected]

TIMA Annual Report 2014 (CIS) 29

30 TIMA Annual Report 2014 (CIS) Smart CMOS Image Sensors

Key-words: CMOS Imagers, Smart, Light adaptive, High Dynamic Range, Temperature compensation, Smart Readout Procedure

Members : G. Sicard, L. Fesquet, H. Abbas (PhD), A. Chefi (PhD), A. Darwish (PhD), L. Rocha (Master Trainee)

Cooperations: CEA-LETI, e2v, LPNC Lab. (Grenoble), EµE lab. (Tunisia)

Contracts: CICA (Gravit)

Research on smart Image Sensors has started in This pre-processing architecture is distributed 2003 in the CIS Group. The aim of this research is between the pixel and column amplifiers with a to improve current CMOS Imagers in order to: low area penalty for the pixel. This imager § Obtain CMOS imagers with a High Dynamic includes a 256x256 linear pixel, designed in a Range (“PICS” Medea+ project, with ATMEL CMOS 0,35µm. The obtained results are very – e2v Grenoble). promising (Fig. 2) [1]. § Implement adaptive systems that ideally deliver the same image of a scene, whatever the external conditions. § Reduce the huge amount of data at the output of the sensor. All these research works have the same technical constraints: § Minimize the number of transistors in the pixel (up to 15) and the pixel silicon area. § Optimize the image processing chain allocation between pixel, column amplifier and the entire circuit in order to optimize the electronic behaviour and the silicon area. § Preserve, as much as possible, the behaviour of a standard industrial CMOS imager in terms of electronic biasing Figure 2. Experimental results on the same scene with capabilities, timing diagram, etc. identical camera setup and circuit (left the local adaptation is off, right it is on). Information in the dark part of the image is Since 2003, seven imagers have been designed enhanced by the balance block and its analog non-linear and tested in our group. The following chapters Michaelis Menten processing. present the results of our on-going research. 2. Temperature Compensation on CMOS 1. Light Adaptive Systems: CICA project Imagers: the Imagyne 4 project

This is a cooperative project LPNC (Laboratoire CMOS vision sensors, like all electronic systems, de Psycho Neuro Cognition de Grenoble) and it is are very sensitive to temperature variation, which funded by GRAVIT. limits their DC electrical behaviour. Fig. 3 presents the temperature effect on basic CMOS imagers. So far, no elegant integrated solution of this shortcoming exists. In this work, we propose to find smart integrated solutions in order to preserve the DC behaviour of the entire imager. We have explored several solutions: Feedback loop, Zero Temperature Coefficient (ZTC) point and band-

Figure 1. Images processed with Matlab. c) Basic correction gap techniques. Fig. 4 shows simulation results (white balance and gamma correction. d) our method. obtained with our ZTC solution on a standard imager. We reduce the variation of the output With a classical post-processing scheme, low voltage by 98% of the total variation. contrasts are lost due to their bad illumination This work was initially supported by the “Vis- conditions. Our CMOS imager integrates a Imalogic” Minalogic project. The characterization patented bio-inspired light adaptive system in that of two prototypes implementing these techniques improves the image quality: it enhances low has been done in 2012. contrast details in a scene.

TIMA Annual Report 2014 (CIS) 31 20% Redundancy Rate

60% Redundancy Rate

Figure 5. Matlab results of the algorithm application on 2 photos.

Figure 3. Temperature effect on integration mode CMOS 4. Asynchronous Low-power Image Sensors Imagers for low, medium and high values. Todays, the sensor power consumption is becoming more and more crucial, mainly for all the embedded applications including embed cameras. It’s due to the very large number of pixels in current CMOS imagers which implies a high output dataflow. Reading all these pixels implies also high constraints on the ADC stage in term of speed and power consumption. Therefore, we decided to adopt a completely different approach by replacing this analog block. The proposed image sensor performs a data flow reduction using a new sampling technique, where only relevant data are read and processed. Figure 4. Temperature effect on integration mode CMOS Furthermore, the reading architecture Imagers after ZTC compensation method. accomplishes spatial redundancies suppression

during the image sensor read-out. This leads to 3. Smart Read-out Systems: Imagyne 5 project adaptive power consumption image sensors,

where only significant data are processed. In Classical image processing is based on the addition to the data flow reduction, we introduced analysis of data delivered by a vision sensor in the an asynchronous digital circuitry in the sensor form of images. These sensors with conventional reading architecture because asynchronous clocks receive visual information from the scene circuits are particularly well-suited to manage an sequentially. Each transmitted and recorded array event-driven data flow. Finally, by combining the of data requires generally a post processing. The event-driven behavior, the spatial redundancies array carries the information of all pixels in the suppression and the asynchronous digital matrix, without considering the stability of some circuitry, we designed a power-efficient fully values. Depending on the dynamic content of the asynchronous image sensor [4]. scene, this leads to a high level of data redundancy. In this case of sequential reading, References the output bandwidth of the sensor is shared equally among all the pixels in the matrix. [1] G. Sicard, H. Abbas, H. Amhaz, H. Zimouche, R. Our work suggests the implementation in the Rolland, D. Alleysson, “A CMOS HDR Imager with an CMOS imager of a new control architecture: our Analog Local Adaptation”, IISW workshop, USA, 2013. method reduces the dataflow that goes through [2] H. Amhaz, H. Zimouche, G. Sicard, “Smart Readout the ADC and must be transmitted all the way after Technique based on Temporal Redundancies the converter. For this aim, we are working on the Suppression Designed for Logarithmic CMOS Image suppression of x-axis spatial redundancy, and/or Sensor” IISW workshop, Japan, 2011. temporal redundancy [2]. [3] A. Chefi, A. Soudani, G. Sicard, " Contribution to the Figure 5 shows the Matlab results of a data flow design of a CMOS Image Sensor with Low-Complexity reduction method using the x-axis spatial Video Compression for Wireless Sensor Networks", redundancy. We evaluate, in a scene, the number Journal of Systems Architecture (JSA), Elsevier of pixels that have the same value as their Publisher, Vol. 59, Issue 10, Part A, November 2013 preceding neighbour compared to the total [4] Amani Darwish, Laurent Fesquet, Gilles Sicard, "1- number of pixels in the scene. Note that this kind level Crossing Sampling Scheme for Low Data Rate of implementation makes it easier to perform Image Sensors”, NEWCAS, Trois-Rivières, Canada, motion detection or edge detection. A test chip June 22 – 25, 2014. was designed in 2011 and tested in 2012.

32 TIMA Annual Report 2014 (CIS) Smart sampling for low-power signal processing

Key-words: Non-uniform sampling, Analog-to-Digital Converters, Asynchronous logic, Signal processing

Members: L. Fesquet, Julien Poujaud (PAST), Taha Beyrouthy (External collaborator), Agnès Bonvilain (MNS), Tugdual Le Pelleter (PhD), Amani Darwish (PhD student), Jean Simatic (PhD Student)

Cooperations: UroMEMS, Vigilio, LJK, GIPSA, CEA-LETI

Contracts: CEE (Persyval)

This work is a contribution to a drastic change in sampling: the amplitude of samples is perfectly standard signal processing chains: Analog-to- known but their time instants are quantized (see Digital Converters (ADCs), digital processing Figure 1). circuits, Digital-to-Analog Converters (DACs)… Integrated Smart Devices and Communicating 2 Analog-to-Digital Converters Based on Objects are the important applications targeted by Non-uniform Sampling this study. The main objective is to reduce their In this context, we propose a new class of ADCs, power consumption by one or two orders of based on this non-uniform sampling and on an magnitude, by completely rethinking their asynchronous hardware implementation (without architectures and the associated signal any global clock). The term A-ADC for processing theory. “Asynchronous ADC” is now used. Contrary to previous works carried out in other laboratories, 1 Non-uniform sampling scheme not only does the term “asynchronous” define the Most of integrated systems bring signals with design mode but also the sampling scheme. interesting statistical properties into operation, but Nyquist signal processing architectures do not take advantage of them. Actually, these signals (such as temperature sensors, electro- cardiograms, speech signals...) are almost always constant and may vary significantly only during brief moments. Thus, classical regular sampling systems are highly constrained, due to the Shannon theory, which is to ensure for the sampling frequency to be at least twice the input signal frequency bandwidth. The new idea of this Figure 2: The A-ADC die photography work consists in realising an adaptive sampling scheme of the analog input signal based on its The theory associated with the A-ADC is amplitude variations, and implementing an completely different from classical Nyquist ADCs. architecture only driven by the samples The Signal-to-Noise Ratio (SNR) only depends on occurrences. The sampling scheme is based on the resolution of the local timer and not on the “level-crossing” that provides a non equi- number of quantization levels. A very low repartition of the samples in time. hardware resolution can also be implemented insuring a high SNR i.e. a high Effective Number

bi-1 Of Bits (ENOB). The silicon area and the power bi Vin consumption can thus greatly be reduced. We have elaborated a methodology to enable the designers to precisely calculate the design parameters of an A-ADC, given a target Amplitude application. In order to make a proof of concept, we designed an A-ADC (cf. Figure 2) according to Dt Time i this theory, using the standard CMOS 0.12µm Figure 1: Non-uniform sampling scheme process from STMicroelectronics, for a speech application and an effective resolution of 10-bit. Quantization levels are disposed along the amplitude range of the signal. A sample is taken Non-uniformly sampled digital signal only when the analog input signal crosses one of processing them. Samples are not regularly spaced out in According to the asynchronous digital signal time, because it depends on the signal variations. processing chain defined in Figure 3, we expect This kind of sampling is the dual case of Nyquist drastic gain on power consumption. This work

TIMA Annual Report 2014 (CIS) 33 mainly focuses on the signal theory of non- like the classical regularly sampled chain: an uniform sampling schemes and on the possible analog signal measured by a sensor can be implementations/architectures of such a non- sampled, processed and reconstructed in order to uniformly sampled signal processing. Many provide to an actuator a new analog signal. The studies deal with non-uniform signal theory but difference between the standard technique and are limited to mathematical aspects like recovery ours lies in the reduced number of samples taken of additive-random or jittered sampling process. for low-active signals. The level crossing scheme We decided to study the sampling scheme of the and the proposed signal processing theory level-crossing sampling technique and to apply it implemented using asynchronous hardware lead to practical experiments. to a significant reduction of power consumption making this technology very attractive for the low power SoC era.

Figure 3: Uniform and non-uniform signal processing chain

Among all the digital processes, Finite Impulse Response (FIR) filters have been chosen as a first experiment to illustrate this work, thanks to their stability and convergence properties. The convolution operator is formalized in the non- uniform sampling context in order to define an Figure 4: the experimental setup for the non-uniform algorithm for the FIR filtering computation of non- sampling at the CIME Nanotech uniformly sampled signals. An asynchronous iterative architecture has been proposed to References implement the algorithm. It is formally proven that [1] Le Pelleter T., Beyrouthy T., Leroy Y., Bonvilain A., the computational complexity of the asynchronous Rolland R., Fesquet L., Low-power signal processing platform based on non-uniform sampling and event- FIR filter can be far lower than the computational driven circuitry Design, Automation and Test in Europe complexity of the synchronous FIR filter, provided (DATE'13), Grenoble, France, 18-22 March, pp., 2013 that the signal statistics are well exploited. It has [2] Le Pelleter T., Beyrouthy T., Rolland B., Bonvilain demonstrated that the computational A., Fesquet L., Non-uniform sampling pattern requirements, and hence the energy, can be recognition based on atomic decomposition,10th reduced by more than one order of magnitude International Conference on Sampling Theory and when compared to the standard uniform sampling Applications (SampTA 2013), Bremen, Germany, July scheme. This gain is due to the reduction of the 1st - July 5th, pp., 2013 number of samples processed. It should be noted [3] Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin, "Adaptive Rate Filtering: A Computationally that the gain could even be higher for other Efficient Signal Processing Approach", Signal applications (medical, monitoring…). Processing Journal, Elsevier, Volume 94, January A IIR filtering chain, which processes directly the 2014, Pages 620–630 non-uniform samples without resampling in a [4] Giuseppe Roa, Tugdual Le Pelleter, Agnès regular scheme, has also been studied. Another Bonvilain, Alejandro Chagoya, Laurent Fesquet, developed approach is an efficient online “Designing ultra-low power systems with non-uniform processing technique for non-uniformly sampled sampling and event-driven logic”, SBCCI 2014, 27th signals which smartly combines the features of Symposium on Integrated Circuits and Systems Design, uniform and non-uniform signal processing. This Aracaju, Sergipe, Brazil, September 1st to 5th, 2014 has been applied to spectrum analysis and filtering. This leads to minimize the computational load and enhance the power efficiency. Moreover, a linear interpolated Digital-to-Analog conversion can reconstruct the signal from its non-uniform samples according to the time-interval values.

3 Conclusion To conclude, the digital signal processing chain using a level crossing sampling scheme behaves

34 TIMA Annual Report 2014 (CIS) Design for Security and True Random Number Generation

Key-words: Security, TRNG, Asynchronous Design, asynchronous ring oscillator

Members: L. Fesquet, R. Possamai Bastos, A. Cherkaoui (Post-Doc), L. Acunha Guimaraes (PhD student)

Cooperations: Lab. Hubert Curien, ST, LIRMM, IF, Starchip, Dolphin

Contracts: Semba, LISA

1 Secure circuit design and smart-cards countermeasures are already implemented in Several DES and AES cryptoprocessors (see ASICs to prevent SPA, DPA, EMA and FAs. The Figure 1) have been designed to evaluate the approaches using QDI asynchronous circuits benefits brought by asynchronous logic to improve appear to be very promising and this work aims at circuit resistance against power analysis, transposing these methods in an e-FPGA context. electromagnetic analysis and fault attacks. DES The challenge is first to make the asynchronous prototypes were jointly designed by TIMA, LETI FPGA natively robust against SPA and DPA while and STMicroelectronics in various projects. The being very flexible. Afterwards, countermeasures goal of this work is to study the introduction in against other SCAs and FAs can be easily smart-card IC design of an innovative hardware explored and experimented. The e-FPGA is technology, namely Asynchronous Logic, and to expected to provide the following advantages for evaluate how it can improve security. This work is security: today more focused on electromagnetic attacks in Balanced power consumption — QDI circuits the framework of the EMAISeCi project. which generally use 1-of-n encoding can be balanced to reduce the power consumption dependency with the processed data. Indeed, the bit encoding ensures that the data are transmitted and computations are performed with a constant Hamming weight. This is important since the leakage of the Hamming weight or distance can be exploited by SPA, DPA, and EMA. Absence of a global clock signal — No clock means that FAs based on clock are removed. Moreover, DPA and SPA attacks without global Figure 1: Asynchronous QDI DES cryptoprocessors clock signal are expected to be much more difficult. Indeed, the clock absence will make very 2 An asynchronous e-FPGA for security complicated the synchronization of the DPA and applications SPA signatures. With the growing security needs of applications Environment variation tolerance — QDI circuits such as homeland security or banking, the adapt to their environment such as voltage and frequent updates in cryptographic standards and temperature variations, which means that they the high ASIC costs, the ciphering algorithms on tolerate many forms of fault injection (power an asynchronous embedded FPGA co-processor glitches, thermal gradients, etc). These QDI are becoming a viable alternative. A novel circuits can be easily combined with other asynchronous e-FPGA has been designed and countermeasure to efficiently counteract FAs. fabricated (see Figure 2). Redundant data encoding — QDI circuits typically use a redundant encoding scheme. For example, the dual-rail encoding (a bit is encoded onto two wires) provides a mean to encode an alarm signal to counteract FAs. To validate the e-FPGA native robustness against SPA and DPA attacks, an electrical simulation campaign has been carried out on a Programmable Logic Bloc (PLB) of the e-FPGA Figure 2: The e-FPGA Layout and micro-photography which is designed in CMOS 65 nm technology.

This architecture is natively robust against side channel attacks such as simple and differential power analysis or clock based fault attacks. Many

TIMA Annual Report 2014 (CIS) 35 interval between the events is set in concordance with the clock jitter magnitude, a simple entropy extraction scheme can be applied for generating random numbers. The proposed STR-based TRNG (STRNG) follows AIS31 recommendations: by using a stochastic model, a designer can compute the lower entropy bound as a function of the STR characteristics (number of stages, oscillation period and jitter magnitude). Using the Figure 3: Current profiles of the e-FPGA PLB obtained entropy assessment, he can then set up

the compression rate in the arithmetic post- The current profiles - on Figure 3 - show that processing block in order to reach the required whatever the manipulated data are, the current security level determined by the entropy per profiles are very similar. In other words, the power output bit. The implementations of the generator consumption is data independent. Moreover, the in two different FPGA families illustrate its observation of output variations shows that they feasibility in digital technologies and confirm that it are completely superposed. This means that the can provide high quality random bit sequences e-FPGA running time is data independent. This letting pass the statistical tests required by AIS31 drastically increases the circuit robustness against at rates as high as 200 Mbit/s and more. SCAs exploiting the running time variations. In conclusion, with data independent power 4 Bulk Built-in Current Sensors consumption and a constant running time, the Today’s deep-submicron technology can suffer of proposed asynchronous e-FPGA architecture is severe transient faults, where the fault duration is natively robust against SPA, DPA and timing comparable or longer than a circuit clock cycle. attacks. Such long-duration transient faults have clearly a

high probability of not being masked, and so a 3 Asynchronous True Random Number greater chance of producing Soft errors. This can Generators also be exploited in the context of malicious fault Many True Random Numbers Generators (TRNG) injections in order to retrieve confidential data. use jittery clocks generated in ring oscillators as a We introduced a fast recovery strategy based on source of entropy. This is especially the case in bulk built-in current sensors for detection of such Field Programmable Gate Arrays (FPGA), where transients (BBICS). They detect anomalous sources of randomness are very limited. Inverter transient currents flowing between any reverse Ring Oscillators (IRO) are relatively well biased drain junction and the bulk of circuits characterized as entropy sources. However, it is perturbed by events BBICS indeed takes known that they are very sensitive to working advantage of the fact that such currents are conditions. This fact makes them vulnerable to negligible in fault-free scenarios but are much attacks. On the other hand, Self-Timed Rings higher than leakage currents flowing through (STR) are currently considered as a promising biased junctions during faulty scenarios. solution to generate robust clock signals. Although many studies deal with their temporal behavior References and robustness in Application Specific Integrated [1] Possamai Bastos R., Torres F.S., Dutertre J.M., Circuits ASIC), equivalent study did not exist for Flottes M.-L., Di Natale G., Rouzeyre B. FPGAs. Furthermore, these oscillators were not A Bulk Built-in Sensor for Detection of Fault Attacks analyzed and characterized as entropy sources IEEE International Symposium on Hardware Oriented aimed at TRNG design. We analyzed STRs as Security and Trust (HOST), Austin, TX, USA, June 2-3 , entropy sources for TRNGs implemented in pp.51-54, 2013 ASICs and FPGAs. Next, we compared STRs and [2] Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, IROs when serving as sources of randomness. Laurent Fesquet, “A Self-timed Ring Based True We show that STRs represent very interesting Random Number Generator”, 19th International alternative to IROs: they are more robust to Symposium on Asynchronous Circuits and Systems environmental fluctuations and they exhibit lower (ASYNC), Santa Monica, USA, May 19-22, 2013 extra-device frequency variations. Based on these [3] Laurent Fesquet, Jérémie Hamon, Abdelkarim considerations, we proposed a new true random Cherkaoui, “Générateurs de nombres aléatoires vrais”, number generator (TRNG) able to exploit the jitter brevet déposé le 6 février 2012, N° FR 12 51079 of events propagating in a self-timed ring (STR) [4] Taha Beyrouthy, Laurent Fesquet, “An for generating random bit sequences at a very Asynchronous FPGA Block with Its Tech-Mapping high bit rate. It takes advantage from a special Algorithm Dedicated to Security Applications,” feature of STRs allowing to adjust the time International Journal of Reconfigurable Computing, vol. 2013, Article ID 517947, 12 pages, 2013 elapsed between successive events as short as needed, even in order of picoseconds. If the time

36 TIMA Annual Report 2014 (CIS) Asynchronous Circuit and System Design

Key-words: Asynchronous Design, asynchronous ring oscillator, GALS,

Members: L. Fesquet, R. Possamai Bastos, A. Cherkaoui (Post-Doc), Tugdual Le Pelleter (PhD student), Chadi Al Khatib (PhD student), Mohamed Gana (PhD student), Jean Simatic (PhD Student), Otto Rolloff (PhD Student)

Cooperations: Lab. Hubert Curien, ST, LIRMM, UroMEMS, Defacto, Starchip, Dolphin, Tiempo

Contracts: Semba, HiCool, LISA, Things2Do

1 Introduction: asynchronous circuits and synchronization through «rendezvous» for systems example, are easily implemented by a collection The global synchronization strategy of of independent and local finite state machines, synchronous circuits was introduced in the early which do not require knowing the state of the 70s because at that time, it was a satisfactory whole system. Data to be computed by the answer to design needs and technological system flow in the architecture as fast as they can potentials. This initial choice of an implementation accord resource availability and hardware strategy, drove and is still driving the design of implementation. The processing cost (in terms of algorithms/architectures, languages and CAD delay and power consumption) is exactly the tools. Today, integration potentials of advanced image of what is specified by the algorithm, given technologies are going beyond design the chosen hardware implementation. It means productivity, and one can wonder whether the that speed and power consumption may depend synchronous circuit style is still relevant. on the data processed. The data-flow behavior of Asynchronous circuits which were introduced in asynchronous circuits, at any level of granularity, the mid 50s, receive now increasing interest. is the source of significant improvements in terms What significant benefits are they likely to offer? of speed/power optimizations and ease of design. Can they contribute to improve design productivity Moreover, this approach can be fruitfully coupled in the future? to an event-based non-uniform signal processing Our motivation is to answer these questions, which provides drastic power reduction, thanks to investigating what impact asynchronous circuits a dedicated signal processing theory. may have on the design of integrated systems Finally, asynchronous circuits also bring flexibility and how to take advantage of this circuit style at at the system level. Complex, highly concurrent different levels: circuit level, image processing applications naturally take architectural/algorithmic level, specification level, advantage of the locality and modularity of clock- and system level? Because asynchronous circuits less circuits. Because they don't need a global provide more flexible, robust and reliable synchronization signal, modularity is a major synchronization and communication mechanisms, property of asynchronous circuits which enables they give rise to alternative and innovative the design of complex integrated systems by solutions that have to be analyzed and evaluated. simply assembling functional blocks. Design time is thus reduced and reusability increased. As an At the circuit level, asynchronous logic enables example, the design of locally-synchronous the design of delay insensitive circuits which do globally-asynchronous SoCs bring a solution to not require accurate and costly delay the problem of communications between distant characterization. In fact delay insensitivity parts using long interconnects. Without requiring guarantees a correct functional behavior drastic change in terms of tools and independently of the propagation delays in the methodologies, synchronous parts of SoCs may basic components (gates, interconnects…). Delay be interconnected using advanced and robust insensitive asynchronous circuits are for example asynchronous interfaces. insensitive to some emerging problems like delay The potentials of asynchronous circuits are being fault due to crosstalk or process variations. The investigated through the design of mobile systems delay insensitivity property makes asynchronous (from smart-card to multimedia terminal). There circuits very promising to exploit advanced CMOS are three main properties of asynchronous circuits and nanometric technologies. that can improve such systems and/or make their Eliminating the global clock, which synchronizes design easier: electromagnetic compatibility, low all parts of circuit in synchronous logic, provides power, power management and flexible more flexibility to design system architectures. In interfacing capabilities. Interfacing digital fact, the control is naturally distributed rather than asynchronous circuits with analog parts (RF front- centralized. Hence, communications as well as end, sensors, actuators, etc.) is also a major field

TIMA Annual Report 2014 (CIS) 37 of interest. It is in fact essential if we expect to the average speed performance of the system successfully design SoCs that may integrate under different cases of the process variability various kinds of digital and analog parts. effect while keeping reduced the overall system energy consumption. Moreover, this is achieved 2 Self-timed ring oscillators with a small area overhead. The results are Low phase noise multi-phase oscillators based on validated on a MIPS R2000 processor node using self-timed ring have been extensively studied. the 40nm CMOS technology from Indeed, the self-timed rings (STR) are promising STMicroelectronics. approach for designing high-speed serial links and clock generators. Indeed, the architecture of Self- 4 Asynchronous distributed controllers for timed rings allows us to achieve high frequencies gated clock and power with multiphase outputs and their oscillation In a synchronous system, the clock tree is always frequency does not only depend on the number of on. Indeed, it synchronizes the whole chip without stages but also on the initial state of the ring. discarding the inactive circuit parts. For this Moreover, this architecture allows us 3dB phase reason, the implementation of a gated clock noise reduction when, while keeping the same structure is a good way to limit the dynamic power frequency, the stage number is doubled. In this consumption. Nevertheless, this needs extra research, we propose a complete method to computation to determine which part of the circuit design Self-timed rings able to generate high- has to be switched off. Another approach is to speed multi-phase outputs. A test chip has been locally synchronize the data between blocks. This designed and fabricated in STMicroelectonics will make the circuit globally asynchronous and CMOS 65 nm technology to verify the theoretical locally synchronous. For implementing such an claims. approach, it is possible to design asynchronous distributed controllers that carry out data signaling. This gives the opportunity to exploit the local synchronization signals for locally controlling the clock or the power.

Figure 2: Distributed clock and power controllers

References Figure 1: Self-timed rings under test [1] Yahya E., Fesquet L., Ismail Y., Renaudin M., Statistical Static Timing Analysis of Conditional 3 Process variation robust and energy- Asynchronous Circuits Using Model-Based Simulation, 19th International Symposium on Asynchronous efficient control for SoCs Circuits and Systems (ASYNC), Santa Monica, USA, The design of complex systems-on-chip (SoCs) in May 19-22, pp.67-74, 2013 the advanced CMOS technologies has become [2] Hatem Zakaria, Laurent Fesquet, “Designing a increasingly challenging due to the high levels of Process Variability Robust Energy-Efficient Control for integration, the excessive energy consumption, Complex SoCs” IEEE Trans. On Emerging and Seected the clock distribution problems and the increased Topics in Circuits and Systems (JETCAS), Vol. 1, No. process variability impact. To deal with these 2, June 2011 issues, we considered network-on-chip (NoC) [3] Sylvain Durand, Hatem Zakaria, Laurent Fesquet, architectures partitioned into several voltage- Nicolas Marchand, “A Robust and Energy-Efficient frequency domains and developed an efficient DVFS Control Algorithm for GALS-ANoC MPSoC in control algorithm for on-the-fly workload Advanced Technology under Process Variability monitoring and management. This algorithm is Constraints”, Advances in Computer Science : an able to cope with the technology-related variability International Journal (ACSIJ), Volume 3, Issue 1, and with the variable workload of the system. It January 2014 dynamically controls the speed of the different [4] Eslam Yahya, Oussama Elissati, Hatem Zakaria, voltage-frequency islands with respect to the Laurent Fesquet and Marc Renaudin, process variability impact on each island. Within “Programmable/Stoppable Oscillator Based on Self- Timed Rings”, 15th IEEE International Symposium on this work, a new clock synchronization scheme is Asynchronous Circuits and Systems” (ASYNC), Chapel also presented. Simulation results demonstrated Hill, North Carolina, 17-20 May 2009. the effectiveness of our approach in guarantying

38 TIMA Annual Report 2014 (CIS) Bulk Built-in Current Sensors (BBICS)

Members : Rodrigo Possamai Bastos

Environmental variations push up huge design flows based on CMOS standard cells of challenges to the design of integrated systems. commercial libraries. BBICS combine the high Perturbation events arisen from environmental detection efficiency of costly fault-tolerance or intentional sources are today able to schemes (e.g. duplication with comparison) produce transient faults in circuits by with the low area and power overheads of less temporarily modifying node voltages, and efficient mitigation techniques such as time provoking soft errors in stored results from redundancy approaches. Several architectures system operations. of BBICS were recently proposed by our group Examples of environment events are alpha to monitor transient faults induced on particles released by radioactive impurities and integrated circuits by radiation or malicious more importantly neutrons from cosmic rays. sources. The proposed sensors detect On the other hand, intentional perturbation anomalous transient currents flowing between events are usually produced by optical sources any reverse biased drain junction and the bulk such as flashlights or laser beams, which can of circuits perturbed by events. BBICS indeed maliciously induce transient effects on secure takes advantage of the fact that such currents circuits to retrieve their secret information. are negligible in fault-free scenarios but are Such circuit misbehaviors from fault-based much higher than leakage currents flowing attacks provide fundamental information for through biased junctions during faulty cryptanalysis methods that are able to break scenarios. security applications. A test chip on CMOS 65 nm was designed with Among the several design strategies for different BBICS architectures (Figure 1) and detection of transient faults caused by fabricated in 2014 in cooperation with CMP radiation or optical sources, Bulk Built-In (Gardanne) and LIRMM (Montpellier), laser- Current Sensors (BBICS) offer a promising based tests will be done at beginning of 2015 solution that is perfectly suitable for system to validate our BBICS schemes.

Figure 1. Test chip that validates BBICS

References [3] Dutertre, J.M.; Bastos, R. P.; Potin, O.; [1] Dutertre, J.M.; Bastos, R. P.; Potin, O.; Flottes, M.L.; Rouzeyre, B.; Di Natale, G., Design Flottes, M.L.; Rouzeyre, B.; Di Natale, G. ; of Bulk Built-In Current Sensors to Detect Single Sarafianos, A., Improving the ability of Bulk Built- Event Effects and Laser-Induced Fault Injection In Current Sensors to detect SEEs by using Attempts. In open Forum on Trustworthy triple-well CMOS. Elsevier Microelectronics Manufacturing and Utilization of Secure Devices Reliability Journal, 2014. (TRUDEVICE) 2014. [2] Bastos, R. P.; Dutertre, J.M.; Torres, F. S., Comparison of Bulk Built-In Current Sensors in terms of Transient-Fault Detection Sensitivity. In: European Workshop on CMOS Variability (VARI), 2014.

TIMA Annual Report 2014 (CIS) 39

40 TIMA Annual Report 2014 (CIS)

Theme 2 / MNS Group Micro Nano Systems

Themes

MEMS microcomponents - Microgenerators - Acoustic microsensors - Pressure microsensors - Time base microresonators BIOMEMS microsystems

Expertise

Scientific Design, Modeling, Manufacturing and Characterization of MEMS Fields of expertise MEMS - Analytic modeling and finite elements In-IC MEMS Know-how MEMS manufacturing in clean-rooms and by rapid prototyping MEMS optical and electrical characterizations Industrial transfer 2011: Creation of the UroMEMS company

Research keywords

MEMS, Microsensors, Micro-energy, Micro-acoustics, BioMEMS

Contact

Skandar BASROUR UJF Professor – TIMA (+33) 476 57 43 07 [email protected]

TIMA Annual Report 2014 (MNS) 41

42 TIMA Annual Report 2014 (MNS) Micro Power Generators for Autonomous Microsystems

Key-words: Energy harvesting, Piezoelectric materials, Piezoelectric layers fabrication.

Members : S. Basrour, L. Rufer, M. Colin, M. Cueff, E. Trioux, Q. Mortier, A. Kachroudi

Cooperations: CEA – Leti, TRONICS, CEDRAT, EASii-IC, SORIN-CRM, PicDi, Altim, SETAM, Vermon, ENSMM, FEMTO-ST, INL,, ESIEE-Paris, LGEF,, IES,.EPFL (Lausanne, Switzerland), LMOP (Tunis, Tunisia)

Contracts: HBS (FUI 2010-13), uSEEMPE (2010-13), Altide (FUI 2011-14).

Energy harvesting has been the subject of intense As a consequence, main actors in the field of research over the last decade. Many transduction cardiac rhythm management (CRM) implants principles have been presented as potential ways prepare miniaturized and autonomous leadless of scavenging the ambient energy (thermal, implants, which could be directly placed inside a mechanical, radiative…) and transforming it into human heart. usable electrical energy. Among these principles, The idea of a stand-alone cardiac implant is not the piezoelectric transduction is probably the most new and several approaches for powering the studied one. The large-scale deployment of such device have been suggested. More recently, devices will result in increased safety, lower researchers from University of Michigan, Ann maintenance costs and extended lifetime of Arbor, USA presented simulation results of a autonomous sensors that are used in many piezoelectric energy harvester operating at 40Hz application fields (medical implants, civilian and that could in theory power a cardiac implant with industrial structural health monitoring…). heart-induced vibrations. Our colleagues from the Most of the approaches that we have studied so Sorin and the CEA/Léti have obtained the heart far were based on resonant piezoelectric devices acceleration spectrum by placing accelerometers which working frequencies are above 200Hz. The inside several heart cavities. It appears that the piezoelectric energy harvesters that we have heart vibration energy is rather localized at lower proposed are currently at the state of the art. frequencies in a frequency band from 5 to 30 Hz. However, while most of the piezoelectric vibration The HBS project (FUI 2010-13) aims at energy scavengers developed so far were developing the technology of leadless designed to be effective at relatively high pacemakers. It gathers experiences from the frequencies (above 200 Hz), we currently work on industry (Sorin, EasiiIC, Cedrat, Tronics) together the development of energy harvesters designed to with the CEA-Léti and the TIMA laboratory. scavenge energy from real vibrational sources. In this project, the TIMA laboratory is in charge of Such a design must take into account a wide- the design, the fabrication and experimental band spectral content of a source acceleration characterization of a piezoelectric energy centered in a frequency band not exceeding harvester prototype operating at very low 100 Hz. The dimensional aspects as the geometry frequency range (10 to 16 Hz). This device, in its and the volume as well as the energy final application, will be excited by the heartbeats requirements are important constraints and play and will make part of a new generation of role in the design strategy. pacemakers. The studied device is beam-like harvester made of two lead zirconate titanate In the following paragraphs, we will describe the (PZT) thick films assembled in bimorph simulation, fabrication and characterization of configuration with dimensions chosen in a way to energy harvesters for two different applications. achieve the resonance below 15Hz. At the same time, constraints applied on dimensions and 1. Heart Beat Scavenging generated power must be satisfied. Current version of implatable cardioverter Heart acceleration signals have been first defibrillators (ICDs) and pacemakers consists of a measured experimentally by placing a 3D battery-powered pulse generator connected onto accelerometer on heart muscles of both animals the heart through electrical leads inserted through and human patients. The spectral content of these veins. However, it is known that the long-term signals was studied and the energy distribution of lead failure may occur and can cause the device these quasi-periodic signals has been analyzed. dysfunction. When required, the removal of failed Given the volume of the leadless pacemaker, we leads is a complex procedure associated with a have shown that the PZT layers must be 15-20µm potential risk of mortality. thick in order to both comply with the energy TIMA Annual Report 2014 (MNS) 43 source frequency (15Hz) and the heart stimulation an embedded electronic circuit. The electronic energy requirements. However, it appears that circuit will integrate a RFID module to none of current fabrication processes can be used communicate with a global database. This will for manufacturing such thick PZT films. Using enable to precisely follow each essential part of processes derived from the microelectronic field the industrial tool. such as Sol Gel deposition or sputtering, the As shown in Figure 2, energy level can achieve maximum achievable thickness is about 2-5 µm. 4 g. However, average energy is only 0,4 g, which In contrary, using co-firing techniques, the PZT is much lower. Furthermore, any particular peak in plates can hardly be thinner than 100 µm. The the energy spectrum can be chosen to design a manufacturing of above described piezoelectric harvester as presented in Figure 3. It is possible scavenger corresponds to an actual process blind to harvest energy from DC to 150 Hz. Three areas window. As a consequence, we work on the can be identified. The first extends from DC to 40 implementation of fabrication processes of PZT Hz, the second from 40 to 60 Hz and the last from thick films. We focus on the optimized grinding 60 to 80 Hz. Signal energy content decays and polishing techniques of bulk ceramics. drastically above 150 Hz. The spectrum content In parallel, a scaled-up demonstrator of the depends on the vehicle load. However, spectrum scavenger operating at 15Hz has been fabricated from 60 to 80 Hz is less disturbed than spectrum and tested (Figure 1b). The test results are in from DC to 60 Hz by the loading condition. good agreement with predictions from our analytical and numerical models. Currently, we have fabricated and tested the monomorph energy scavenger (Figure 1b). The metallic substrate is used as a bottom electrode. We added a 5.4 x 6.15 x 5 mm3 proof mass made of tungsten (2.36 g) in order to decrease the resonance frequency of the device down to 15 Hz. The total length was 31 mm. Under a harmonic excitation of 10 mg only, the mean power transferred to a 150 kΩ resistance was 1.3 µW (VRMS = 0.43 V) and the transverse displacement amplitude is 300 µm. Figure 2: Excitation time signal measured along vertical axis

21 mm! 8 mm!

5 mm!

tip mass!

Figure 1: a picture of the fabricated cantilever scavenger mounted in the test clamping element.

The electrical performances of such devices are among the best published in the literature. Figure 3: Fast Fourier Transform of the acceleration

signal. 2. Seismic Microgenerator for Traceability System There is no specific frequency, which can be The goal of the ALTIDE project is to develop a chosen to design a resonant harvester. A traceability system for industrial tools, in order to broadband, non-resonant solution is currently optimize maintenance. The project is lead by under investigation. Altim, a small company from Haute-Savoie. Two Reference other industrial partners are involved: PicDi, a [1] Colin, M. Basrour, S., Rufer, L., Bantignies, C., small company specialized in RFID devices, and Nguyen, A., Highly Effective Low Frequency SETAM as the end user. The AS2M department Energy Harvester Using Bulk Piezoelectric from FEMTO-ST is also involved to work on Ceramics, (PowerMEMS), 3-6 December 2013, database development. London, UK, pp. 641-645. The main goal of TIMA Laboratory in this project is to develop a micro-power generator to scavenge mechanical vibrations to power 44 TIMA Annual Report 2014 (MNS)

Microsystems for Health

Key-words: Urinary sphincter, Medical needle, piezoresistive microgauges, Vibration sensor,

Members : S. Basrour, A. Bonvilain, L. Rufer, T. Le Pelleter, Aïteb Naimi

Cooperations: UroMEMS, IMACTIS, CHU Grenoble, TIMC-IMAG, SIMaP,

Contracts: SiRéMi (Carnot LSI 2012), GAME_D (ANR 2013-2016)

in the artificial urinary sphincter is then established. 1. Artificial Urinary Sphincter Finally we have designed and tested the prototype This work is performed in collaboration with TIMC- of the artificial urinary sphincter. The mechatronic IMAG laboratory and an urologist physician at la system and the functionality of the device are then Pitié Salpétrière hospital in Paris. It proposes to evaluated and validated, first in vitro, and then in solve the problem of urinary incontinence with a vivo. new adaptive autonomous artificial urinary sphincter. Nowadays, we work to minimize energy consumption to provide greater autonomy to the Urinary incontinence is defined as the involuntary implant. Different ways are explored like the leakage of urine and there are several surgical optimization of algorithms, of the signal data methods to alleviate it. In the event of a major processing [1], and of the actuation. leak, the establishment of an artificial urinary sphincter can give patients a normal social life. Nowadays, there is only the prosthesis developed 2. Deformation measurements of a cylinder: by the American Medical System Company particular case of a medical needle (Figure 1 left), which remedies to severe This work is performed in collaboration with TIMC- incontinence. IMAG laboratory. It proposes to solve the problem Our work aim for replacing the manual pump of knowing the precise position of the tip of a mechanism used by many patients worldwide by a flexible cylinder inserted in a non-transparent mechatronics implanted device. environment. The prototype developed is shown on Figure 1 Percutaneous medical procedures for diagnosis or (right). In this work, we propose a study on a therapeutics, guided or not by imaging dynamic control of the system, which improves its (ultrasound, fluoroscopy imaging, magnetic efficiency, by adjusting the behavior of the system resonance imaging, etc.) aim at introducing, to the patient and his lifestyle. We developed also through the skin, an instrument to a previously a communication between the implant and the identified target. However, the path of the outside world via a RF link. instrument can be deviated by an obstacle. To facilitate the implementation of these procedures, tools for tracking and navigation were specifically developed. While these tools have really helped to revolutionize medical practices, they suffer from several limitations, among which two are specifically identified: the cost and the assumption of the dimensional stability of the instrument used. Indeed, the interaction of a deformable instrument with the human tissue is a source of its deformations, which can cause a failure of Figure 1: Artificial urinary sphincter AMS 800 (a) cuff interventional medical procedure. (b) balloon (c) pump (left) and Prototype of the new artificial urinary sphincter (right) This work is focused on the integration of microsensors (piezoresistive microgauges) on the Some measurements are performed on the deformable tool to allow the real time monitoring patient with microsensors. We extract various of its deformations. relevant information to adapt the occlusive pressure of the artificial urinary sphincter. The We first conducted a feasibility study by detection algorithm designed to be implemented developing a macroscopic prototype consisting in a medical needle on which we manually glued TIMA Annual Report 2014 (MNS) 45 commercial gauges. Experiments of this first which is expert in materials. prototype have allowed us to validate the Nowadays, we establish statistics on our analytical and numerical models. numerous experiments. And we envisage making In the next step, we aimed to integrate annealing tests on samples to improve the piezoresistive micro-gauges directly on the body characteristics of the poly-Ge. After, we shall of the needle. The challenge of this step consists envisage improving the microfabrication process, in a micro-fabrication process that has to be to fabricate a new prototype. performed on an unconventional substrate (in terms of form (curved) and material (stainless steel)) corresponding to a needle surface. References We determine the dimensions and the constitution [1] Le Pelleter T., Beyrouthy T., Leroy Y., Bonvilain A., of the germanium piezoresistive microgauges with Rolland R, Fesquet L. Low-power signal the help of the previous analytical and numerical processing platform based on non-uniform modeling. Then we developed the sampling and event-driven circuitry. Design, microfabrication process of the microgauges on Automation and Test in Europe (DATE'13), Grenoble, France, 18-22 March, pp., 2013. the needles. With these results (Figure 2), we have shown that it is possible to integrate microsensors on the body of the needle. These works will open a new way of monitoring deformable tools inserted in a non-transparent environment.

a) b) Figure 2: Microgauges: a) on steel needle, and b) on NiTi needle We have then begun to test these new microsensors after doing a bonding connection. The experimentations consist in making a controlled deflection to the tip of the needle, and to measure the variation of the resistance of the microsensor. The first results (figure 3) show five straight trajectories (6 mm) of the tip of the needle (3 mm on each side from the non deformed position). Thirteen measured points are defined. Several microgauges are already experimented in the same conditions (about 40), and the results are similar. So we can deduce that we have a good repeatability of the measures. We can after calculate the experimental gauge factor (GF) of the microsensor. For the different experimented microgauges, we find a GF around 3. The theoretical one was about 45, so it is not as high as expected. This difference can be explained essentially by three reasons: - the Π factor is not well known, - the resistivity of the poly-Ge seems to be not homogeneous on the entire surface, - all of the parameters of the crystallization of the Ge are also not well known. So we have initiated works with SIMaP laboratory

46 TIMA Annual Report 2014 (MNS)

Design and Technologies for Integrated Micro and Nano Systems

Key-words: Acoustics, Aero-acoustic sensor, CMOS-MEMS, Ultrasound, Surface Acoustic Waves,

Members: S. Basrour, L. Rufer, M. Gorisse, J. Esteves, Z. Zhou, Y. Civet, F. Bernard.

Cooperations: STMicroelectronics, LMFA (Lyon), LIRMM (Montpellier), Hong Kong University of Science and Technology, Escola Politécnica da Universidade de São Paulo (Brazil), INRIA (Lille), Université de Lille 1, CEA Léti (Grenoble), AlphaUI, Orange Labs, EASII IC,

Contracts: SIMMIC (ANR, 2011-14)), PHAMM (BQR- INP, 2011-14), Touch-It (FUI, 2012-2015), MANI (Capes-Cofecub, 2011-14), Transpin (RTRA, 2010-2014), NACRE (Nano 2012).

1. High-frequency aero-acoustic sensor This microphone was calibrated using the N-wave Aero-acoustics, a branch of acoustics which method developed by our partners from LMFA. studies noise generation via either turbulent fluid The measured and calculated microphone motion or aerodynamic forces interacting with frequency characteristics are shown in Figure 2. surfaces, is a growing area and has received fresh emphasis due to advances in air, ground and space transportation. While tests of a real object are possible, the setup is usually complicated and the results are easily corrupted by the ambient noise. Consequently, testing in relatively tightly-controlled laboratory settings using scaled models with reduced dimensions is preferred. However, when the dimensions are reduced by a factor of M, the amplitude of the corresponding acoustic waves is increased by 10logM in decibel and its bandwidth by M. Therefore microphones with a bandwidth of Figure 2: High-frequency sensor characteristics several hundreds of kHz and a dynamic range covering 40Pa to 4kPa are needed for aero- 2. CMOS-MEMS for acoustics acoustic measurements. Recently, different works showing the feasibility of MEMS using CMOS technology followed by Micro-Electro-Mechanical-systems (MEMS) surface micromachining without mask have been microphones using the piezoresistive principle, published. Unlike the older approach, where compared with all other working principles can suspended MEMS components were obtained by achieve a higher sensitivity bandwidth (SBW) silicon substrate etching, the proposed technology product due to its scaling characteristic, and consists in etching oxide layers resulting from the therefore they are well suited for aero-acoustic CMOS process and thus releasing metallic layers measurements. In this collaborating work with the of the same CMOS technology. Hong Kong University of Science and Technology, a metal-induced-lateral-crystallized (MILC) In this project, we develop a technological process polycrystalline silicon (poly-Si) based in terms of the etching type, etching time, as well piezoresistive type MEMS microphone was as the feasible extreme dimensions for simple designed and fabricated. Figures 1a) and b), show structures in CMOS technology. We have also the sample plan-view and cross-sectional view. validated the CMOS-MEMS process by the development of MEMS acoustics devices. Two a) b) different sorts of devices are considered: a capacitive microphone and a capacitive micromachined ultrasonic transducer (CMUT) for biomedical applications. At this stage, the modeling and the fabrication of a SiO a-Si LS-SiN capacitive microphone shown in Figure 3 have 2 Cr/Au MILC Poly-Si been done. The results of the sacrificial layer etching are shown in Figure 4. The Figure 1: High-frequency microphone: a) Plan-view optical micrograph of a fabricated sample; b) Cross- characterization of the microphone is in progress. sectional view of the sensor

TIMA Annual Report 2014 (MNS) 47 is aiming smartphones screens, is anticipated, and some issues were already solved. The integration into mobile devices is the biggest challenge of this project. This involves a reduction of the power consumption for the actuation. Based on physical equations, an equivalent model of the vibration slab has been generated. Knowing the

Figure 3: CMOS-MEMS microphone structure cross- different parameter of the entire system, the section. vibration frequency can be adjusted to provide the best highest electro-mechanical transduction. Thanks to piezoelectric transducers leaded as sensors, the equivalent model is integrated into the sensor detection in order to reduce the time of frequency adaptation. A real time feedback loop is generated. A study on those sensors has been made. A characterization of the best position providing the highest feedback signal has been carried-out. A latency time of the entire feedback loop still has to be established.

Figure 4: Structure of the CMOS-MEMS microphone after the etch. 4. SAW Transducers Most of the current semiconductor technology is 3. Haptic Interface based on the control of the electron charge. Only Most of the available technological consumer recently, it has been proposed that the electron objects neglect the sense of touch. Yet, this sense spin could be used as a new control variable. This is one of the most important for human beings. concept stems from the idea of storing information The project called Touch-It plans to design a new in small magnetic objects, widely used in haptic interface (i.e., an interface that allow a magnetic memories. The production and control of tactile feedback for the user) that could be spin-polarized electronic currents have nowadays implemented on every kind of existing tactile an enormous technological impact. Yet, the screens, from mobile phones to laptops, or remote combination of spin current and quantum physics controls. is not as much developed. In particular, the control of electron spins in phase coherent set- The existing technologies concerning these ups offers immense opportunities for novel applications present several drawbacks, among devices, like spin filters, spin-based transistors or them the disappointing fineness of the texture, the switches. relatively large electrical consumption (more than 600 mW), which is crippling for mobile Recently, a lot of effort has been invested to trap applications, the low system integration, with a a single electron in a quantum dot defined dedicated and bulky packaging. electrostatically in a two-dimensional electron gas (2DEG) defined in GaAs heterostructures. By Considering this, the project proposes an local gating, one can change the charge integrated solution using thin film piezoelectric contained in the dot and succeed to trap only one actuators creating a squeeze film effect on the electron. surface. This device allows a fine texture rendering by changing the friction coefficient. The purpose of this project is to explore different experimental possibilities to coherently transport a The project is focused on five major aspects: single electron spin from one dot to another in transparency, consumption reduction, integration, GaAs heterostructures. The coherent transport design of new applications and cost reduction. consists in transferring the electron in the TIMA is supporting the fabrication of the actuators quantum channel where spin information has to by the design and modeling. be preserved and to convey the electron to the TIMA proposed a whole finite elements study of second quantum dot. A possible option to realize the design of the actuators, taking into account the quantum channel consists in engineering a the different materials, from silicon devices to moving quantum dot. In this way, the electron will glass applications, and geometries. We also set be transferred to its final position all along a path up a characterization bench using a velocimeter to isolated in space from the other electrons. The measure the displacement amplitude of the realization of a moving quantum dot is enabled by mechanical vibrations. A retrofit of the measured the excitation of surface acoustic waves (SAW) devices has been made, showing a good match with k-vector perpendicular to the electrostatic with finite elements results. The next step, which trapping potential. Due to the piezoelectric 48 TIMA Annual Report 2014 (MNS) properties of GaAs, the electron will be trapped in the minimum of the electrical field generated by the stationary surface waves. Its feasibility has been demonstrated recently. The project is developed by the Louis Néel Institute, in collaboration with IMEP-LAHC and TIMA. TIMA is responsible for the design of an interdigited transducer (IDT) for the SAW generation. We have proposed several structures of IDTs used to generate SAW on GaAs substrates in the GHz frequency range and in ultra-low temperature having low insertion loss.

The structures were designed with the main objective to stimulate a unidirectional propagation from the transducer (SPUDT – Single phase unidirectional transducer). The other objective was to avoid different secondary effects that degrade the generated SAW in term of transfer function shape deformation. Among these effects are SAW reflection, multi-mode excitation, and multiple transit echoes.

Different IDT structures were considered and fabricated in collaboration with the Louis Néel Institute. The main challenge of this part of the project is the realization of IDTs having an 20nm Cr extreme aspect ratio and a metal line width of fraction of micrometer. 5. Frequency Compensated MEMS Resonators The performance of electronic systems is generally limited by the accuracy and stability of Figure 5: a) Frequency variations depending on the clocks or frequency references they use. localized correction area (FEM simulations); b) Micro-Electro-Mechanical (MEM) resonators offer Frequency electrical measurements of a wine-glass a promising alternative to industrial quartz crystal disk resonator before correction; c) SEM pictures of time references thanks to size reduction, low cost, localized correction onto bulk mode resonator CMOS integration and multi-frequency applications. However, since MEM resonator Further electrical measurements are under frequency is linked to device dimensions, progress onto bulk mode resonators to observe manufacture mismatch induces frequency frequency shift and check the relevancy of the deviations. Our work proposes to investigate an modelling and accuracy of the method. “in-line” trimming by compensation-localized deposition. Bulk mode (plate & disk) resonators We also investigated charge phenomena at Si / have been studied with compensation smartly SiO2 interface on SOI wafer. We provided a full localized onto micro-resonators. Taking into electrical model of substrate and charges in order account a lithography resolution of 50 nm, to well implement electrical measurements set-up simulations of finite element model (FEM) as well and take into account charge influence onto as analytical modeling provide as low as 40 ppm resonator behaviour. resolution of the frequency dispersion over a full References wafer. Figure 5 shows FEM results of a wine- [1] Zhou, Z., Rufer, L., Salze, E., Yuldashev, P., glass mode disk resonator (a), electrical Ollivier, S., Wong, M., Bulk micro-machined wide- measurements of the latest (b) and localized band aero-acoustic microphone and its application correction via lift-off process (c). to acoustic ranging, J. Micromech. Microeng. 23, 2013. [2] Esteves, J., Rufer, L., Basrour, S., Ekeom, D., CMOS-MEMS technology with front-end surface etching of sacrificial SiO2 dedicated for acoustic devices, 5th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI’13), Bari, Italy, 13-14 June 2013, pp. 154-159. [3] Casset, F., Danel, J.S., Chappaz, C., Civet, Y., Amberg, M. et Al., Low voltage actuated plate for haptic applications with PZT thin-film, Transducers and Eurosensors XXVII, 2013, p. 2733-2736. TIMA Annual Report 2014 (MNS) 49

50 TIMA Annual Report 2014 (MNS)

Theme 3 / Design and verification of Systems on a chip architectures SLS Group: Design

Themes

Architectures and CAD software for multiprocessor systems on chip and networks on chip Modeling and simulation techniques for software/hardware interfaces Specification and implementation of embedded systems on chip Reconfigurable prototyping platform for system validation

Expertise

Scientific Integration and optimization of Multiprocessor hardware/software systems Fields of expertise Multiprocessor architecture, Network on chip, Memory subsystems, On chip embedded operating system, Fast simulation of digital systems, Methods and tools for system level synthesis, Reconfigurable architectures Know-how Design of circuits and integrated systems, FPGA, Operating systems, Software/hardware integration Industrial transfer Patent for 3D asynchronous circuitry, patent pending on buffer sharing in NoCs, 8 CIFRE theses over the 4 last years (2010 – 2014) Re Research keywords search kords System simulation, network-on-chip, memory hierarchies, 3D design, reconfigurable computing, low-level software, digital system architecture, dynamic binary translation

Contact

Frédéric PÉTROT GRENOBLE INP Professor – TIMA (+33) 476 57 48 70 [email protected]

TIMA Annual Report 2014 (SLS) 51

52 TIMA Annual Report 2014 (SLS) Innovative MPSoC Architectures: memory hierarchy, reconfigurable systems

Key-words: HLS tools, dynamic reconfiguration, FPGA visualization,

Members : S. Mancini, O. Muller, F Pétrot, F. Rousseau, A. Abrial, P.H. Horrein, A. Prost-Boucle, Y. Xu, V. Schwambach Costa

Cooperations: Télécom ParisTech, STMicroelectronics, Telecom Bretagne, LIP6

Contracts: iGlance (CATRENE)

Trends in MPSoC are towards massively memory performance (latency, throughput). parallel and homogeneous architectures. The underlying issues of these architectures are Mmopt : Memory Management optimization the memory wall (access to memory does not in a HLS flow scale as Moore's law), power wall (power When designing hardware accelerators for low consumption is limited by dissipation) and level vision kernels (image correction and programmability wall (parallel machine are transformation), one as to efficiently manage hard to program ). the transportation of data from huge and cheap To contribute in this field, we provide memories to embedded memories, the closer architectural mechanisms to relieve the to the computing unit. Then the designer has pressure on memory, by optimizing memory to find a trade-off between the amount of accesses. We are also working on increasing loaded data, the size of embedded memories the efficiency of MPSoC cores by using and the overall computing time. application specific cores (or hardware To overcome the limitations of standard components) in reconfigurable systems, with commercial HLS tools, the Mmopt tool and friendly tool-suites for easier programmability. methodology acts as a pre-process in a HLS Both research activities are presented in the flow to help the designer finding pareto optimal following sections. solutions and automatically generates an efficient memory management controller. Simplification and optimization of data Mmopt targets “non-linear” kernels, which access memory references are non-linear functions of loop indexes. The optimization process takes nD-AP Cache : n-Dimensionnal Adaptive as input the kernel C/C++ code of the and predictive Cache Processing Engine (PE) and generates a set Pre-fetching in a memory hierarchy is known to of optimal parameters of a generic target Data alleviate the "memory wall" paradigm but and Management Controller (DCM). A final there's a need to provide strategies more code containing both the PE and the DCM is efficient than standard mechanisms such as then the entry of the last HLS step. SPT (Stride Prediction Table). Indeed, there's Past research focused on the proof of concept a need to manage complex memory reference and benchmarking on a set of kernels. patterns as well as data-dependent ones. The Current research focuses on the parallelization proposed nD-AP Cache performs a stochastic of memory references and on the design of prediction of future references from an analysis multi-kernel processing engines. of past ones. The prediction mechanism allows to cope with irregular patterns as well as dynamic quasi-random ones. It shows to be more efficient than SPT in many situations. Past work showed the effectiveness of the approach and lead to hardware demonstrators of the nD-AP Cache. Current work focusses on the auto-adaptativity and self tuning of the prediction mechanism in order to precisely set the amount of prefetched data and determine the prefetching distance. The adaptativity is performed according to some dynamically measured characteristic of the fetch sequence as well as the main Figure 1: Reconfigurable MPSoC architecture template

TIMA Annual Report 2014 (SLS) 53 Improving reconfigurable system We have built a open-source tool, called productivity AUGH (Autonomous and User-Guided High- level synthesis). Experiments conducted on To provide better computing efficiency, in several applications show that our terms of execution time, power consumption methodology converges rapidly towards a and area in a given technology, MPSoC satisfying solution and scales even to complex architectures often integrate application- designs. specific processors (IP). The nature and number of these dedicated hardware The second challenge states in programming components are limited and have to be set up reconfigurable MPSoC. Writing applications on at design time. The reconfigurable computing these architectures is laborious, poorly paradigm gives the opportunity to a virtually portable and hardly scalable to multi-user infinite hardware component pool. and/or multi-FPGA systems, mainly because of A reconfigurable MPSoC architecture, as a mixture of application code (software and illustrated in Figure 1, is based on hardware components) and flexibility homogeneous fabric of cells (chunk of management code. hardware resources, which can be dynamically In order to abstract the complexity for user and reconfigured to host a hardware component thus to ease the integration process in a while the rest of system is still running and software-centric application, we have proposed computing), reconfiguration controllers (Rctrl an light-weight and platform-independent manages the relocation of a hardware Operating System (DNA-OS) extension to component from its description in memory to handle hardware components (communication, the configuration of a cell) and CPUs. Thus, by synchronization and reconfiguration). To time-multiplexing the reconfigurable cells, a enhance portability of reconfiguration reconfigurable MPSoC can tend towards better management procedure, we have also performance that heterogeneous one, while proposed an abstraction layer, called preserving flexibility. Hardware Component Manager (HCM), which In spite of their tremendous potential, clearly separates the allocation of a hardware reconfigurable MPSoCs still fail to convince components from the control of a application programmers. Their design reconfiguration procedure. An hardware methods and tools offer a poor productivity implementation of the HCM was used in the (time required to arrive to a solution), proposed OS extension. compared to multi-CPU or GPU solutions, To compare to integration on other MPSoC which benefit from standard programming platform, we have developed and used the models and better design automation tools. HeRA framework. This framework can abstract Therefore, we have tackled several locks on implementation and execution methods of a the productivity of reconfigurable MPSoC. component and currently supports several OS (linux, DNA-OS) and platforms (multi-CPU, The first lock tackled is the generation of GPU, reconfigurable MPSoC). hardware component. Currently, High-Level Synthesis (HLS) tools are used to improve References designer productivity on reconfigurable fabric [1] Y. Xu, O. Muller, P.H. Horrein, F. Pétrot, HCM: (FPGA). However, the existing tools are far An abstraction layer for seamless from being productive enough: long time to programming of DPR FPGA, Field solution, manual iterations in the design flow to Programmable Logic and Applications (FPL 2012), Aug. 2012, Oslo. obtain a hardware component fitting in a cell [2] Prost-Boucle, O. Muller, F. Rousseau, A Fast (hardware design skills required). and Stand-alone HLS Methodology for To bring the HLS much closer to the Hardware Accelerator Generation Under compilation task for CPUs, we have proposed Resource Constraints, High-Performance and a fast, scalable and standalone methodology, Embedded Architectures and Compilers that works under strict resource (and (HiPEAC 2013), HLS4HPC workshop, jan. frequency) constraints and produces one 2013, Berlin unique solution.

54 TIMA Annual Report 2014 (SLS)

Embedded and low-level software generation

Key-words: Embedded software, device driver, MPSoC, Multi-tile systems, task migration

Members : F. Rousseau, F. Pétrot, N. Fournel, A. Elantably, C. Deschamps, E. Ripert

Cooperations: STMicroelectronics, Magillem Data Service, INFN Roma, CEA LETI

Contracts: SoftSoC (FUI), EURETILE (FP7),

However, sharing the device driver development The low level software is the intermediate knowledge is complex, and writing drivers is an software layer between the hardware architecture error prone and a time consuming activity. and the software application layer. This low level Therefore, we are currently working on automatic software, also called Hardware dependent driver generation from high-level hardware and Software (HdS) includes three main parts: software descriptions. From a practical point of • The Operating System (OS), which manages view, this would simplify this task much. the sharing of resources. It is responsible for the initialization and management of the In simplest terms, device drivers are means of application tasks and communication between communication between the kernel and hardware them. It provides services such as tasks devices. In more advanced terms, a device driver scheduling, context switching, and so on. The is a specific type of software component/module relationship with the hardware is tenuous, and in the OS that converts requests from higher-level mainly through the implementation of drivers. software (e.g., the kernel or an application • The communication layer, which is responsible program) into a series of low-level input/output for managing the I/O operations and more (I/O) operations specific to a hardware device generally the interaction with the hardware (e.g., a network interface controller) abstracting components and the other subsystems. This the functionality of a physical or virtual device and communication layer implements the different managing their operation. It hides completely the communication primitives used for task details of how the device works. communication (intra or inter processor). • The HAL is a thin software layer, which totally A device driver interface can be separated into depends on the type of processor that four parts (see Figure 1). The driver requires executes the software stack, but also depends kernel services like memory allocation, and also on the hardware resources interacting with the offers services (e.g., hardware initialization) to the processor. The HAL performs the processor kernel. b) User application sends general related accesses on which the device drivers commands to the driver using exported driver are based to implement the interface for the interface, while c) libraries provide the driver with communication with the device. some services like string manipulation. d) Lastly, the hardware abstraction layer (HAL) To contribute in this field, we have developed a accommodates hardware access methods, which small embedded operating system, called DNA- are used by the driver. OS, that has been ported on top of a few typical processors (MIPS, ARM, SPARC, Microblaze,

 NIOS, x86, …). This OS serves as basic component for a software design flow able to

  
  
 produce binary code for all computing units of a  multiprocessor architecture. The design approach     is component-based, static, and very low cost. 
    This design approach was a main contribution few   
 years ago. This allows to specifically tailoring the  OS regarding the services required by an 
  
 application, which corresponds to the constraints 


 
 
 that an integrated system has to meet. It is the basic for all the following research activities. 

Figure 1: Device driver interface Device driver generation One of the most elementary pieces of information In terms of communication layer, a set of platform about a device and the driver that manages it, is specific device drivers has been developed. what function the device accomplishes. Different

TIMA Annual Report 2014 (SLS) 55 devices carry out different tasks and need process state plus its address space from the information at different semantic level to work out. source core (referred to also as home or host There are devices that play sound samples, node) to the destination one (referred to also as devices that read and write data on a magnetic destination node). Its significant cost is coming disk, and still other devices that display graphics mainly from the process of transferring the to a video screen, and so on. Thus, because of address space. The address space is usually the various and interrelated sources of composed of the task stack and heap. However, information, driver generation is intrinsically this is not the only task attribute to be transferred. complex. The whole task state including the address space and the CPU registers, open files and ports, have A method, called Me3D, has been investigated to to be transferred to the destination core to be help in device driver generation. Step by step, eventually resumed/ restarted properly. information is requested from the designers (IP- XACT model of the platform or device, behavior of As a solution, we consider task replication: It the driver, …) for the final generation. A set of consists in having replicas of tasks in the system. tools is also available, called ADDAX When a migration is needed, the task is (http://timasls.imag.fr/www/research/addax/addax- suspended in its source processor and resumed setup/). Method and tools are today related to in the destination processor after the transfer of DNA-OS, but will be extended to other OS. the process state. The destinations for migrating tasks are determined statically prior to compilation In the context of multi-tile systems connected by and linking. This enables the system level design NoC, we have provided an original method with process more open for optimum locations of the use of a formalization of communication paths migrating tasks. Although the system level to generate drivers. Usually, the way data designer must be aware of the sources and transfers occur in this architecture is predefined corresponding possible destinations of all migrate- and implicit. Due to the multiple levels of able tasks, our solution has been designed so that hierarchies, describing explicitly in the architecture there is no involvement from the programmer side model the different stages of data transfers whatsoever regarding the migration process. Our becomes a necessity. A simple way to do it is to solution is implemented as a layer between the enumerate all communication paths between two operating system and the application. It has been processing units, and for each communication chosen to utilize OS application software interface path all devices involved in the transfer. APIs without modifying the operating system itself and that’s to make the solution capable of being Writing one driver per communication path is not plugged over any operating system. conceivable anymore due to the large number of available communication paths in a complex One of the issues of task migration is the architecture. One solution is to develop generic inconsistency in the communication arising from driver templates that implement several the change of the location where the task is communication paths. For each communication supposed to be running in. This consequently, path, a correct template is selected and requires informing all the adjacent tasks to the specialized to efficiently handle the hardware migrating one in the task graph with its new resources. Thus, we obtain a multi-device driver location after migration to keep sending and that is then compiled and linked with the operating receiving tokens correctly. Not only location system and application code to provide the binary update is important to keep the communication code for each processing unit. We provide a consistent, but also any remaining unprocessed communication synthesis process with a good tokens left in channels FIFOs have to be simplicity/control trade-off. forwarded/re-sent to the right corresponding FIFOs after migration to ensure consistent Task migration in non-SMP architecture completion.

Task migration is a well know feature in the References context of SMP (Symmetrical Multi-Processor) [1] H. Chen, G. Godet-Bar, F. Rousseau, F. Petrot, architecture. This becomes very challenging when Me3D : A Model-driven Methodology expediting dealing with non-SMP architecture, and we are Embedded Device Driver Development, developing method and tool to provide such a Symposium on Rapid System Prototyping (IEEE RSP 2011), Mai 2011, Karlshrue, Germany. feature. The main goal is to provide an answer to [2] Chagoya-Garzon, F. Rousseau, F. Pétrot, Multi- load balancing, thermal and fault tolerance Device Driver Synthesis Flow for Heterogeneous awareness of processors in MPSoC. Hierarchical Systems, DSD Conference, Sept 2012, pp. 389 – 396, Izmir, Turkey. The main idea of task migration is the transfer of a 56 TIMA Annual Report 2014 (SLS)

Three-Dimensional Networks-on-Chip

Key-words: 3D-IC, Network-on-chip

Members : F. Pétrot, A. Sheibanyrad, S. Foroutan, M. Bahmani, J. Saade, H. Bel-Hadj-Amor, N. Bentini

Cooperations: ST-Microelectronics, CEA-LETI

Contract: 3DIM3 (Catrene)

As the end of scaling CMOS transistors comes in design-time, from the (flexible) elevator- sight, the 3D-Integration may come to the rescue assignment that can be reconfigured later of the industry to allow for a continuing according to application requirements. The main exponential growth of integration during the 2015- advantages of this decoupling are: 1) The elevator 2025 periods. Moreover the incorporation of the number/location decision can remain a completely third dimension in the design of the NoCs allows hardware-dependent and application-independent the exploitation of three dimensional topologies problem. 2) Without changing available hardware which result in a major improvement in network resource, we can optimize the NoC performance performance. for given application requirements, just by Through-Silicon-Via (TSV) has the potential to configuring elevator assignment. 3) When a offer a great vertical interconnect density and vertical link fails (followed by a TSV failure), we features an extremely small inter-wafer distance. can reconfigure the assignment to avoid routing Although 3D-Integration using TSVs introduces a through the failure link by maintaining the optimal whole new set of application possibilities, it also performance. Different elevator-assignments for introduces new architecture level design issues. the same number/location of elevators (the same Fabricating a 3D integrated circuit using TSV topology), can change the network performances. technology involves several extra and costly For solving the assignment optimization problem, manufacturing steps, and each extra step adds a we have proposed a heuristic algorithm based on risk for defects, resulting in potential fabrication tabu search. To do this we have (1) shown the yield reduction. Additionally, the TSV interconnect relation between link buffer utilization, network pitch (mainly due to its pads) imposes a larger performance (in term of network saturation area overhead than the corresponding horizontal threshold), and elevator assignment, (2) defined a wires and a TSV consumes all layers in the upper novel quantitative metric to determine which die in addition to the top layer in the lower die. assignment leads to a better network To deal with this cost-efficiency trade-off, we had performance, and (3) proposed a straightforward suggested reducing the number of vertical links to approach to choose the neighborhood solution in be exploited by the network. However despite the each step of search. undeniable benefits of reducing the number of We use the link buffer utilization to quantify the TSVs, removing vertical links has a degrading link-level local traffic. The link with the highest impact on the NoC performance. Our major buffer utilization is the bottleneck of the network. research efforts during 2013 focused on how we Buffer utilization is a strong weight metric for our can optimally assign elevators (vertical links) to optimization purpose as it reflects in the same nodes of a Vertically Partially Connected 3D- time both link (flit) rate and link congestion. When NoCs. packets are in contention they become stalled and their flits are accumulated in link buffers. If the flit Assignment of Vertical Links (Elevators) to rate is high it means more flits are accumulating Nodes of Vertically-Partially-Connected NoCs and so the buffer utilization becomes larger. While the number and location of vertical links are Different elevator assignments lead the global determined at design-time according to the traffic routed via different paths, which hardware constraints, the major remaining consequently lead to different local traffic challenge is to assign to each router it’s up and distributions, which finally lead to different down elevators according to target application. performance results. Since there are fewer This consists of assigning to each router at elevators than nodes (routers) on each die, configuration-time, the address of a router on the several nodes are assigned to a single elevator. same die that possesses a vertical link to the An inappropriate assignment may thus result in upper die, as the up-elevator, and the address of creation of local hotspots which significantly a router on the same die that possesses a vertical deteriorates the global performance. In order to link to the bottom die, as the down-elevator. We avoid an assignment leading to such an decouple the (fixed) hardware decision of number imbalanced and sharp traffic distribution, our and location of elevators that must be solved at algorithm detects the bottleneck. Then, by TIMA Annual Report 2014 (SLS) 57 proposing new assignments it tries other local When the maximum number of tabu assignments traffic distributions and verifies if the bottleneck is evolves from 50 to 100, 500, 1000, 5000, 10000, appeased and thus the saturation threshold can or 100000, the algorithm has more time to explore be improved. If not, then the algorithm checks the solution-space and find better solutions. whether the second bottleneck (i.e. the link with However, as the algorithm converges very rapidly the second highest buffer utilization) can be to the near optimal it can find, a much higher improved, and so on to the least congested link number of attempts does not necessarily provide (i.e. the link with lowest buffer utilization). So for a much better solution. The results for the cases any given global (i.e. end-to-end) traffic of 5000, 10000, and 100000 (or more precisely distribution, the algorithm searches for an elevator 21472 as after that the algorithm cannot progress assignment that leads to a smoother local traffic anymore) are almost the same. distribution and thus optimizes the NoC saturation threshold. Since the solution-space is huge, we have to stop the algorithm after a maximum number of attempts (i.e. when the number of tabu assignments reaches a maximum). However, depending on the initial solution, the algorithm may converge to a local optimal solution and thus cannot progress anymore, before achieving the intended maximum number of attempts. We cannot claim that the final solution found by the algorithm, is the absolute optimal one. Local search approaches (and specifically tabu search according to [36]) can obtain near optimal Figure 2. Results obtained for 50, 100, 500, 1000, solutions. These solutions depend on the initial 5000, 10000, and 100000 attempts assignment. Figure 1. shows how significantly the final In order to give an idea about the optimization assignments obtained after applying the proposed complexity, Table 1 compares the algorithm run algorithm to a set of arbitrary assignments time under Linux on a PC with Intel Xeon W3530 improve the network performance. The figure at 2.8 GHz and with 12 GB of RAM, for different shows an improvement of about 100% in maximum number of attempts, and for a random saturation threshold for each configuration. and a greedy nearest initial assignments. The optimum solution with greedy initial assignment is obtained more than 9 hours sooner than that of random assignment. Table 1. The algorithm run times

Random One of the Nearest Tabu Hop Run Run Hop Tabu Number Count Time Time Count Number 0 7.56 - - 5.78 0 50 7.52 35s 35s 5.98 50 100 7.50 64s 41s 6.11 100 500 7.44 263s 295s 6.30 500 Figure 1. The optimized solutions for the elevator ratio 1000 7.39 916s 617s 6.34 1000 of 80, 50, and 20% 5000 7.23 6662s 6104s 6.37 5000 Our experiments were based on a 5x5x5 mesh- 10000 10000 7.13 16698s 13449s 6.37 based 3D-NoC. In such a relatively big network 8728 with 125 nodes (25 in each die) if, for example, 100000 100000 7.08 48127s 13449s 6.37 the elevator ratio is 50%, the assignment solution- 21472 8728 space is averagely 12.562.5 = 3.6e+68 that is impossible to cover. However, as shown in Figure 2 (which demonstrates the impact of number of References attempts on the result of the algorithm), even in [1] Sahar Foroutan, Abbas Sheibanyrad, Frédéric such a huge solution-space only after 50 attempts Pétrot, Assignment of Vertical Links to Routers in our algorithm provides a much better solution, Vertically-Partially-Connected 3D-NoCs, IEEE compared to the initial assignment (the saturation Transactions on CAD (accepted with a major threshold improves more than 40%). revision) 58 TIMA Annual Report 2014 (SLS)

Methods and tools for computer aided design

Key-words: simulation, debug, profiling

Members: F. Pétrot, N. Fournel, D. Hedde, M. -M. Hamayun, L. Michel, S. Lagraa, M. Gligor, M. Cunha, Th. Ducroux

Cooperations: STMicroelectronics, Magillem Data Service, Kalray

Contracts: SoCTrace (BGLE), Acose (BGLE), COMCAS (CATRENE), Kalray

The CAD activities mainly covers the following All these level of abstractions share the same themes: Modeling, Simulation and Debug and issue in native simulation, the address spaces. Profiling. Indeed, there are two address spaces merged in one, the one from the target system and the one Fast simulation strategies from the simulator. Some solutions have been proposed in the recent Simulation of large scale integrated, potentially years to overcome this issue, but they fix some heterogeneous, multiprocessor platforms is a long development constraints on the application and lasting theme of the SLS group. This work is of the operating system running on the target system. primary necessity as the number of processors in Among these solutions one propose to use the integrated circuits is raising, and therefore the simulator address space during the application by simulation times are increasing constantly. As inserting some translations at simulation start. predicted by ITRS the evolution of integrated system architecture tends to embed several hundreds of processors, turning multi processors systems into many-core systems. These systems are mainly based on VLIW processors architectures (e.g. Tilera TileGx72 or Kalray MPPA256) to reduce the complexity of the processors to integrate a larger number of them. On top of that, these many-core systems rely on a Network-On-Chip based interconnect. As a result, the execution of the software on Instruction Set Simulators during simulation (making the processor the ultimate hardware/software interface) is not viable anymore. Several innovative approaches have been defined and demonstrated

For several years, the so called native simulation approach has been seen as the implementation of the low level software functions of an Operating System using a simulator API. This has become specifically popular with the wide dissemination of Our main contribution in native simulation has SystemC, as it provides many API functions been to define an approach that tackles this similar to the ones of an OS. The idea is thus to problem of address spaces by using widely spread model the system as a stack of layers, and each hardware solution. Desktop computer processors upper layer can rely on the functions provided by embed hardware to assist virtualization and the lower level layers. If the abstraction is coarse, protect the host operating system from the guest then several layers can be merged to provide at a operating system. This hardware allows to make a low execution cost the functions (usually realized fresh complete address space for the guest on top of an operating system or a high level operating system and translate it to the host hardware abstraction such as SystemC TLM), if address space transparently. The guest operating the abstraction is fine grain, then the “real” system is then unaware of the fact that it is running realization (some OS code for example) is in a virtual environment. By placing the target provided, and the hardware can be described system as the guest operating system, the more accurately at the cycle level. problem of conflicting address spaces raised earlier is solved.

TIMA Annual Report 2014 (SLS) 59 As far as processor simulation is concerned, the analysis is trace based, a correct execution can use of dynamic recompilation techniques is very still be detected as leading to a potential race promising from a speed perspective. The Dynamic condition. The detection algorithm is exponential, Binary Translation of VLIW architectures on scalar but behaves well in practice if the processes architectures is still an open ground. Our synchronize often, as these synchronizations are contribution in this topic is to propose a solution to indeed limiting the number of events to be tackle the issues. Among these issues, we can considered in parallel. Figure 1 illustrates the cite the parallel execution on instructions, intervals that can be built from a trace. expressed in the binary code for the VLIW architecture while sequentially is the base of scalar Virtual prototyping allows releasing constraints on processors code. The write back of registers is the what can be verified today. Indeed, the key of this issue. We proposed a solution based consistency check on actual parallel machines on a single assignment register representation in relies on the fact that, among others, each write the translation which allows tackling this issue and must be done with a different value in order to be other issues raised by these architectures. able to know what process or processor produced it. NP completeness of these checks can possibly Debug and Profiling (it is still to be proved) be made polynomial by The emergence of massively parallel embedded adding information that the virtual prototype may systems due to the arrival of the multi- and many- be able to produce. Up to now, we have been core integrated systems opened new issues about working on sequential consistency, but we plan to debugging and profiling applications. Debugging extend the approach to other memory consistency and profiling in that context cannot be considered models. as usual debug, i.e. launching a debug process per actual process to follow the flow of As far as profiling is concerned, the mass of computation. As there may be hundreds of information collected using traces makes difficult processes cooperating, the real problem is to the identification of weak points. A successful identify wrong behaviors like wrong sharing, race collaboration with colleagues from the computer conditions, inappropriate understanding of the sciences lab of Grenoble to apply data-mining consistency issues or bad memory accesses techniques to automatically identify repeated or sequences due to bad memory placement. costly patterns in the traces. Interesting results have been obtained on both performance and power profiling experiments, for example with the automatic detection of high latencies of floating point computation function.

To summarize, we apply here existing data-mining strategies to our traces to detect the occurrence of events that occur either very often or very rarely, Figure 1: Interleavings of memory accesses, the and then have the designer analyze himself the black dot represent the synchronizations identified points. We believe that due to the specific structure of the traces, more efficient Our proposition in this field is based on simulation algorithms than the general purpose ones can be and execution traces. This infrastructure has the proposed. advantage to be be non-intrusive, i.e. not modifying timing nor behavior of the traced models, and allow to collect information not References available in other cases. [1] H. Shen, M.M Hamayun, F. Pétrot, Native Simulation of MPSoC Using Hardware-Assisted Virtualization, IEEE As far as identifying wrong behavior like problem Transactions on Computer-Aided Design of Integrated of consistency or race conditions is concerned, a Circuits and Systems, Vol 31, No.7, pp 1074 - 1087 formal approach would be ideal, but unfortunately [2] L. Michel, N Fournel, F. Pétrot, Fast simulation of it is clearly not possible to handle actual programs systems embedding VLIW processors. CODES+ISSS with these techniques. So we focus on a more 2012, pp 143-150 practical approach in which we analyze execution [3] S. Lagraa, A. Termier, F. Pétrot, Automatic traces describing ordered communications congestion detection in MPSoC programs using data mining on simulation traces. RSP 2012, pp 64-70 operations per processor.

For race condition analysis, these operations are merged per process from the partial orders of the traces. Despite the use of these partial orders, the

60 TIMA Annual Report 2014 (SLS)

Theme 3 / Design and verification of Systems on a chip architectures VDS Group: Verification

Themes

Test and verification methods for mixed or digital IP blocks IP blocks synthesis from logic-temporal specifications Test and verification methods for hardware/software on-chip systems Verification methods for Networks on Chip Formal methods for robustness analysis

Expertise

Scientific Simulation and description semantics, systems modeling, requirements formalization, temporal logics, automatic proofs

Fields of expertise Correctness verification at various levels of the design flow, robustness analysis and formal methods

Know-how Formal specification of functional and robustness requirements, formal verification (mechanized proofs), assertion-based design, symbolic simulation

Industrial transfer Transfer of HORUS technology in EDA tools for mixed systems by Dolphin Integration

Research keywords

Specification and verification of complex systems, EDA (Electronic Design Automation) assertion-based verification, design flow, correct-by-construction design

Contact

Laurence PIERRE UJF Professor – TIMA (+33) 476 57 49 92 [email protected]

TIMA Annual Report 2014 (VDS) 61

62 TIMA Annual Report 2014 (VDS) Verification of Hardware/Software Systems on Chip

Key-words: Verification of SoC, Assertion-Based Verification (ABV), SystemC TLM

Members: L.Pierre, Z.Bel Hadj Amor, M.Chabot, D.Borrione

Debugging today’s hardware/software embedded The next step of the design flow is to provide the systems is a complex process. We have previously RTL (Register Transfer Level) implementation of described our tool, ISIS [1], that enables the this abstract model, by means of HLS (High Level runtime Assertion-Based Verification (ABV) of Synthesis) tools and/or by manual refinements. An temporal requirements for high-level (SystemC assertion refinement process conveys assertions TLM) models of such systems, by the automatic through this ESL-to-RTL refinement procedure. It instrumentation of SystemC virtual platforms with gives designers the possibility to reverify, after assertion checkers. This verification infrastructure synthesis, the exact semantical counterpart of the has been enhanced with two major features. initial System-level requirements. The first one offers the possibility to customize and to optimize the verification process, and to get 0#J86$#7#'?"( !"#$%&"'"()*+"(,%(""&+ more easily analyzable results. The flexibility of the original version of ISIS was limited, it was only -./01&'+/&23%)"2)+ possible to select, at the SystemC compile time, .,.,( the assertion checkers to be attached to the E#$6D):%&'($#F&$?"( Timed !""#$%&'( design. It now enables to customize at runtime and Proc. DMAs )*#)+#$"( MS MS to optimize the process, and also to get concise ,6789:%&'( AHB

S S S void handle_interrupt! 23./)+45'6)7$ (void* context, ! alt_u32 id){! volatile int* ! edge_capture_ptr = ! information about checker's activations, thus static alt_u8 data_a;! static alt_u8 reg_rx;! reg_rx,-(=! Mem. Mem. ReadSPI_0(REG_RX_INT ! data_a=! DSP ReadSPI_0(REG_RX_DAT ! improving the debugging task [2][3]. DATA CODE cpt++;! @:?:A:"#(&B( ANI DSI The second additional key feature is a companion C#$6D):%&'($#"89?"( ANO DSO ,-./0+1$%&'()*+$ 4156/&"+ tool that performs a semantic refinement of the 7"8".19"&+ ;<,(=(7:'8:9(">'?*#"6"( !,,/01.23,(0/4.3/5/31( temporal assertions, such that analogous G&"?H requirements can be verified before and after ESL- F$&)#""6'I( E#$6D):%&'($#F&$?"( Timed !""#$%&'( to-RTL synthesis [4]. Proc. DMAs )*#)+#$"( void handle_interrupt! (void* context, ! alt_u32 id){! MS volatile intMS* ! edge_capture_ptr = ! static alt_u8 data_a;! ,6789:%&'( AHB static alt_u8 reg_rx;! reg_rx,-(=! ReadSPI_0(REG_RX_INT ! data_a=! S S ReadSPI_0(REG_RX_DAT ! S 1. ABV toolchain cpt++;! Mem. Mem. DSP DATA CODE

ANI DSI These improvements result in a toolchain that @:?:A:"#(&B( ANO DSO seamlessly embeds runtime verification in the C#$6D):%&'($#"89?"( !"#$%&'()*+$ design flow, as pictured by Fig.1. Figure 1. ABV infrastructure in the SoC design flow While the initial system requirements can be used by the platform architect to propose a SystemC virtual platform as the outcome of architecture Let us discuss these improvements in more details. exploration and HW/SW partitioning, their PSL formalization is transformed by ISIS into assertion 2. Improvements of the verification process checkers that instrument this platform. At that point of the design flow, the "processor" representation in In addition to enabling the optional runtime the SystemC model is often a simple traffic instantiation of the assertion checkers (w.r.t generator used to perform preliminary evaluations choices given in a configuration file - this file is of the transactional behaviour of the platform. The generated with default values that enable all the checkers can be used to report first conclusions assertions and that can be toggled to "disable"), about the integration of the components (i.e., the ISIS now also allows to take into account the fact functional correctness of the interactions between that requirements are usually correlated (not by them), and to confirm the architecture exploration purely logical relations, but by conceptual relations choices. determined by the designer). For example, if a Once the hardware platform is considered property that states that input data are not lost in a adequate, a more realistic processor model (ISS) image processing platform is violated, checking can be integrated, and software development can that these data are not lost within the platform start. The software developer can use the monitors becomes useless. to check the functional correctness of the To that goal, a Verification Manager component hardware/software interactions. To that goal, he has been introduced in the observation model. By can customize the checkers activity at runtime. It is means of a configuration file, the user specifies also possible to configure the simulation to take relations of the form Ai R Aj which express that, if into account relationships between assertions to assertion Ai experiences violations, then checking dynamically disable/enable monitors, thus clarifying assertion Aj becomes worthless. The Manager can and optimizing the verification. Verification results be configured such that, when it detects that the are provided both as textual outputs and as concise monitor of Ai reports violations, either it only information stored in a database to be analyzed by disables Ai immediately, or it also disables the post-processing tools. monitor of Aj. This has two main advantages: TIMA Annual Report 2014 (VDS) 63 simulation traces only include the most relevant related to the “write” TLM function specifies that information provided by the checkers, thus there is a one-cycle delay between sending the simplifying the interpretation of the verification control and address and sending data). results and improving debugging; the CPU time Given a TLM assertion, the tool recognizes where overhead induced by the checkers may be some of the transformation rules can be applied minimized. (using unification) and applies them, see Fig.3. The To ease the analysis of the verification results, in implementation is such that minimal user guidance addition to textual reports, verification results are is required: the designer has to disclose the actual now stored in a database. To achieve this, the protocols and timing that are introduced in the monitors have been extended with a member which TLM-to-RTL design flow, but we provide an easy- is a vector of database entries. During a simulation, to-use procedure to guide this process. the monitor stores here the information about every assertion activation: start time, end time, status (pass or fail). This information is ultimately committed to the database. A post-processing tool extracts a concise and easily analyzable tabular representation of the result.

Fig. 2: Verification post-processing

Fig.2 shows how the post-processing tool displays simulation times and the results of the evaluations.

3. Assertions from TLM to RTL

For a comprehensive and seamless verification flow, analogous requirements should be verifiable before and after ESL-to-RTL hardware refinement. This requires the transformation of ESL assertions Figure 3. Refinement tool into their counterparts at the RT level. We have defined a methodology and implemented To the best of our knowledge, this tool is the first a tool that performs the automatic extraction of implementation of a refinement process that takes signal level assertions from system level into account the conversion of temporal granularity transactional requirements. Beyond simple issues to automatically generate RTL temporal assertions such as data concretization, the most salient from ESL requirements. concern is related to the modification of temporal granularity due to the introduction of actual References communication channels in place of abstract [1] http://tima.imag.fr/vds/Isis/ components. A set of PSL transformation rules has [2] M.Chabot, L.Pierre: "A Customizable Monitoring been defined. These rules address cases where an Infrastructure for Hardware/Software Embedded atomic communication action is transformed into a Systems". IFIP Int. Conference on Testing Software and given sequence of actions, and cases where a Systems (ICTSS'2014), Springer LNCS 8763. concrete communication action is expected after a [3] L.Pierre, M.Chabot: "Customization of the Runtime certain number of clock ticks. A transformation rule Verification of Hardware/Software Virtual Platforms in L àC R maps a TLM temporal expression L into ISIS". Proc. FDL'2014 (Demo). the corresponding RTL expression R, according to [4] Z.Bel Hadj Amor, L.Pierre, D.Borrione: "A Tool for the given time constraints C . The role of a constraint is Automatic TLM-to-RTL Conversion of Embedded to specify delays introduced by the actual Systems Requirements for a Seamless Verification communication protocol (for example, for a single Flow". Proc. VLSI-SoC'2014. write operation for an AHB bus, the constraint

64 TIMA Annual Report 2014 (VDS)

Automatic Compilation of Properties into Synthesizable Designs

Key-words: Correct by construction, Assertion-Based Design (ABD), PSL

Members: N.Javaheri, K.Morin-Allory, D.Borrione

Declarative specifications are now widely adopted and produces a reasonably sized RTL circuit in the context of verification: declarative properties model. Experiments and performances were about the behavior of a design (Assertions) or its reported in 2013. In 2014, new optimizations have environment (Assumptions) are checked using been performed, leading to significant impro- dynamic or static verification tools. Once refined vements in the size of the combinatorial part of the down to the register transfer level (RTL), a reactants. Original benchmarks have been complete set of assertions unambiguously specified and processed: a high-level data link characterizes how a module reacts to signals sent control (HDLC) module, a SDRAM controller, and a to it, logically and temporally. Many tools are now CRC; the results obtained show the versatility of available to compile assertions into monitors, i.e. the method. verification IP's that check the design correctness, For all the temporal operators, we have defined a either by simulation or emulation. Dependence relation Δ between its operands exp Our current project considers the direct and cond, in accordance with the trace semantics production of compliant control and of PSL. It is based on writing it under one of these communication modules from a set of two generalized expressions: ki assertions. A property is seen as the specification ∀ i ∈ [ k1, k2 ], ⎡ exp Δ cond ⎤ ω of the module to be designed, and we directly ki ∃ i ∈ [ k1, k2 ], ⎡ exp Δ cond ⎤ ω produce the synthesizable RTL design from its where ki is the first time point of the trace when assertions. For each property, we obtain a some formula F has been true exactly i times (F compliant RTL component called reactant: its depends on the temporal operator). The hardware inputs and outputs are operands of the property, it semantics of the Δ relation, of a counting function, reacts to the input values and produces output of the and quantifiers were defined as logic values so that the property holds. ∀ ∃ circuits. From there, the construction of the Previously published works are based on automata reactants is obtained by mere interconnection of and game theory. In contrast, our method is the primitive modules for the operators generalized modular: it is based on the interconnection of expression. The construction was proved correct by primitive library modules for the logical and inductive reasoning [2]. temporal operators of the property, according to its syntactic structure, a technology that we initially introduced to compile assertions into monitors (Horus). Fig.1 illustrates the construction.

&'()*+,-*./012/)'(&*345*. 8$9 &'()*+,-*. 671*!1!' 0$=0%; !"#$% 17<' :;'*1

Property P2 is always ( ( BtoS ACK 0 and StoB REQ 0 ) −> next ! ( BtoS ACK 0 ) ) ;

Fig. 1: Reactant architecture for property P2 Fig. 2: Hardware semantics for Next_e [kmin, kmax] In general, the specification has many properties, and a same variable may appear in several distinct What remains to be done is the synthesis of properties. The originality of our approach is to properties written with SEREs. A partial solution is avoid combining all the properties into one big under construction. automaton. Our method constructs the dependence between the design variables, and identifies which References properties monitor a variable, and which properties generate its value. If a variable is an output for [1] Morin-Allory K., Javaheri F.N., Borrione D., "Design Understanding with Fast Prototyping from Assertions", several reactants, these are combined with a solver Workshop on Design Automation for Understanding to produce the final design. Hardware Designs (Friday Workshop DATE'14), Dresden SyntHorus-2 is a new software tool that implements (Germany), 2014 these principles [1]. It takes as input the entity [2] Morin-Allory K., Javaheri F.N., Borrione D. (interface) declaration of the specified module and "Efficient and Correct by Construction Assertion-Based a set of properties written in the simple subset of Synthesis", to appear in IEEE Trans. on VLSI, 2015, DOI: PSL, and produces a RTL design in the 10.1109/TVLSI.2014.2386212 synthesizable subset of VHDL. SyntHorus2 compiles several dozens properties in seconds, TIMA Annual Report 2014 (VDS) 65

66 TIMA – Annual Report 2014 (VDS) Theme 4 / RMS Group Reliable Mixed-signal Systems

Themes

Mixed-signal/RF integrated devices Test and control techniques Design-for-test Diagnosis Embedded control Behavioral and statistical modeling methods CAD tools for test and control

Expertise

Scientific Test and diagnosis for mixed-signal/RF integrated devices, design-for-test, behavioral and statistical modeling, embedded control Fields of expertise Microelectronics, control, statistical modelling Know-how Test metrics estimation, machine-learning-based test, non-intrusive test and control, diagnosis, mixed-signal/RF design-for-test Industrial transfer Techniques of integrated test for analog-to-digital signal converters, CAD software for test, embedded sensors diagnostic technique

Research keywords

Design-for-test, built-in self-test, design-for-manufacturing, calibration, density estimation, machine-learning, embedded control

Contact

Salvador MIR Emmanuel SIMEU CNRS Research Director – TIMA UJF Associate Professor - TIMA (+33) 476 57 48 95 (+33) 476 57 47 25 Salvador.Mir@imag [email protected]

TIMA Annual Report 2014 (RMS) 67

68 TIMA Annual Report 2014 (RMS) ADC BIST for static linearity test

Members : G. Renaud, M. J. Barragán, S. Mir, H. Le Gall

Cooperation: STMicroelectronics

Contracts: ELESIS (ENIAC) Introduction ADC static linearity test is one of the most time consuming tasks in production testing. The static performance of an ADC is characterized in terms of its DNL and INL figures which measure the deviation of the static transfer curve of the ADC from its ideal behavior. Traditional test methods for static test are based on applying a high- linearity test stimulus and then collecting a large number of samples per code to average the noise. Figure 1. Switched-Capacitor integrator.

Previous research by our group proposed a In this work we opted for a switch-capacitor reduced code linearity test technique for ADCs implementation for the integrator, as depicted in having a repetitive structure [1]. This technique Fig. 1 (single-ended version shown for simplicity). reduces the number of required test samples to To a first-order, the integration step in this around 6% of the total number of codes in the integrator is defined by the capacitance difference ADC, reducing this way the overall test time. between Ci1 and Ci2. We propose to achieve this However, the problem of providing an accurate difference by introducing a defect at layout level in test stimulus at the input of the ADC still remains one of the capacitor plates. This way, we assure a as an open problem. In this work we are exploring very small capacitance difference but we also methodologies for adapting the technique in [1] to introduce uncertainty in the value of the step due a full BIST scheme, including stimulus generation to process variations. and response evaluation. In order to overcome this limitation we have The proposed BIST architecture is based on an proposed two techniques for compensating the integrator-based servo-loop technique. This effect of this mismatch in the measurements. technique is a standard test set-up for determining code locations in ADCs. In this structure, an Measurement correction techniques integrator feeds a test stimulus to the ADC, and a. Correction based on one code measurement then the result of the conversion is compared to a target code. If the ADC output is below this target This correction technique is aimed at correcting code, the input is raised by a fixed amount. If the the initial estimations for the code transition ADC output is equal to or above the target code, voltages obtained by the servo-loop technique by the input is lowered. This process is repeated until independently estimating the position of an the ADC input settles to a stable average value. arbitrary transition close to the full-scale of the Then, the input value can be either measured or, converter. By computing the difference between if the input source is well calibrated, computed this estimation and the initial measurement, it is from its transfer function. possible to correct the complete set of initial servo-loop measurements by linearly propagating Built-in test instruments the correction factor. The interested reader is The main challenge for moving the servo-loop referred to [2] for a detailed description of the technique to a practical on-chip implementation is technique. the strict accuracy requirements for the input It is important to notice that this technique stimulus. In order to make a significant requires a slight modification of the ramp measurement, the magnitude of the integration generator, as it is shown in Fig. 2, to be able to step should be below the LSB of the ADC, which inject a known reference voltage, V in Fig. 2, is a defiant constraint for high-resolution ADCs. a close to the converter full-scale.

TIMA Annual Report 2014 (RMS) 69

0 CF
0 2 Va
0
0 0 Real INL
2 Ci1
1 Vref
%0 1024 2048 3072 4096 V 2
1
2 out

0
2 Ci2
1 -Vref Estimated INL
%
1
2 0 1024 2048 3072 4096 #$%

0 errors

Fig. 5. Modified switched-capacitor integrator. INL estimation Fig. 2 Modified SC integrator for code correction Fig. 6. Estimated maximum INL vs real maximum INL. Servo-loop
#$%0 1024 2048 3072 4096 introducing a defect at layout level in one of the capacitor Fig 3. Estimated maximum INL vs. real maximum INL. ADC code measurement. measurements corrected based on one code measurement. Servo-loop measurements are corrected based on one Fig. 3. Generic block diagram of a classical integrator-based servo-loop for plates. This way, we assure a very small capacitance difference Fig. 8. Estimated and real INL figures for each code in the ADC. Servo-loop code measurement. measurements corrected based on one code measurement. ADC linearity test. –and hence a very small integration step– but we also introduce 3 uncertainty in the value of the step. Moreover, the mismatch 2 b. Correction based on estimating the magnitude Figure 4 on the other hand shows a scatterplot of 4 CF in the capacitors due to the fabrication process imposes a limit 1 1.2 LSB INL estimation error line

of the ramp stimulus step theReal DNL estimated versus real maximum INL for all the 3.5 to the magnitude of the step. In a practical implementation, 0 2 LSB INL estimation error line simulated test scenarios using the correction
2 Ci1
1
∈ 3 theThe defect second should introduce correction a capacitance technique difference is based that on has 0 1024 2048 3072 4096 Vref based on estimating the magnitude of the ramp to be at least as large as the mismatch between the capacitors. 3 2.5 Vout evaluating the average magnitude of the steps in
1
2 stimulus step. Results show a maximum Inthe addition, ramp givenstimulus that theprovided capacitance by the difference integrator. introduced This 2 2 estimation1 error of about 1 LSB, although 90% of by the defect cannot be controlled precisely, this uncertainty 1.5 estimation is then used to correct the initial servo- 0
2 Ci2
1 theEstimated DNL simulated test scenarios are below the 0.7

has to be compensated to provide meaningful measurements. Estimated INL errors (LSB) -V loop measurements. Again, the interested reader 1 ref LSB
∈ 0 estimation1024 error line.2048 In this particular3072 case,4096 The servo-loop test set-up described in the previous subsec- #$%
1
2 is referred to [2] for a detailed analysis of the the nominal ramp step was reduced to 1/10 of 0.5 tion relies on an external high-precision voltmeter to measure 0.2 LSB INL estimation error line technique. 0 LSB0 by reducing the input reference voltage. 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

the location of each code transition in the ADC once the errors Real INL errors (LSB)

Fig. 4. Switched-Capacitor integrator. integratorResults output stabilizes. However, moving this voltmeter DNL estimation
#$%30 1024 2048 3072 4096 Fig.test 9. techniques Estimated asmaximum a full-BIST. INL Future vs real work maximum in this INL. line Servo-loop will be on-chip for a full-BIST solution is a challenging task. One ADC code this target code, the input is raised by a fixed amount. If the measurementsdirected to corrected implement based an on estimatingintegrated the demonstrator integration step. including possibilityWe have for modeled implementation the proposed is to integrate servo an-loop additional test 2.5 ADC output is equal or above the target code, the input is approaches and we have conducted behavioral Fig. 7. Estimated and real1 DNL LSB INL figures estimation for error each line code in the ADC. Servo-loop precisionthe reduced is not code enough technique for an in accurate the servo-loop production scheme test, but for ADC to monitor the integrator output voltage. This ADC has measurements corrected based on one code measurement. lowered. This process is repeated until the ADC input settles 2 tosimulations have a higher in resolution MATLAB. than The the ADC ADC under under test test, has but it precisioncharacterizing can be an improved actual ADC. by reducing the integration step. to a stable average value. Then, the ADC input value can be been modeled as a 2V-FS, 12- bit converter with A. Correction based on one code measurement An efficient way of achieving this is to reduce the DC input can be much slower, which enables efficient implementations. 1.5 ACKNOWLEDGEMENTS either measured or, if the input source (i. e. the integrator) is linearity errors up to 2 LSBs. A uniform random In order to evaluate the robustness of the proposed correc- reference for the integrator. Figure 10 shows the scatterplot This approach would be similar to the test strategy proposed in This work has been carried out in the framework of the well calibrated, computed from the integrator transfer function noise was added to each transition to model the tion method,1 a random uncertainty of 1.5 LSBs has been added of maximum estimated INL versus maximum real INL for an [16], based on using an extra ADC for static testing. However, Estimated INL errors (LSB) European project ENIAC ELESIS. to estimate the location of the target code threshold voltage. to the value of the reference Va. Figure 6 shows a scatterplot of integrating step of 1/10 LSB. Achieving this integrator step thisbehavior additional of ADC a demands practical further ADC. hardware Concerning resources, the and 0.5 In practice, the main challenge to move the servo-loop 0.2 LSB INL estimation error line requires additional hardware to generate an input reference at it shouldintegrator, also bethe tested. integration step has been set to an the estimated versus real maximum INL for all the simulated REFERENCES technique to an on-chip implementation is the strict accuracy test scenarios.0 As it can be seen in the figure, results show a FS/2, but the proposed method does not require a precise idealInstead value of that, of 1/5 we proposeof the converter to measure ideal the widthLSB. ofSte eachp 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 [1] F. Poehl, F. Demmerle, J. Alt, and H. Obermeir, “Production test requirements for the input stimulus. First, the BIST circuitry Real INL errors (LSB) reference, which relaxes the implementation. Results show a codeerrors in the due ADC to ascapacitor a function mismatch of the integration and kT/C step noise defined maximum estimation error around 1 LSB. challenges for highly integrated mobile phone SOCs: A case study,” should be simple in order to reduce the area/power overhead. Figures 7 and 8, on the other hand, show the real and maximumin Test Symposiumestimation (ETS), error 2010 of about15th IEEE 1 LSB, European although, 24-28 May 90% 2010, of bywere the integrator. included Providing in the model. that we Capacitor can devise measurement mismatch Fig.Fig. 10. 4. EstimatedEstimated maximum maximum INL vs INL real maximumvs. real INL.maximum Servo-loop INL. mea- Secondly, in order to make a correct measurement, the mag- estimatedsurements correctedDNL and basedINL on estimating, respectively, the integration for all step the (ideal codes step=1/10 in the simulatedpp. 17–22. test scenarios are below the 0.7 LSB estimation strategieshas been to estimate modeled the as integration a random step deviation within of a giventhe Servo-loop measurements are corrected based on [2] A. Laraba, H. Stratigopoulos, S. Mir, H. Naudet, and G. Bret, “Reduced nitude of the integration step should be below the LSB of theLSB). converter for a particular test scenario, together with the error line. Figures 11 and 12 show the real and estimated DNL confidenceintegration margin, step wewith would a standard be able deviation to provide of estimations 0.3%. estimating the magnitude of the ramp stimulus step. code linearity testing of pipeline adcs in the presence of noise,” in VLSI the ADC under test, while the linearity of the resulting ramp estimation error. The linear nature of this correction method and INLTest, Symposium respectively, (VTS), for 2013 all IEEE the 31st codes, April in 29 the 2013-May converter 2 2013, for pp. a of DNL and INL from these measurements. In the following should be higher than the linearity of the ADC. is made evident in the INL estimation error plot. Interestingly, particular1–6. test scenario, together with the estimation error. In sections,The two we presentpresented two differentcorrection strategies techniques for this for purpose. the Future work [3] S. Goyal, A. Chatterjee, M. Atia, H. Iglehart, C. Y. Chen, B. Shenouda, servo-loop measurements were implemented and the estimation error is approximately bounded in the range this caseN. Khouzam, our measurements and H. Haggag, are within “Testtime a 0 reduction.1 LSB uncertainty, of successive B. Practical on-chip implementation The first one is aimed at correcting the estimated linearity 3 ± simulated. For each simulation, 800 test scenarios [ Currently0.2LSB, 0 .2 weLSB are]. This working0.2 LSB on uncertainty the design is a physical of an as itapproximation could be expected register a/d due converter to the natureby selective of the code stepwise measurement,” test values using a single independent voltage measurement of one
2 ± Test Conference, 2005. Proceedings. ITC 2005. IEEE International In this work we opted for a simple switched-capacitor limitintegrated to our measurements, prototype given of thatthe thedescribed input ramp stimulus ramp stimulus.in , consisting of randomly generated pairs 1 8-8 Nov. 2005, pp. 8 pp.–225.

code transition. The second one is targeted at estimating an Real DNL implementation for the integrator, as depicted in Fig. 4 (single- ADC/integrator are tested. The servo-loop has isgenerator defined0 in discrete in ST 1/5 65nm LSB steps. CMOS technology to [4] J.-F. Lin, S.-J. Chang, T.-C. Kung, H.-W. Ting, and C.-H. Huang, ended version shown for simplicity). To a first-order, the average value of the magnitude of the integrator step. “Transition-Code BasedV. Linearity C ONCLUSIONS Test Method for Pipelined ADCs With been set to measure each code 100 times to validate
∈0 the functionality1024 2048 and performance3072 of 4096 the 1) Correction based on one code measurement: Due to Digital Error Correction,” Very Large Scale Integration (VLSI) Systems, B. Correction3 based on estimating the magnitude of the ramp The presented servo-loop measurement strategy together integration step in this integrator is defined by the capacitance reduce the effect of noise on the estimated proposed test instrument. IEEE Transactions on the cumulative nature of the INL, as defined in (5), small stimulus step , vol. 19, no. 12, pp. 2158–2169, Dec. 2011. difference between Ci1 and Ci2 as number of steps per code. 2 with[5] E. the Peralias, proposed A. Gines, correction and A. techniques Rueda, “INL represent Systematic Reduced-Testa low-cost errors in the estimation of the code widths will accumulate 1 alternativeTechnique for for built-in Pipeline static ADCs,” test in ofTest ADCs. Symposium Behavioral (ETS), 2014 simula- 19th Ci1 Ci2 Figure 9 shows a scatterplot of the estimated versus real and lead to large errors in the INL for the codes at the higher 0 IEEE European, 2014. Vout(n)=Vout(n 1) +
Vref (6) Figure 3 shows a scatterplot of the estimated maximumReferencesEstimated DNL INL for all the simulated test scenarios. As it can tions show the feasibility of our proposal, and an accuracy of
CF [6] “IEEE Standard for Terminology and Test Methods for Analog-To- end of the ADC characteristic. Let us denote as t˜ the set [1] A.
∈ Laraba, H.-G. Stratigopoulos, S. Mir, H. Naudet versus real maximum INL for all the simulatedk test be seen0 in the figure,1024 results2048 show a maximum3072 estimation4096 1 LSBDigital in Converters,” the predictionIEEE Std of 1241-2000INL has, been 2001. demonstrated. { } and #$∈G. Bret. Reduced code linearity testing of pipeline ∈ where Vout(n) is the output voltage at instant t = nTck, ofscenarios uncorrected using code the transitions correction derived based from on the one servo-loop code error of about 2 LSBs, although 93% of the simulated test [7]The M. presented Renovell, F.technique Azais, S. Bernard, is also and a Y. promising Bertrand, “Hardware low-cost resource can- n ADCs in the presence of noise. IEEE VLSI Test minimization for histogram-based adc bist,” in VLSI Test Symposium, and Tck is the clock period in the integrator. We propose to measurements for all codes (k [1, 2 1]). didate to implement recently presented reduced code linearity measurement. As it can be seen in the figure, scenarios0 yield an estimation error below 1.2 LSBs. This 2000. Proceedings. 18th IEEE, 2000, pp. 247–252. ∈
Symposium,errors Berkeley, CA, USA, April-May 2013. achieve a small difference between these two capacitors by resultsThe proposed show a correction maximum method estimation is similar error to around the one [8] F. Azais, S. Bernard, Y. Betrand, and M. Renovell, “Towards an adc bist DNL estimation scheme using the histogram test technique,” in Test Workshop, 2000. 1 LSB. [2]
#$∈G.0 Renaud, 1024 M. J. Barragan,2048 S. Mir,3072 and M. Sabut.4096 ADC code Proceedings. IEEE European, 2000, pp. 53–58. On-chip implementation of an integrator-based servo- !"# [9] B. Provost and E. Sanchez-Sinencio, “On-chip ramp generators for !"# Fig.loop 11. for Estimated ADC and static real DNL linearity figures for test each. IEEE code in Asianthe ADC. Test Servo- mixed-signal bist and adc self-test,” Solid-State Circuits, IEEE Journal loopSymposium, measurements Hangzhuo, corrected based China, on estimating 2014. the integration step (ideal of, vol. 38, no. 2, pp. 263–273, Feb 2003. step=1/10 LSB). [10] S. Bernard, F. Azais, Y. Bertrand, and M. Renovell, “A high accuracy triangle-wave signal generator for on-chip adc testing,” in Test Workshop, 70 TIMA Annual Report 2014 (RMS) 2002. Proceedings. The Seventh IEEE European, 2002, pp. 89–94. [11] L. Jin, K. Parthasarathy, T. Kuyel, D. Chen, and R. L. Geiger, “Accurate testing of analog-to-digital converters using low linearity signals with 2 stimulus error identification and removal,” Instrumentation and Mea- 1 surement, IEEE Transactions on, vol. 54, no. 3, pp. 1188–1199, June 2005. 0 [12] B. K. Vasan, D. J. Chen, and R. L. Geiger, “Adc integral non-linearity Real INL
∈ testing with low linearity monotonic signals,” in Instrumentation and Measurement Technology Conference (I2MTC), 2011 IEEE, 10-12 May 0 1024 2048 3072 4096 2 2011, pp. 1–5. 1 [13] R. Holcer, L. Michaeli, and J. Saliga, “Dnl adc testing by the exponential shaped voltage,” Instrumentation and Measurement, IEEE Transactions 0 on, vol. 52, no. 3, pp. 946–949, June 2003.
∈ [14] B. Olleta, H. Jiang, D. Chen, and R. L. Geiger, “A deterministic Estimated INL

& dynamic element matching approach for testing high-resolution adcs 0 1024 2048 3072 4096 #$∈% with low-accuracy excitations,” Instrumentation and Measurement, IEEE #$∈ Transactions on, vol. 55, no. 3, pp. 902–915, June 2006. [15] H. Xing, H. Jiang, D. Chen, and R. L. Geiger, “High-resolution adc linearity testing using a fully digital-compatible bist strategy,” Instru- errors 0 mentation and Measurement, IEEE Transactions on, vol. 58, no. 8, pp. INL estimation 2697–2705, Aug. 2009.
#$∈0 1024 2048 3072 4096 ADC code [16] A. J. Gines, E. J. Peralias, and A. Rueda, “Blind adaptive estimation of integral nonlinear errors in adcs using arbitrary input stimulus,” Fig. 12. Estimated and real INL figures for each code in the ADC. Servo- Instrumentation and Measurement, IEEE Transactions on, vol. 60, no. 2, loop measurements corrected based on estimating the integration step (ideal pp. 452–461, Feb. 2011. step=1/10 LSB).

!"#

Piece-Wise-Linear ramp generator for CMOS imagers and Calibration Techniques

Members: C. Pastorelli, S. Mir and P. Mellot

Cooperation: STMicroelectronics

Contracts: CIFRE absolute limit that comes from the light source. Introduction The picture is degraded as ‘n’ decreases. The size of the pixel matrix in next generation ADC Piece-Wise-Linear ramp CMOS sensors keeps increasing while there is a demand for high frame rates (120 fps). In order After conversion, the additional quantization
noise at the output is
=
∈# with
the to achieve these levels of performance, the read
∈#
∈
∈# out circuitry must be improved taking into LSB. As shown in Figure 2, the quantization account the highly constrained column pitch and noise does not need to be low when the signal is the power consumption [1]. A possible way of strong, because it will be lower than the noise improvement is to use a PWL ramp in the read floor. This observation allows an increase of the out circuit to increase the frame rate without quantization noise for stronger signals and the degrading the image quality. use of a piece-wise linear ramp [2]. A high speed 13Mpix image sensor has been Image sensor architecture developed with a PWL ramp ADC. To get a high speed conversion at low power consumption in a small pitch-limited area, the single slope analog-to-digital (ADC) is the best choice. The time delay from the beginning of the ramp to the time when the ramp crosses the pixel value is measured by a counter as shown in Figure 1.

Pixel

Ramp

Gen.

+ -

Counter DATA

Figure 1. Single slope ADC architecture. The converter LSB is defined by the slope of the ramp and the speed of the counter. Actually, the Figure 2. Single slope converters using linear best way to reduce the conversion time without and piece-wise linear ramps. increasing the power consumption is to PWL RAMP Architecture accelerate the ramp. This is possible taking into account the sources of pixel noise. The main The PWL ramp generator is based on a pure I/C source of electrical noise is the photon shot architecture using an array of 11-bit noise which follows a Poisson law of the form thermometric current sources and a column-

P k = e

[1] distributed integration capacitance as shown in
! Figure 3. with ‘n’ the number of photons. Therefore,
σ
= n and
∈# = =
. This is an
TIMA Annual Report 2014 (RMS) 71

measurements. In the case of 2 segments, a linear ramp conversion is applied with different slopes between the small and big ramps in order to measure the differential delay as drawn below.

Figure 3. Schematic of the I/C ramp generator.

The use of a buffer prevents smearing issues caused by ramp distortions when many comparators flip simultaneously. The I/C ramp generator shown in Figure 1 is controlled with the timing diagram in Figure 4. The switches Figure 5. Additional conversions for ADC SWOFFSET and SWRESET allow, respectively, linearization. to create an offset before starting the ramp and to recharge the integration capacitance. Besides, This calibration data is saved column by column a digital Correlated Double Sampling (D-CDS) for linearization. Then to correct the distortion technique is used to reduce the Vertical Fixed around the knee points, two approaches are st Patern Noise (VFPN) as explained in [3]. under investigation: the 1 focuses on a mathematical interpolation based on the previous calibration data; the 2nd benefits from the implementation of a resistive ladder coupled to a dummy pixel structure without photodiode. In the 2nd approach, the ADC non-linearity can be characterised through the use of a spatially monotonic increasing voltage. The goal with this last approach is to extract the difference value between a linear and a PWL ramp in order to apply this pure delay to the converted value to linearize the data.

References Figure 4. Timing diagram of the I/C ramp generator. [1] A. Theuwissen, “CMOS Image Sensors: State-of- the-art and future perspectives”, 33rd European Solid In the case of a PWL ramp generator, the knee State Circuits Conference, (ESSCIRC), Munich, points have to be as abrupt as possible to Germany, 2007, pp. 21-27. minimize distortion error during the linearization. [2] M.F. Snoeij et al., “A low power column-parallel 12- bit ADC for CMOS imagers”, IEEE Workshop on This first constraint requests the use of a fast CCDs & AIS, Karuizawa, Japan, 2005, pp. 169- 172. current source such as in current steering [3] S. Kuramochi, et al. “A 1/1.8-inch 6.4 MPixel 60 structure or such as proposed in [3]. And the frames/s CMOS Image Sensor With Seamless Mode second issue is to achieve an accurate ramp Change,” vol. 41, no. 12, pp. 2998–3006, 2006.[4] D. ratio between two consecutive segments of Zhang, R. Yassine, L. Truong, and J. Rysinski, “Single power of 2. Slope ADC with On-chip Accelerated Continuous-time Differential Ramp Generator for Low Noise Column- Calibration Techniques Parallel CMOS Image Sensor” IISW, 2013. [5] C. Pastorelli, P. Mellot, S. Mir and C. Tubert, In the proposed technique [5], the output data Piece-wise-linear ramp ADC for CMOS imager sensor for the 1st segment is automatically calibrated by and calibration techniques, International Image the use of a digital CDS while the other Sensor Workshop (IISW), Vaals, The Netherlands, June 2015. segments are calibrated through additional

72 TIMA Annual Report 2014 (RMS) High Frequency Jitter Estimator for SoCs

Members : H. Le Gall, R. Alhakim, M. Valka, S. Mir, H. Stratigopoulos, E. Simeu

Cooperation: STMicroelectronics

Contracts: ELESIS (ENIAC)

signal will contain additional transitions (or Introduction unstable bits) around the rising/falling edges as This work presents an Embedded Test Instrument shown in Fig. 1. It must be noticed that, in (ETI) for the estimation of the High Frequency practice, both clock signals may be affected by HF (HF) jitter of an observed clock signal. The ETI jitter, and there will be a cumulative effect on the uses a second reference clock for under-sampling number of unstable bits present in the beat signal. the observed signal, as considered in previous Modeling the under-sampling process works [1]. However, the analysis of the test response does not require the construction of the We have developed a theoretical model for Cumulative Distributed Function (CDF) of the describing the ETI transfer function, that is, the jitter, as in previous approaches. We demonstrate number of transitions appearing on the beat signal in this work that the transfer function of the ETI during a given time window of the observed clock defined by the ratio of the output and the input signal as a function of the input HF jitter. jitter noise is linear. Spice level simulations have been performed using a 65 nm CMOS Model is described by the state transition STMicroelectronics technology. Experimental probabilities denoted by P00(t), P01(t), P10(t) and studies have been performed using a FPGA- P11(t), while the probabilities of being in each state based test platform and large volume are denoted by Po(t) and P1(t). We can express it STMicroelectronics System-on-Chip (SoC) in form of matrix. devices [2].

Under-sampling concept (2)

The ETI is based on under-sampling the observed Let us suppose the CDF function of the jitter in a clock signal of frequency fobs by means of a rising/falling edge of the observed signal. The reference clock signal of frequency fref, with fref being slightly lower than fobs [1]. The difference Δ same CDF is assumed for both rising and falling between the periods of both signals is given by: edges. The associated probabilities correspond to the first column of the matrix in (2). At time , the

(1) transition probabilities are P00=1 and P01=0. At time , the probabilities are given by where Tref and Tobs are the periods of the the jitter CDF as shown in (3). We can represent reference and observed clocks, respectively. As a these transitions by the Markov model of Fig. 2. result of the time difference Δ, the rising edges of both signals slide in time, with respect to each other, a value Δ during each clock period. (3)

Figure 2. Markov model of the output of the under-sampling process. Once the state transition probabilities are described as a function of time, it is then possible Figure 1. Beat signal affected by jitter. to obtain the transfer function that describes the expected number of transitions in the beat signal In the case that a signal with HF jitter is under- as a function of the input HF jitter, for a given time sampled by a clean reference clock, the beat period. We will not develop here an analytical

TIMA Annual Report 2014 (RMS) 73 model for this function. Instead, we have A. Comparison with the simulation models considered a Monte Carlo simulation to derive this For the case of TestID=1 in Table 1, Fig. 5 function, assuming a Gaussian CDF of the jitter. compares the experimental and simulation results. Jitter Instrument Implementation As it can be seen, the results match with negligible error. Small differences can only be Fig. 3 shows the basic architecture of the ETI. It seen for the lowest value of injected jitter, where has three principal inputs (Tref, Tobs and enable) the jitter estimated by the ETI cannot be lower and two output registers referred as Transition than the under-sampling resolution Δ combined (Tr) and Beat Edge Counter (BEC). The main with measurement error of the actual instruments. components of the proposed architecture are the following: Clock Gater (CG), Under-sampling Unit (USU) and Jitter Detection Unit (JDU).

Figure 3. Basic architecture of the ETI. Figure 5. Comparison of experimental measurements and simulation results for TestID=1. Results B. HF jitter estimation on SoC In this section we will detail the results obtained during the measures performed on FPGA and on Finally, the results of a study conducted for a real real SoC and we will compare them with SoC, considering two on-chip 800 MHz PLLs simulations. implemented in a 65 nm CMOS technology from STMicroelectronics providing the observed and A. Comparative study for HF Jitter the reference frequencies with difference Δ = 1.5 Two experimental tests with different signal ps. frequencies as described in Table I. An analysis of HF jitter has been performed for various process corners, with the results shown in Table 1. Configuration of two experimental tests. different color for each of them in Fig. 6. It can be TestID Fref [MHz] Fobs [MHz] Δ [ps] seen that HF jitter always shows a similar 1 300 300,3 3,333 distribution for all corners with a different mean 2 300,2 300,3 1,109 value.

Fig. 4 shows the correlation between the injected HF jitter and the estimated value for configuration TestID=1. Note that the injected HF jitter is plotted on the horizontal axis in terms of power supply variations (i.e. Vpp [V]), while on the vertical axis is the measured/estimated value of HF jitter.

Figure 6. HF Jitter estimation on real SoC.

References

[1] S. Sunter and A. Roy, “Purely Digital BIST for any PLL or DLL,” 12th IEEE European Test Symposium, pp. 185-192, May 2007.

[2] H. Le Gall, R. Alhakim, M. Valka, S. Mir, H.-G. Stratigopoulos and E. Simeu, High Frequency Jitter Estimator Figure 4. Comparison of the jitter measured using the for SOC, IEEE European Test Symposium, Cluj-Napoca, oscilloscope versus the estimated jitter for each of the Romania, May 2015 (to appear). performed tests.

74 TIMA Annual Report 2014 (RMS) Automatic Synthesis of Reliable Programmable Logic Controllers

Members : E. Simeu, R. Alhakim, G. Ndenoka, M. Tchuente

Cooperation: LIRIMA, Equipe IDASCO, Fac. Sciences, Yaoundé Cameroun

Introduction The control program is written on a computer and is downloaded to the PLC via cable. These loaded Programmable logic controllers (PLCs) are digital programs are stored in non–volatile memory of the devices basically used to control automated PLC. International Electro-technical Commission electro-mechanical systems in industries. They are (IEC) has issued five standard programming one of the most sophisticated and simplest forms languages to program the PLCs: Ladder Diagram, of control systems which are now replacing hard Functional Block Diagram, Grafcet, Structured Text wired logic components (such as relays, cam and List of Instruction Sets. All these IEC timers, drum sequencers) at a large scale, that specification standard languages are adopted by contributes explicitly to save time, energy and the major companies in this industrial field such as: materials and to improve quality, accuracy and Allen Bradley, Siemens, Schneider Electric, etc. precision. The automation operation of PLCs, mentioned in Figure 1, is achieved as follows: Figure 2 shows a representation example of control system using the specification language Grafcet. Figure 2.a depicts the tanks filling system: The system is composed of one reservoir, two tanks, 4 valves (V1, V2, W1 and W2), 4 level sensors (b1, b2, h1 and h2) and one push button (m). Both tanks are used in a similar way, Tank 1 is empty when the level is less than b1 (i.e., b1 = 0), and is full when the level is greater than h1 ( i.e., h1 = 1). At the initial state, both tanks are empty. If push button m is pressed, both tanks are filled by opening valves V1 (V1 = 1 means that valve V1 is open) and V2. When a tank is full, e.g., tank 1, filling stops (by closing valve V1) and its contents start to be used (by opening valve W1). When tank Figure 1. Programmable logic controller (PLC). 1 is empty, valve W1 is closed. Filling from the reservoir to the tanks may only start up again when 1- First, the input points of the PLC are both tanks are empty and if the button m is connected to sensors, which permit to report pressed. Figure 2.b shows the connection of the events and conditions occurring in a input and output elements (button, sensors and controlled process such as motor speed, valves) to the PLC. The specification of this control pressure, temperature, volumetric flow, etc, system based on Grafcet is given by Figure 2.c; and to transmit this information as signals to where the Grafcet chart has 5 transitions, 6 steps PLC. and 4 actions.

2- A built control program inside the PLC will Objective then read the input signal and instruct the PLC what actions to take upon encountering Today, In addition to PLCs there are various types particular input signals or conditions. of programmable control circuits that allow us to monitor the state of input devices (sensors & 3- These generated actions are interpreted by switches) and make decisions based upon a PLC as output signals transmitted to output custom control program to control the state of devices (such as actuators and relays) to output devices (actuators & relays). These control control the process. For example, the PLC circuits have different characteristics and are issues output signals to speed up or slow unfortunately programmed by different down a conveyer, open or close a relay, rotate specification language. Sometimes, Control the arm of a robot, raise or lower temperature. engineer has a need to write the control program in certain specification language (such as Ladder, Thus, the PLC operation is sequential in nature Grafcet …) which is created exclusively for PLC and composed of alternating cycles of monitoring and to execute it in different programmable the inputs, executing the control program and integrated circuits (such as microcontroller, FPGA, driving the outputs. ASIC…); some examples about this remark are TIMA Annual Report 2014 (RMS) 75 mentioned bellow: 1- PLCs are specially designed to survive in harsh industrial situations and shielded from heat, cold, moisture, dust, etc. Therefore PLCs are relatively expensive and not be recommended for some simple control applications which are not required to be operated in such harsh environment with all these protections and isolations. In this situation, the control engineers are asked to use a cheap alternative programmable circuit for achieving the same tasks, so design engineers are forced to learn from zero another new programming language. All that needs to spend more time and efforts and it has high risk to commit beginner-programing mistakes.

2- The PLCs are expensive for the developing countries and usually not available in the universities. In this case, learning the material of automation system and technology for Figure 2. Control system example: (a) tanks filling academics and engineer students becomes system, (b) connection this system with PLC, (c) so difficult and boring without using any real specification of this system on Grafcet. demonstration platform. Therefore, the proposed tool will permit the academics and References students to build the control program by using [1] F. Mallet, D. Gaffé, F. Boéri, Concurrent Control the specification PLC language, then the Systems: from Grafcet to VHDL, IEEE Euromicro control programs are applied on real and Conference, Maastricht, Netherlands, September 2000. practical platforms, based on cheap control [2] S. Frank, S. Sebastian, F. Alexander, Tool support for circuit, in order to evaluate and validate . an automatic transformation of GRAFCET specifications into IEC 61131-3 control code, IEEE Emerging Thus, the five IEC standard programming Technologies & Factory Automation Conference, languages allow engineer to specify the operation Cagliari, Italy, September, 2013. of discrete event systems, even those who are more complex. However, they do not allow a direct [3] T. Krairojananan, S. Suthapradit, A PLC Program Generator Incorporating Sequential Circuit Synthesis realization on different control targets like Techniques, IEEE Asia-Pacific Conference on Circuits microcontrollers or FPGA. Therefore, the objective and Systems, Chiang Mai, Thailand, November 1998. of this research work is to build an appropriate software tool that takes in input any PLC control [4] C. André, D. Gaffé, Evénements et conditions en program and treats it by successive refinements to GRAFCET, Journal APII-AFCET/CNRS, vol. 28, Number produce an implementation on different targets. 4, pp. 331-352, 1994.

Several research studies have been occurred in order to find appropriate techniques which allow synthesizing any PLC control specification code and converting it to other executable programs (such as C, Fortran, VHDL) adapted with different hardware architectures [1-4].

76 TIMA Annual Report 2014 (RMS)

Power Supply Noise Estimation on SoCs

Members: M. Valka, C. Partasarathy, H. Le Gall, S. Mir, H. Stratigopoulos, E. Simeu

Cooperation: STMicroelectronics

Contracts: NANO 2017

Introduction Testing for performance is mandatory to catch timing or delay faults. It is often implemented through at-speed scan testing for logic circuits. At- speed scan testing consists of using a rated (nominal) system clock period between launch and capture for each delay test pattern, while a Figure.2. Ring Oscillator based Power Supply Noise Detector. longer clock period is normally used for scan shifting (load and unload cycles). Although at- The next techniques for PSN detection are based speed scan testing is mandatory for high-quality on a Ring Oscillator architecture (Figure 2). These delay fault testing, its applicability is severely techniques are reported in [1,2] where the process challenged by test-induced yield loss which may monitoring box (PMB) is used to determine the occur when a good chip is declared faulty during actual power consumption. PMB is represented as at-speed scan testing. The major cause of this a ring oscillator with its output used as the clock of problem is Power Supply Noise (PSN), i.e., IR- a counter. The counter works during a fixed time drop and Ldi/dt events, caused by excessive window and the output value C is read. The C switching activity (leading to excessive power value depends on the ring oscillator frequency consumption). which itself depends the actual power supply voltage. Thus, C is the actual frequency measure. State of the art It is then compared with the expected one to verify the system performances. Thus, in case of PSN In order to determine the Power Supply Noise event the value of C is lower than expected. events, and on-chip detector (PSN-D) has to be developed. From the literature the Power Supply Noise detectors can be roughly classified into the three categories: (i) ADC based detectors, (ii) Ring Oscillator based detectors and (iii) Delay Line based detectors.

Figure 3. Delay Line based Power Supply Noise Detector.

Figure1. ADC based Power Supply Noise Detector The last category of PSN-D is represented by the Delay Line architectures (Figure 3). It has two The ADC-based detector (Figure 1) is composed main inputs: Fobs and Fref. The output is a 17-bit of a buffer (BF) that shares the measured voltage bus called beat edge counter (BEC). The output value corresponds to the number of timing domain (VDDmeas) and a FF placed on noise-free uncertainty (jitter) measured between Fobs and voltage domain (VDDsafe). The input of the buffer ( A) receives a square signal. Due to the toggle Fref [3]. activity in the circuit under test, PSN events will be References provoked on the VDD that will affect the output meas signal (B) (timing distortion). The output signal is [1] Kobayashi, K.; Yamaguchi, J.; Onodera, Hidetoshi, sampled by the reference clock (CLK) of given "Measurement results of on-chip IR-drop," Custom frequency. If signal B is noise-free the signature Integrated Circuits Conference, 2002. Proceedings of the will provide the same logic value. However, once IEEE 2002 , vol., no., pp.521,524, 2002 the signal B is affected by the noise, the FF’s [2] Chakravarty S., et al, “Optimal Manufacturing Flow to Determine Minimum Operating Voltage”, ITC 2011, pp. 1- setup will be violated and the logical value will 10 change. In order to design such ADC in multi-bit mode, the architecture has to be multiplied N [3] Valka, M.; et. al.; “Power Supply Noise sensor based on Timing Uncertainty Measurements”, Asian Test times (i.e., N-buffers, N-FFs). Symposium (ATS), Nigaata, 2012 Japon TIMA Annual Report 2014 (RMS) 77

78 TIMA Annual Report 2014 (RMS) Non-intrusive sensors for built-in RF test

Members : A. Dimakos, H.-G. Stratigopoulos, S. Mir, A. Siligaris, E. De Foucauld

Cooperation: CEA-LETI

Contracts: ELESIS (ENIAC) performances. For this purpose, we can employ Introduction Process Control Monitors (PCMs), such as single layout components (e.g. transistors, capacitors, Standard RF test practices incur a very high cost. resistors, inductors), and dummy circuits that are An alternative technique with high potential to reduce extracted from the CUT topology (e.g. bias stages, test cost is built-in test, where the idea is to integrate current mirrors, gain stages, level-shifters, etc.). on-chip some structures to facilitate the test, such as a These sensors are placed in close physical test stimulus generator, response analyzer, etc. The proximity and are matched to identical structures most popular built-in test approach for RF transceivers in the CUT. For example, we can place a dummy is the loop-back test where the test signals are bias stage next to the bias stage of the CUT, a generated in the baseband and the transmitter’s output dummy transistor next to a critical transistor in the is switched to the receiver’s input to analyze the test CUT, etc. In this way, the sensors and the CUT response also in the baseband. Another popular built-in “witness” the same die-to-die (D2D) and test technique relies on the use of envelope detectors correlated within-die (WID) process variations and, and current sensors to extract DC/low-frequency test as a result, the measurements obtained on the signatures that nevertheless carry RF information. sensors will be correlated to the performances of the CUT to a very large extent. An indirect, low- For a successful implementation of a built-in test cost test can be put in place by employing the technique, different criteria need to be satisfied alternate test paradigm to map the sensor simultaneously: (a) the test accuracy of the standard measurements to the performances. This test method is maintained; (b) the performances of the approach has been inspired by the PCMs typically Circuit Under Test (CUT) are not affected; (c) the pin placed in the scribe lines of a wafer to monitor and area overheads are acceptable; and (d) the achieved variability and identify off-target process test cost reduction justifies the built-in test development parameters. effort. It is noteworthy that none of the aforementioned state-of-the-art built-in test techniques fully satisfies In our previous work, we demonstrated this type of objective (b). For example, the loop-back connection non-intrusive built-in test based on variation-aware requires the insertion of a switch and an attenuator and, sensors for a 0.25µm RF Low Noise Amplifier for some types of receivers, even an extra mixer is (LNA). A disadvantage of the technique is that the inserted in the RF signal path. Envelope detectors and correlation between the sensor measurements current sensors also tap into the RF signal path. In and the performances of the CUT and, ultimately, general, adding components in the RF signal path the success of alternate test, is affected by degrades the impedance matching and adds parasitics, uncorrelated WID variations (e.g. mismatch). It is which inevitably shift the performances and unbalance expected that this type of variations will become the performance trade-offs achieved by design. more prominent as we shrink transistor lengths.

To address this issue, built-in test circuitry needs to be In this work, we demonstrate the non-intrusive co-designed with the CUT which increases design built-in test strategy for a 65nm RF LNA and we iterations to meet the target design specifications, if show that the correlation still holds strong in this possible. For this reason, designers are rather reluctant particular advanced technology. We observed that to incorporate such built-in test techniques since the the variability in the inductors explains to a large design specifications are stringent and exploit the full degree the variability in the performances, thus it capabilities of advanced technology nodes. was deemed necessary to monitor the variability in the inductors. However, adding a dummy inductor Non-intrusive built-in test PCM is not a smart choice since it incurs a large area overhead. For this reason, variability in the In this work, we propose to rely on non-intrusive inductors was not considered at all in our previous built-in sensors that have the comparative work. In this work, we studied the sources of advantage that let the design intact. These non- variability in the inductors and we found that most intrusive sensors capitalize on the undesired of the variability is due to the variability in the phenomenon of process variations. resistivity of the high-level metal and alucap layers that form the coils of the inductors and not due to The underlying idea is to monitor process the variability in the pure inductance of the coil. variations instead of measuring directly the RF This led us to employ low area overhead metal

TIMA Annual Report 2014 (RMS) 79 and alucap resistor PCMs, instead of an area- (a) average Root Mean Square (RMS) error, (b) hungry inductor PCM, in order to capture most of absolute average RMS error, (c) maximum error, the variability in the inductors. and (d) correlation coefficient between the simulated (e.g. “true) and predicted performances. Benefits of the approach

The proposed test approach has some appealing attributes: - Area overhead: The dummy analog stages and the PCMs occupy a very small area on the die. These sensors are in fact placed in the area within the inductors of the LNA which is anyhow left void to respect electromagnetic design rules. Since the inductors are by far the most area-hungry components, the area overhead is kept at a minimum. - Test cost: The dummy analog stages are self- biased and provide DC measurements. The PCMs require DC or low-frequency test stimuli and Figure 1. 2.4 GHz CMOS inductive degenerated LNA provide DC or low-frequency measurements. In schematic. short, using these nonintrusive variation-aware sensors the test stimulus generation and test Table 1 shows the alternate test results for the response analysis are largely simplified. In main six performances of the LNA considering addition, the CUT needs not to be powered-on only D2D variations. Table 2 shows the same results during test which, combined with the simplified taking into consideration this time WID variations as test generation and test response analysis, allows well. We observe that the correlations have slightly testing multiple devices in parallel, thus drastically degraded, but they still remain strong. We conclude that reducing the test cost. a low-cost alternate test based on the selected set of - Non-intrusiveness: The non-intrusive variation- non-intrusive sensors is capable of replacing the aware sensors do not degrade the performances standard specification tests for measuring the of the CUT. The built-in test is totally transparent performances while maintaining practically the same to the design, thus the test development is test accuracy. completely dissociated from the design, which finds designers eager to adopt this test approach. - Generic approach: The non-intrusive variation- aware sensors are in fact no more than components and analog stages built from components in the CUT, thus the idea is generic and transferable to virtually any RF circuit. Table 1. Alternate test results considering only D2D variations. Results

The LNA and the non-intrusive variation-aware sensors have been designed using the 65nm CMOS065 bulk technology provided by ST Microelectronics. The schematic of the LNA is shown in Fig. 1. The sensors that we have employed in the analysis include (a) a dummy current mirror, (b) a diode-connected MOS PCM, Table 2. Alternate test results considering both D2D (c) a MOM capacitor PCM, and (d) high-level and WID variations. metal and alucap resistor PCMs. References A Monte Carlo sample set of 1000 circuit instances was used to learn the regression [1] A. Dimakos, H.-G. Stratigopoulos, A. Siligaris, S. Mir, functions in alternate test. Out of the 1000 and E. De Foucauld, “Non-Intrusive Built-In Test for instances, we used 800 circuit instances in the 65nm RF LNA”, 19th IEEE International Mixed-Signal, training set and the rest of 200 instances were Sensors, and Systems Test Workshop, 2014. used as a validation set to provide an unbiased estimate of the prediction error of alternate test. The prediction error is expressed in terms of the 80 TIMA Annual Report 2014 (RMS)

One-Shot calibration of RF circuits based on non-intrusive sensors

Members : M. Andraud, H.-G. Stratigopoulos, E. Simeu and S. Mir

Contract: SACSO (ANR)

structures can be identified in the topology of the Introduction circuit, and are carefully chosen to exhibit high correlation with the RF performances that have to The current demand for ubiquitous connectivity be monitored. imposes stringent requirements on the functionality of RF transceivers. To increase performance while reducing the form factor, power consumption, and overall manufacturing costs at maximum, the trend nowadays is to build heterogeneous Systems-on-Chip (SoCs), where the RF transceiver is integrated together on the same die with the digital processor, memory, etc. But while the scale down of the CMOS technology, together with the development of design automation tools, have always been Figure 2. Self-biased cascade power amplifier topology suitable for improving digital circuits, the situation and extracted non-intrusive sensors. is different for RF transceiver design that remains more like an art. Indeed, for technology nodes As an example, Fig.2 shows a case study below 65 nm, the manufacturing yield of RF composed of one stage of a 2.4 GHz power transceivers drops significantly due to amplifier (PA), with a self-biased cascode exacerbated process variations, which is a show- topology. The tuning knobs have been chosen to stopper for the evolution of heterogeneous SoCs . avoid any change in the PA topology, and consist of the bias voltage VG and the power supply voltage VD. To build the non-intrusive sensors, we Proposed one-shot calibration technique can create a dummy gain stage composed of identical cascode transistors M1 and M2 and, in This work proposes to develop a post- addition, we can create a dummy resistor RM and manufacturing calibration methodology for RF a dummy capacitor CM. These dummy structures circuits based on non-intrusive built-in sensors are extracted from the initial circuit layout, placed and pre-trained regression models, as presented in close physical proximity on the die and are well- Fig.1. matched to the corresponding structures in the PA . stage. The underlying idea is that the dummy structures will "witness'' the same die-to-die and correlated within-die process variations as the circuit itself. Thus, we expect that measurements obtained on the dummy structures will be highly correlated to the performances of the RF circuit. In this way, the performances can be implicitly inferred from the measurements and the tuning knob settings. In the example of Fig.2, we can Figure 1. Proposed post-manufacturing calibration consider measuring resistance RM, capacitance setup for RF circuits. CM, and the DC current of the dummy gain stage

IDC. The key property of this built-in test approach Calibration is enabled by judiciously inserting is its non-intrusiveness, that is, the sensors are tuning knobs into the circuit. The tuning knobs add totally transparent to the circuit since they do not degrees of freedom in the design and can act on tap into its signal path. In addition, this built-in test all the performances irrespectively. The calibration approach can be applied virtually to any circuit algorithm employs a pre-trained regression model and the RF circuit needs not to be powered on that expresses the relationship amongst circuit during testing. The correlation between the sensor performances, tuning knob values and measurements and the performances can be measurements that offer an "image'' of process established by regression modeling. variations, through non-intrusive built-in sensors. Those sensors consist of basic analog stages (i.e. Considering the tuning knob values and non- bias stage, current mirror, gain stage, etc.) and intrusive sensor measurements, there exists the single layout components (i.e. transistor, following relationship for each performance P of capacitor, resistor, etc.) extracted from circuit the circuit: layout and duplicated on the die. These dummy TIMA Annual Report 2014 (RMS) 81

P=fP(M,TK) (1) sample of PA instances that is used as a training set to learn the regression functions for predicting Where M is the vector of sensor measurements the performances for a given set of sensor and TK is the vector of tuning knob settings. This measurements and the tuning knob setting. We relationship can be learned off-line during a consider four major PA performances, namely training phase that employs a set of circuit linearity, measured by the 1-dB compression point instances that is representative of the (OCP1), power gain, power added efficiency manufacturing process and the tuning knob range, (PAE), and DC power consumption (PDC). as illustrated Fig.3. Once the relationships are Thereafter, another Monte Carlo simulation is learned, they can be readily used for calibrating carried out to generate PA instances that fail one the circuit. Since the non-intrusive sensors are not more performance specifications. The blue electrically connected to the RF circuit, the sensor histograms in Fig.4 illustrate the performances for measurements stay invariant when varying the this faulty sample for the nominal tuning knob tuning knob setting. setting. The calibration is performed for these faulty instances using the regression functions learned beforehand to find optimal tuning knob settings. The result is shown with the green histograms in Fig.4. As can be observed, the histograms now are more centered and lie within the specifications, that is, all faulty circuit instances have been successfully calibrated.

Finally, notice that the regression models can Figure 3. Illustration of training scheme used in the predict the calibrated performances, thus a calibration process. standard test to confirm that the calibration has been completed successfully may not be even This key property thus allows to perform the necessary. calibration in one-shot, that is, in a single test step that involves obtaining the sensor measurements only once. In other words, we are able to achieve a complete independence between sensor measurements and tuning knob settings. The calibration procedure is then as follows. First, we obtain the sensor measurements and we predict each performance P using the corresponding regression function fP for the nominal tuning knob setting. If P violates the specification, then calibration starts. The calibration is a quick optimization procedure that is run off-line. The optimization uses fP as the objective function and consists of finding an appropriate tuning knob setting that optimizes the performance value. Since the sensor measurements stay invariant under tuning knob changes, there is no need to measure sensor response for each visited tuning knob setting, thus Figure 4. Calibration results for a 2.4 GHz RF power achieving a one-shot calibration amplifier.

Results References

Fig.4 shows the calibration that can be achieved [1] M. Andraud, H.-G. Stratigopoulos, and E.Simeu, with the proposed method in the case of the PA « One-shot calibration of RF circuits based on non- example. The PA is designed in the 65 nm intrusive Sensors », in Proc. Design Automation CMOS065 technology provided by Conference (DAC), 2014.

STMicroelectronics and is formed by cascading [2] M. Andraud et al., « Solutions for the self-adaptation two stages, one driver stage and one power stage, of communicating systems in operation », in Proc. both with the same self-biased cascode topology International On-Line Testing Symposium (IOLTS), shown in Fig.2. The same non-intrusive sensors 2014. as in Fig.2 are used within both stages. A Monte Carlo simulation is carried out to generate the

82 TIMA Annual Report 2014 (RMS

Enhance Error Concealment Process in a Digital Image Decoding

Key-words: Video quality, error concealment, regression, prediction, video decoder,

Members : B. Ekobo-Akoa, R. Alhakim, E. Simeu, F. Lebowsky

Cooperation: STMicroelectronics

Contracts: Research contract with STMicroelectronics

of applying the classification-based VQMT on 24 Introduction videos in CIF format. These results are classified into With the evolution of multimedia technologies and five groups: Excellent, Good, Unsatisfactory, Bad and requirements in quality of images being viewed by Worse. 70% of video sequences were used for training users, digital video decoders must provide satisfactory and 30% for the test. quality to decoded video. Therefore, in this project we attempt to develop digital video decoder structure in order to ensure the best perceptual quality as possible to images at the output of multimedia devices, regarding to human visual perception. The proposed way in order to improve digital decoder performance is to establish a suitable supervision loop, which is composed of two main blocks: The first is a VQMT (virtual quality measuring tool) for detecting and measuring visual artifacts inside the received videos. The second is a suitable adaptive filter for reducing / concealing the visual artifact effects. Video quality measurement tools (VQMT)

The usage of artificial intelligence and statistical Figure 1. Classification-based VQMT Performance for analysis algorithms has helped in various domains to the videos used for the test: Clustering vs. MOS overcome optimization issues in Microelectronics. In [1-3], we have applied these approaches on image and • Regression-based VQMT video processing in order to detect and measure efficiently visual artifacts. We have selected EPFL We have explained in [1] how to use regression database, described in [4-5], to design VQMT block and algorithms for deriving suitable video quality optimize its parameters, because this video database measurement tool (VQMT). We have submitted the respects the following criteria: 1) the database must mobile video of the data base to the regression-based consist of a set of videos covering a wide variety of VQA and compared the predicted scores with the MOS. levels of spatial/temporal information complexity and The results in Figure 2 show the good correlation levels of loss of packets, 2) the injected errors must be (correlation coefficient R² = 0.946) between the independent of the source of image capture, 3) Each estimated MOS obtained from by regression-based video experience of this database must be accompanied VQMT and the real MOS provided in EPFL database. with the corresponding subjective human-evaluation The results confirm that the proposed VQMT system is score (denoted by Mean Observers Score: MOS). very close to human perceptual vision. The four quality metrics extracted from EPFL database and used for developing statistical algorithms are: peak signal to noise ratio (PSNR), packet loss rate (PLR), spatial index (SI) and blur metric. We have employed three statistical methods for construct video quality measurement tool, which allow generating objective video-evaluation score correlated perfectly to human visual system perception. These three statistical learning models of VQMT are respectively based on classification, non-linear regression and artificial neural networks (ANN).

• Classification-based VQMT Figure 2. MOS (x axis) vs. estimated MOS (y axis) We have explained in [2] how to use classification based on regression algorithms algorithms for deriving suitable video quality • ANN-based VQMT measurement tool (VQMT). Figure 1 shows the results TIMA Annual Report 2014 (RMS) 83

We have explained in [2] how to use artificial neural noised image score is -1.07 and the obtained denoised networks algorithms for deriving suitable video quality score is 1.88, with a 5-by-5 pixels filter. measurement tool (VQMT). The implemented ANN has 2 layers with 4 neurons for the first (hidden) layer and 1 neuron for the second layer [2]. The MSE obtained at epoch 19 is very close to zero about 5.10-2. The results in Figure 3 show the good correlation (correlation coefficient R² = 0.98) between the estimated MOS obtained from by ANN-based VQMT and the real MOS provided in EPFL database. The results confirm a good match between experience MOS and the VQMT Figure 4. Noise concealment with Wiener filter: Left: estimated output scores. Image with Gaussian noise; Right : denoised image.

After adding this supervision loop within the digital video decoder, we are able to conceal the better as possible the most visual artifacts appearing on the image/video, and deliver at the output image/video close as possible to the original picture captured, as seen by human eyes.

References [1] Ekobo Akoa B., Simeu E., Lebowsky F., "Video decoder monitoring using non-linear regression," On- Line Testing Symposium (IOLTS), 2013 IEEE 19th International, pp.175,178, July 2013 Figure 3. MOS (x axis) vs. estimated MOS (y axis) [2] Ekobo Akoa B., Simeu E., Lebowsky F., "Using based on ANN Artificial Neural Network for Automatic Assessment of Video Sequences".27th IEEE International Conference Artifact Concealment on Advanced Information Networking and Applications As explained earlier, the first block of the Workshops (WAINA'13), Barcelone, Espagne, 25- supervision loop, video quality measurement tool 28/03/2013 VQMT, has been establish based on one of the three [3] Ekobo Akoa B., Simeu E., Lebowsky F., "Using proposed statistical algorithms (classification, statistical analysis and artificial intelligence tools for regression or ANN). This block permits to detect and automatic assessment of video sequences". Proc. SPIE measure different type of visual artefact. While the next 9015, Color Imaging XIX: Displaying, Processing, block of the closed loop is used to reduce and conceal Hardcopy, and Applications, San Francisco, Californie, these artifacts. To simplify the concealment process, we Etats-Unis, 8/01/2014 take only the two artifacts (blur and noise) into considerations. Both distortions have been assimilated [4] De Simone F., Naccari M., Tagliasacchi M., Dufaux as functions with a Gaussian distribution on the entire F., Tubaro S. and Ebrahimi T. (2009). Subjective image, the degraded image could be represented as assessment of H.264/AVC video sequences transmitted follows:
= h ∗ u + b, where u is the original image to over a noisy channel. Proc. Int. Conf. QoMEX. restore, h is a positive symmetric kernel convolution [5] De Simone F., Tagliasacchi M., Tubaro S. and filter (blur effect) and b is a Gaussian white noise of Ebrahimi T., “A H.264/AVC video database for the standard deviation σ. evaluation of quality metrics,” in Proceedings of IEEE Among the several methods used for error International Conference on Acoustic Speech and concealment in image/video, we have chosen Wiener Signal Processing (ICASSP), Dallas, TX, USA, March filter. In fact, Wiener filter does not characterize the 2010. signal and noise by their analytical form but by their statistical properties by using the local neighborhoods of n-by-n to estimate the local image mean and standard deviation. This is a unique linear finite impulse response filter adapted to both the attenuation of noise and reduction of blur in an image. We have developed the denoising algorithm, handling the n parameter of the 2D Wiener filter in order to maximize the NLR-based predicted score of the denoised image. Figure 4 shows the results obtained with an iteration step of 0.25. The

84 TIMA Annual Report 2014 (RMS)

Energy modeling and management in wireless sensor networks

Key-words: Wireless Sensor Networks, Energy consumption, cover set, target coverage, K-coverage.

Members ; D. Tchuani Tchakonte, E. Simeu, M. Tchuente

Cooperation: LIRIMA, Equipe IDASCO, Fac. Sciences, Yaoundé Cameroun

Contracts: AUF Grant

Introduction problem of maximizing the network lifetime while preserving coverage of all targets is called target The explosive advancement in wireless- coverage. This study aims at solving the target communication technologies in recent years have coverage problem using cover sets. witnessed an increased interest in the use of wireless sensor networks (WSNs) in numerous In a network where the sensors are deployed applications. The WSNs help to overcome the densely, a partial subset of the sensors can monitor constraint of wiring, which significantly limited the all the targets, while other sensors are maintained deployment of a large number of sensor nodes. It in standby or sleep state to save energy. These has thus become possible to deploy a network subsets are cover sets. The problem of constructing consisting of many collaborative sensors in order to the maximum number of cover sets has been monitor larger area of interest. In these proved NP-hard [1]. In most works, authors assume applications, micro-sensor nodes equipped with that all sensors have the same lifetime. Under this embedded RF transceiver for communication are assumption, disjoint or non-disjoint cover sets are deployed to operate autonomously. built. For all cases, the cover sets have the same This new micro-sensor technology has opened new lifetime that is a fraction of the sensor lifetime. Let f perspectives for various applications in many fields be the number of sensors covering the least (disaster management, military, space exploration, covered target, and w the number of cover sets environmental monitoring, medical, domestic ...) formed by a disjoint cover set heuristic. We showed However, the use of WSNs still poses many that the gain over the network lifetime that we can challenges both from an algorithmic and practical get when using non disjoint cover sets is at most point of view (deployment, location, autonomy, f/w. coverage, collection and data fusion, ...). In particular, energy consumption management is a By using a more realistic assumption, we proposed key element for optimizing network performances. a heuristic that outperforms previous ones. Indeed, This study focuses on the analysis and optimization we assume that each sensor has its own lifetime of the lifetime of the network, which is determined and we take it into consideration while forming the by the lifetime of the batteries. Indeed, the only cover sets. Thus, when a sensor fails, it is replaced source of energy of a sensor node is its battery, by new ones so that all the targets are always whose lifetime is limited. covered. Moreover, after replacement of a sensor in the current cover set, a polynomial time checking Optimization of the WSN lifetime: 1 - coverage procedure is applied to detect and to pause the The WSNs consist of a set of small electronic sensor nodes that become redundant. These devices, autonomous, and equipped with sensors redundant sensors are can be useful afterwards in capable of communicating there between. the construction of new cover set. Our solution Each node contains: gives a longer network lifetime and a shorter time - a detection unit, responsible for recording physical complexity. Currently, the first cover set is built to quantities (temperature humidity, vibration, ...) and cover all the targets but from the second one, transforming them into digital values targets that the heuristic tries to cover is those the - a data processing and storage unit failed sensor was the only one to cover. So the - a wireless transmission module heuristic is executed on a small subset of targets. - a power supply The cost function we used to select the “best” It is usually impossible to recharge the batteries sensor at each iteration takes into account the because of the location of nodes, but more often for number of new targets covered by the candidate the simple reason that this is practically or sensor, the number of already covered targets (by economically unfeasible. previously selected sensors) that the sensor covers Sensors are generally deployed over the area of and the remaining lifetime of the candidate. This interest to cover a set of specified locations called function was proposed by Zorbas et al [2]. targets. The constraint is that each target should be covered at any time by at least one sensor. The

TIMA Annual Report 2014 (RMS) 85

By using the same cost function, the results Optimization of the WSN lifetime: k - coverage obtained with our method are we compared to those given by the “traditional” method that consists Depending on the application, the desired level of in building from zero the cover set when a sensor coverage can be different. In many cases, each fails. Some results are shown on figures 1 – 3. target should be covered at any time by at least k sensors, with k greater or equal 1: that is the k- coverage constraint. k-coverage [3] is useful for the 7000 purpose of reliability, robustness, or localization (e.g. triangulation-based positioning). 6000 Tradition The k-coverage problem is how to maximize the 5000 al model network lifetime while guaranteeing that each target based is k-covered. This problem is then a generalization 4000 algorithm of the previous one (1-coverage). The goal is to find out how to exploit results from 1-coverage problem New Network lifetime 3000 to solve k-coverage and how to design a new model solution for k-coverage without using 1-coverage based and then compare the performances of the two 2000 algorithm solutions.

Number of sensors [1] M. Cardei, M. Thai, Y. Li, W. Wu, Energy- Figure1. Network lifetime in relation to number of efficient target coverage in wireless sensor, in: sensors Proc. of INFOCOM 05, Vol. 3, IEEE, 2005, pp. 1976– 1984.

12,0% [2] Dimitrios Zorbas, Christos Douligeris: Connected Tradition 10,0% coverage in WSNs based on critical targets. al model 8,0% Computer Networks 55(6): 1412-1425, 2011. 6,0% based 4,0% algorithm [3] F. Huang, and C. Tseng, The coverage problem 2,0% in a wireless sensor network, in Proc. WSNA’03, 0,0% New model 2003. Distance to the

500 650 800 950 based theoritical maximum Number of sensors algorithm

Figure 2. Distance to the theoretical maximum in relation to the number of sensors

54% 52% 50% 48% 46%

distance to the 44% Reduction of the theoritical maximum 500 550 600 650 700 750 800 850 900 950 1000 Number of sensors

Figure 3. Improvement of the new algorithm over the distance to the theoretical maximum given by the traditional model based algorithm

86 TIMA Annual Report 2014 (RMS)

Academic and research members

BARRAGAN Manuel ANGHEL Lorena

Position Position Researcher at the French National Research Agency Professor at Grenoble Institute of Technology (CNRS) (Grenoble INP – Phelma) (Physique-Electronique-

Matériaux) Current responsibilities

Researcher in the Reliable Mixed-signal Systems Current responsabilities (RMS) Group Researcher in the Architectures for Robust and complex Integrated Systems (ARIS) group

BENABDENBI Mounir BASROUR Skandar Position Position Associate Professor at Grenoble-INP PHELMA Professor in Electronics and Microsystems at Ecole (Physique-Electronique- Matériaux) since 2009 Polytechnique de l’Université Joseph Fourier (Polytech’G), Electrical Engineering Department (3I) Current responsibilities Researcher in the Architectures for Robust and Current responsabilities complex Integrated Systems (ARIS) group Head of the Micro and Nano Systems (MNS) group

BONVILAIN Agnès BORRIONE Dominique Position Associate Professor at Ecole Polytechnique de Position l’Université Joseph Fourier (Polytech’G) Professor at Ecole Polytechnique de l’Université Joseph Fourier (Polytech’G), Electrical Engineering Current responsabilities Department (3I) Researcher in the Micro and Nano Systems (MNS) group Current responsabilities Director of TIMA Laboratory since January 2007

TIMA Annual Report 2014 - Academic and research members 87

FOURNEL Nicolas FESQUET Laurent

Position Position Associate Professor at Grenoble Institute of Associate Professor at Université Joseph Fourier UFR Technology (Grenoble INP) IM2AG

Current responsibilities Current responsabilities Head of the Concurrent Integrated Systems (CIS) Researcher in the System Level Synthesis (SLS) group group

GASCARD Eric LEVEUGLE Régis Position Associate Professor at Ecole Polytechnique de Position l’Université Joseph Fourier (Polytech’G) Professor at Grenoble Institute of Technology (Grenoble INP - Phelma) Current responsabilities Researcher in the Architectures for Robust and Current responsabilities complex Integrated Systems (ARIS) group Vice-director of TIMA Laboratory since January 2007 Researcher in the Architectures for Robust and complex Integrated Systems (ARIS) group

MAISTRI Paolo MANCINI Stéphane

Position Position Research Engineer at the French National Research Associate Professor at École Nationale Supérieure Agency (CNRS) d'Informatique et de Mathématiques Appliquées of the Grenoble Institute of Technology (ENSIMAG) of Current responsabilities Grenoble INP Researcher in the Architectures for Robust and complex Integrated Systems (ARIS) group Current responsibilities Researcher in the System Level Syntheis (SLS) group

88 TIMA Annual Report 2014 - Academic and research members

MORIN-ALLORY Katell MIR Salvador

Position Position Research Director at the French National Research Associate Professor at Grenoble Institute of Agency (CNRS) Technology (Grenoble INP - Phelma)

Current responsabilities Current responsibilities Vice-director of TIMA Laboratory Researcher in the Verification & Modeling of Digital Head of the Reliable Mixed-signal Systems (RMS) Systems (VDS) group Group

MULLER Olivier NICOLAIDIS Mihail

Position Position Associate Professor at École Nationale Supérieure Research Director at the French National Research d'Informatique et de Mathématiques Appliquées of the Centre (CNRS) Grenoble Institute of Technology (ENSIMAG) of Grenoble INP Current responsibilities Current responsibilities Head of the Architectures for Robust and complex Researcher in the System Level Syntheis (SLS) group Integrated Systems (ARIS) Group

PANCHER Fabrice

Position PÉTROT Frédéric Research Engineer CNRS at TIMA Laboratory since June 2010 Position Professor in Computer Architecture at École Nationale Supérieure d'Informatique et de Mathématiques Current responsabilities Appliquées of the Grenoble Institute of Technology Software developments for TIMA’s research groups (ENSIMAG) of Grenoble INP

Current responsibilities Head of the System Level Syntheis (SLS) group

TIMA Annual Report 2014 - Academic and research members 89

PORTOLAN Michele PIERRE Laurence Position Position Associate Professor Grenoble Institute of Technology Professor in Computer Science at Université Joseph (Grenoble INP - Phelma) Fourier Current responsibilities Current responsibilities Researcher in the Architectures for Robust and Head of the Verification & Modeling of Digital Systems complex Integrated Systems (ARIS) group (VDS) group

POSSAMAI BASTOS Rodrigo ROUSSEAU Frédéric Position Associate Professor at Université Joseph Fourier (UFR Position IM2AG) Professor at Université Joseph Fourier

Current responsibilities Current responsabilities Researcher in the Concurrent Integrated Systems Researcher in the System Level Synthesis (SLS) (CIS) group group

RUFER Libor

Position SHEIBANYRAD Abbas (Hamed) Researcher at Université Joseph Fourier Position Current responsibilities French National Research Centre (CNRS) Research in the Micro- & Nano-systems (MNS) Group: Research Fellow since 2009 Electro-acoustic and electro-mechanical transducers modeling, design, and fabrication applied to MEMS- Current responsabilities based sensors and actuators, energy harvesting, and Researcher in the System Level Synthesis (SLS) group RF MEMS.

90 TIMA Annual Report 2014 - Academic and research members

SICARD Gilles SIMEU Emmanuel

Position Position Associate Professor at Université Joseph Fourier Associate Professor at Ecole Polytechnique de l’Université Joseph Fourier (Polytech’G) Current responsabilities Head of the Concurrent Integrated Systems (CIS) Current responsibilities group Co-Head of the Reliable Mixed-signal Systems (RMS) Group

STRATIGOPOULOS Haralampos VELAZCO Raoul

Position Position Researcher at the French National Research Agency Research Director at the French National Research (CNRS) Agency (CNRS)

Current responsibilities Current Responsibilities Researcher in the Reliable Mixed-signal Systems Co-Leader of the Architectures for Robust and (RMS) Group complex Integrated Systems (ARIS) group Researcher in Architectures for Robust and complex Integrated Systems (ARIS) group

ZERGAINOH Nacer-Eddine

Position Associate Professor (Maître de Conférences) in Computer Engineering and architecture, Ecole Polytechnique de l’Université Joseph Fourier (Polytech’G)

Current responsibilities Researcher in Architectures for Robust and complex Integrated Systems (ARIS) Group

TIMA Annual Report 2014 - Academic and research members 91

92 TIMA Annual Report 2014 - Academic and research members

Staff members

BEN TITO Laurence CHEVROT Frederic Position Assistant Engineer INPGrenoble at TIMA Laboratory Position since March 2010 Assistant Engineer INPGrenoble at TIMA Laboratory since March 2003 Current responsabilities Executive Secretary Current responsabilities Assistant System Engineer

DE BIGNICOURT Alice FOURNERET-ITIE Anne-Laure

Position Position Personnel officer ADR at TIMA Laboratory since Engineer CNRS at TIMA Laboratory since May 2011 September 2003

Current responsabilities Current responsabilities Webmaster Personnel officer and special event manager

GARNIER Nicolas GAYRAUD Aurore

Position Position Engineer CNRS at TIMA Laboratory since 2006 Accountant UJF at TIMA Laboratory since March 2013 Current responsabilities System Engineer Current responsabilities In charge of justification research contracts

TIMA Annual Report 2014 - Staff members 93

KHALID Ahmed MARTINEAU Sophie

Position Position Technical Assistant Grenoble INP at TIMA Laboratory Assistant Engineer CNRS at TIMA Laboratory since since 2007 2006

Current responsabilities Current responsabilities System Technician In charge of all the Missions/Travelling administrative points and french teacher for foreign PhD students

SALIZZONI Marie-Christine RAJAB Youness

Position Position Accountant ADR at TIMA Laboratory since January Technician CNRS at TIMA Laboratory since 2000 September 2008

Current responsabilities In charge of all accounting expenses of TIMA Current responsabilities laboratory Accounting of budgets, contracts…..

TORELLA Lucie

Position Adjoint Technique de Recherche et de Formation (UJF) at TIMA Laboratory since 1997

Current responsabilities Secretary / Publications

94 TIMA Annual Report 2014 - Staff members Ph. D. candidates

ACUNHA GUIMARAES, Leonel BOURGE, Alban Title of thesis : : Exploration of new Title of thesis : Hardware Task Context schemes for detection of hardware trojans Switch on FPGA between Heterogeneous Expected date of defense : 2017 Reconfigurable Devices in a cloud-FPGA Previous degrees : Master (Brésil) environment Expected date of defense: 2016 ABBAS, Hassan Previous degrees : Master and Engineer Title of thesis : Design of CMOS color image sensors inspired by human vision BOUSQUET, Laurent Completed on July 04, 2014 Title of thesis : Heterogeneous systems Previous degrees : Master 2R modeling and simulation: SystemC-AMS library extension ALCANTARA DE LIMA, Otavio Completed in January 29, 2014 Title of thesis : Study and implementation of Previous degrees : Master MNE (2009) Future Generation Network features in Embedded systems CHARIF, Amir Expected date of defense : 2015 Title of thesis : Multi-level Robustness Previous degrees : Master (2011) Techniques for Massively Parallel On-Chip Systems AL KHATIB, Chadi Expected date of defense: 2015 Title of thesis : Design of control devices for Previous degrees : Master distributed power management Expected date of defense : 2015 CHEFI, Ahmed Previous degrees : Master Title of thesis : Design of a CMOS image sensor with low power consumption for ANDRAUD, Martin Wireless Sensor Networks Title of thesis : Solutions for the Self- Completed in January 28, 2014 Adaptation of Wireless Systems Previous degrees : Master Expected date of defense : 2015 Previous degrees : Engineer CHERKAOUI, Abdelkarim Title of thesis : Secure True Random BEL HADJ AMOR, Ela Numbers Generators embedded in Title of thesis : Memory hierarchy in asynchronous circuits embedded multiprocessor system built Completed on June 16, 2014 around networks on chip Previous degrees : Master 1 Expected date of defense: 2017 Previous degrees : Master (2013) CHIBANI, Kais Title of thesis : Robustness analysis of digital BEL HADJ AMOR, Zeineb integrated systems Title of thesis : Formal verification of complex Expected date of defense: 2016 Systems on Chip from the Transaction level Previous degrees : Engineer to the Register Transfer Level Completed on December 17, 2014 COLIN, Michael Previous degrees : Master 2 Title of thesis : Design and fabrication of piezoelectric energy scavengers of wide BENHASSAIN, Ahmed frequency band Title of thesis : Management in-situ et Expected date of defense: 2015 endurcissement au vieillissement des Previous degrees : DESS, France (2000) circuits Expected date of defense: September 2017 COSTA MARQUES, Greicy Previous degrees : Master Title of thesis : Study and validation of fault- tolerance software techniques to deal with BERNARD, François errors induced by natural radiation in Title of thesis : Development of new architectures based in advanced processors heterogeneous architectures on silicon Completed on October 14, 2014 dedicated to tactile interfaces Previous degrees : Master Expected date of defense: 2015 Previous degrees : Engineer

TIMA Annual Report 2014 - Ph.D. candidates 95 CUNHA, Marcos GANA, Mohamed Title of thesis : Use of multiprocessor trace Title of Thesis: Méthodes et outils pour for replay, analysis and source code back- l’intégration de structures faible annotation consommation Expected date of defense: 2015 pour circuits intégrés complexes basé sur Previous degrees : Master (2011) un contrôle distribué asynchrone Expected date of defense : 2016 DARWISH, Amani Previous degrees : Engineer Title of thesis : Optimized reading for CMOS vision systems GANG, Yi Expected date of defense: 2015 Title of thesis : Fault Tolerance and Previous degrees : Master 2R congestion management in Network on Chips DIMAKOS, Athanasios Expected date of defense: 2015 Title of thesis : Built-in test in wireless Previous degrees : Master systems using non-intrusive sensors Expected date of defense: 2015 IORDACHE, Mihai Previous degrees : Master (2012) Title of Thesis: Power estimation and reduction in 3D designs DUCROUX, Thomas Expected date of defense : 2016 Title of thesis : Parallel Computing and Power Previous degrees : Master 2R Management on MPSoC Expected date of defense: 2015 JAVAHERI, Negin Previous degrees : Engineer (2011) Title of thesis : Fast prototyping from assertions DUMAS, Julie Expected date of defense: 2015 Title of thesis : Scalable coherent Previous degrees : Master interconnect for heterogeneous computing architectures KACHROUDI, Achraf Expected date of defense: 2017 Title of thesis : Development of new polymer Previous degrees : Master (2014) materials for micro-sensors of vibrations Expected date of defense: 2016 EKOBO AKOA, Brice Previous degrees : Master Title of thesis : Detection and error concealment within a video decoder: Using KAZMA, Rabih techniques based on statistic analysis Title of thesis : Ultra High Sensitive CMOS Completed on October 31, 2014 Imager Previous degrees : Master 2 Expected date of defense: 2016 Previous degrees : Master ELANTABLY, Ashraf Title of thesis : Task migration in Non KEBAILI, Mejid Uniform Memory Architecture(NUMA) as a Title of thesis : Definition of a structural and solution for fault tolerance and thermal functional verification flow for clock domain balance in MPSoC crossing path on high performance Expected date of defense: 2015 integrated subsystem based on processors. Previous degrees : Master Expected date of defense: September 2017 Previous degrees : Engineer FAIX, Marvin Title of thesis : A probabilistic Theory of LAGRAA, Sofiane computation Title of thesis : New MP-SoC profiling tools Expected date of defense: 2017 based on data mining techniques Previous degrees : Master Completed on June 13, 2014 Previous degrees : Master 2 FEI, Richun Title of thesis : Alternative solution to LE PELLETER, Tugdual improve the production test of optical Title of thesis : Energy consumption study sensors in CMOS technology and optimization for Sensor and order Expected date of defense: 2015 functions of an human implant device Previous degrees : Master Expected date of defense: 2015 Previous degrees : Master

96 TIMA Annual Report 2014 - Ph.D. candidates MALLOUG, Hani PASTORELLI, Cédric Title of thesis : Built-in test strategies for Title of thesis : Nonlinear ramp generator for dynamic test of high-performance Analog- analog-to-digital signal conversion in CMOS to-Digital Converters imagers Expected date of defense: 2017 Expected date of defense: 2016 Previous degrees : Engineer Previous degrees : Engineer

MATOUSSI, Omayma PAYET, Matthieu Title of thesis : Simulation of Multi/Many-core Title of thesis : Definition of an integrated SoC: Non-Functional Aspects and emulation environment of Network-on-chip Parallelization designed for an optimized multi-FPGA Expected date of defense: 2017 platform and its evaluation with financial Previous degrees : Engineer (2014) and spectral imaging applications Expected date of defense: 2015 MAXA, Jean-Aimé Previous degrees : Engineer 3i (2011) Title of thesis : Expected date of defense: 2016 PLASSAN, Guillaume Previous degrees : Title of thesis : Semi-formal vérification of clock domain crossing properies MAZET, Kévin Expected date of defense: December 2017 Title of thesis : Monitoring de spécifications Previous degrees : Phelma Engineer Degree temporelles pour la vérification et la sécurisation de logiciel embarqué PONTIE, Simon Expected date of defense: 2017 Title of thesis : Design and validation of a Previous degrees : Master secure crypto-processor for cryptography based on elliptic curves MICHEL, Luc Expected date of defense: 2016 Title of thesis : Using the dynamic binary Previous degrees : : Agregation, Master M2R translation for quick and accurate in Nano-Electronics and Nano-Technology simulation of multiprocessor integrated systems PROST-BOUCLE, Adrien Expected date of defense: 2015 Title of thesis: Génération automatique Previous degrees : Master (2011) d'accélérateurs matériels sur cible reconfigurable via la synthèse d'architecture MKHININI, Asma Completed in January 08, 2014 Title of thesis : Hardware implementation of Previous degrees : Master's Degree in Micro homomorphic encryption and Nano Electronics Expected date of defense: 2016 Previous degrees : Engineer RAMOS, Pablo Title of thesis : Methodology and tools for NAIMI, Aiteb error rate prediction of applications Title of thesis : Study and realization of a implemented in advanced processors prototype needle instrumented by Expected date of defense: 2016 piezoresistive microsensors Previous degrees : Master, Engineer Expected date of defense: 2016 Previous degrees : Master in Physics RENAUD, Guillaume Title of thesis : Built In Self Test of pipeline NJOYAH NTAFAM, Perrin Analog-to-Digital Converters Title of thesis : New performance evaluation Expected date of defense: 2016 methods for early and refined software Previous degrees : Engineer development on SOC platforms Expected date of defense: 2017 RENDON, Adrian Previous degrees : Engineer (2014) Title of thesis : Design and implementation of a piezoelectric micro-generator thermo- PAPAVRAMIDOU, Panagiota magnetically triggered for autonomous Title of thesis : Yield and Reliability in sensors nodes Memories for Late CMOS Technologies Expected date of defense: 2017 Completed on November 19, 2014 Previous degrees : Master (2012) Previous degrees : Master

TIMA Annual Report 2014 - Ph.D. candidates 97

ROLLOFF, Otto Aureliano SIVADASAN, Ajith Title of thesis : Design and evaluation of Title of thesis : Modélisation Spice et standard cells for asynchronous integrated FastSpice du vieillissement de circuit et circuits in low power nanotechnology technique avancés pour gérer la fiabilité par Expected date of defense: 2018 le design Previous degrees : Master (Brasil) Expected date of defense: 2018 Previous degrees : Master SAADE, Julien Title of thesis : A generic approach on TCHUANI TCHAKONTE, Diane system-level for the design of High-Speed Title of thesis : Synchronization and Energy Serial Links Management in Wireless Sensor Networks Expected date of defense: 2015 Expected date of defense: 2016 Previous degrees : Master Previous degrees : Master

SAIF UR, Rehman TERRAS, Lydie Title of thesis : Defect Tolerant SRAM-Based Title of thesis : Audit processor for safe and FPGA: Design For Test and Diagnosis secure embedded systems Expected date of defense: 2015 Expected date of defense: 2017 Previous degrees : Master Previous degrees : Master 2 (2014)

SALIVA, Marine TRIOUX, Emilie Title of thesis : Dynamic and statistical Title of thesis : Development and 3D reliability modeling assessment and integration of piezoelectric materials for circuit/system reliability modeling & energy harvesting applications monitoring enabling Expected date of defense: 2015 Expected date of defense: september 2015 Previous degrees : Engineer (2011) Previous degrees : Engineer VARGAS, Vanessa SARRAZIN, Guillaume Title of thesis : Software Environment for the Title of thesis : Nativesimulation technics for development of reliable concurrent many-core systems applications on multi-core and many-core Expected date of defense: 2016 platforms Previous degrees : Engineer Expected date of defense: 2016 Previous degrees : Master (2007), Engineer SCHWAMBACH COSTA, Vitor (2002) Title of thesis : Generic Multiprocessor Architectures for Efficient Implementation of XU, Yan Video Analysis Algorithms Title of thesis : Lightweight software Expected date of defense: 2015 management for partial dynamic Previous degrees : Master reconfiguration Completed on March 13, 2014 Previous degrees : Master

98 TIMA Annual Report 2014 - Ph.D. candidates Others members of TIMA

Post-Doctoral position and Engineers

NAME FORENAME POSITION GROUP ALHAKIM Rshdee POSTDOC RMS BERGAOUI Salma ATER ARIS BOUHADDA Ismail POSTDOC MNS BULLICH Adrien ATER SLS CHABOT Martial Contracted Engineer VDS CHAIX Fabien POSTDOC ARIS CHEFI Ahmed Contracted Engineer CIS CHEFI Ahmed POSTDOC CIS DESCHAMPS Clément Contracted Engineer SLS DIMOPOULOS Michael POSTDOC ARIS GORISSE Marie POSTDOC MNS KOUMELA Alexandra POSTDOC MNS LAGRAA Sofiane ATER SLS MAMEESH Rania POSTDOC SLS MANSOUR Wassim POSTDOC ARIS MORTIER Quentin Contracted Engineer MNS POUJAUD Julien ATER CIS PROST-BOUCLE Adrien POSTDOC SLS RIPERT Etienne Contracted Engineer SLS TEMANI Afif Contracted Engineer SLS VALKA Miroslav POSTDOC RMS VANHAUWAERT Pierre Contracted Engineer ARIS VINCENT Lionel POSTDOC SLS

Visitors

NAME FORENAME COUNTRY DURATION HANNACHI Oumelkheir ALGERIA 14 days

TIMA Annual Report 2014 - others members of TIMA 99

Trainees

NAME FORENAME COUNTRY DURATION GROUP ARSLAN Cansu TURKEY 6 months 23 days CIS AUPETIT Claire FRANCE 2 months 23 days CIS BAILLE Mathieu FRANCE 3 months 13 days VDS BAUMELA Thomas FRANCE 6 months 15 days SLS BECKER Denis FRANCE 4 months 22 days SLS BEILLIMAZ Cyril FRANCE 2 months ARIS BENIER Clément FRANCE 4 months 22 days SLS BERTHIER Sébastien FRANCE 6 months 23 days SLS BONDO Francis CONGO (Kinshasa) 4 months 7 days VDS CAPUTO Nicolas FRANCE 11 months 23 days TIMA CHAABANI Nesrine TUNISIA 2 months 5 days ARIS CHAHED Amine TUNISIA 5 months 11 days ARIS CHARIF Amir ALGERIA 4 months 30 days ARIS CHOUCHENE Rami TUNISIA 5 months 17 days ARIS D'ANGELO Claudia ITALY 10 months 28 days SLS FARAVELON Antoine FRANCE 8 months 12 days SLS FARAVELON Antoine FRANCE 9 months 21 days SLS FARIAS PUHL Luciano BRAZIL 3 months 30 days VDS FERRAFIAT Jérôme FRANCE 3 months 13 days VDS GUIMARD Lénaïc FRANCE 4 months 8 days VDS JOUBERT Arnaud FRANCE 4 months 7 days VDS KHAOULA Dahdeh TUNISIA 4 months 28 days VDS KIEFFER Arthur FRANCE 3 months 9 days VDS LEFRERE Jules FRANCE 3 months 13 days VDS MAITY Biswadip INDIA 1 month 29 days ARIS MAKHLOUF Mehdi FRANCE 6 months 16 days VDS MATOUSSI Omayma TUNISIA 6 months SLS MAZET Kévin FRANCE 7 months 23 days VDS MENDES FERREIRA Iverson BRAZIL 2 months 26 days VDS MESTIRI Hassen TUNISIA 2 months 30 days ARIS REGAIEG Younes TUNISIA 7 months 1 day SLS ROCHA Leandro BRAZIL 2 months 23 days CIS ROLLOFF Otto Aureliano BRAZIL 6 months 1 day CIS SELLAMI Hamza TUNISIA 4 months 19 days ARIS TEMANI Afif TUNISIA 6 months SLS VIGNAL Christophe FRANCE 3 months 13 days VDS VINCHON Arthur FRANCE 1 month 30 days SLS XIE Zhuofan CHINA 3 months 9 days SLS ZHU Haoshen CHINA 3 months 13 days MNS ZIANE-CHERIF Amine FRANCE 7 months 16 days VDS

100 TIMA Annual Report 2014 - others members of TIMA

Contracts

TIMA has a long tradition of international cooperation, both with industrial and academic partners in the context of multinational projects. This chapter provides a short abstract of the topics and objectives of the contracted partnerships that were active in 2014.

ANR faulty behavior. For instance, in so-called ARPEGE / EMAISeCI project - Analyse et Differential Fault Analysis (DFA), an attacker can Injection Electromagnétiques sur circuits deduce the secret key used in the crypto- sécurisés algorithms by comparing the faulty result and the (Oct 01, 2010 - Jan 29, 2014) correct one. The main goals of this project are : 1. Partners: Université de Montpellier II (Sciences to study and model the effect of laser shots onto Techniques du Languedoc), Ecole Nationale submicronic circuits and 2. to provide efficient Supérieure des Mines de Saint Etienne, tools to circuit designers to prevent such laser Université de Saint Etienne, Commissariat à attacks. For that, a first sub-goal is to model the l'Energie Atomique et aux Energies Alternatives effect to laser shots onto deep submicron (Centre de Grenoble), ST MICROELECTRONICS integrated circuits and to derive electrical and (Rousset) SAS. logico-temporal fault models that can be used in a The security constitutes a crucial component of design flow. A second goal of this project is to Media and Communication technologies. Among develop tools helping the designers to validate the threats, the vulnerability of the electronic their solutions against laser injections without material which implements cryptography is neither actually having access to expensive laser perhaps most important. Among the most known equipment, nor to fabricate ICs. These tools will attacks, those called by "side channels" (or allow simulating the laser effects on the basis of observation), exploit the correlation between the the laser fault moldels developed within the handled data and the consumption or the project itself ; the designers will thus benefit from electromagnetic radiation of the component. the possibility to evaluate soon in the design flow Another type of attacks, called by "injection of the behavior of the systems with respect to the faults" circumvents protections intended to protect different parameters and variables highlighted the sensitive information, while modifying the during the experimentation campaigns. In order to operation of the component. The objective of the accelerate the evaluation process, emulation will EMAISeCi project is to allow a theoretical be taken into account : generic tools are already comprehension of the influence of EM (for the available at the partners and they will be refined observation or the injection of faults) on integrated and adapted to the results obtained during the circuits. This comprehension will later on make it project. A third goal is to anticipate new attacks possible to build counter measures dedicated to based on the effects on these advanced the emergent threats on security based on the technologies and thus to propose counter- exploitation of the EM channel. measures for near-future circuits. A final objective of this project in the exploitation of the data Ingenierie Numérique pour la Sécurité (INS) / collected during the experimental campaings : the LIESSE project - Effets laser et fautes sur les derived error models will be the basis for the circuits intégrés dédiés à la sécurité (Oct 01, definition of new attacks to secured cryptographic 2012 - Mar 31, 2016) systems. Partners: Université de Montpellier II, EC. NAT. SUP. des MINES ST-ETIENNE, Office National Ingenierie Numérique pour la Sécurité (INS) / d'Etudes et recherches Aérospatiales, ROBUST project - Concevoir un FPGA robuste STMicroélectronics (Crolles 2) SA, TIMA/INP tolérant aux défauts intégrant le test et le Several means of attacking integrated circuits are diagnostic (Oct 01, 2011 - Mar 15, 2015) reported in the literature (for instance analysis of Partners: INSTITUT TELECOM, Université PARIS the computation time, of the correlation between VI (Pierre et Marie Curie), TIMA / Grenoble-INPG the processed data and the current consumption, Le défi auquel le projet veut répondre est de of electromagnetic emanation, of the noise pouvoir utiliser des circuits tout en tolérant la caused by the emitted photons, etc.). Among présence de défauts physiques. La réponse à ce them, laser illumination of the device has been défi aura des répercussions sur les modèles des reported to be one important and effective mean dispositifs, l’architecture, la sûreté de to perform attacks. The principle is to illuminate fonctionnement, la sécurité et les outils de CAO. the circuit by mean of a laser and then to induce a Les circuits reconfigurables de type FPGA connaissent un succès croissant car leur TIMA Annual Report 2014 – Contracts 101

performance et leur capacité d’intégrer des rapport à une trajectoire idéale nécessite le applications très complexes ont directement développement de nouvelles modalités de bénéficié de l’évolution technologique. Ces correction, en temps réel, des trajectoires de circuits accroissent en permanence leur part de l’aiguille. marché relativement aux ASIC. Les partenaires Un consortium d’experts a été constitué pour de ce projet unissent leurs compétences pour relever ces défis : TIMA (Techniques de étudier une nouvelle architecture FPGA à base de l’Informatique et de la Micro-électronique pour SRAM tolérante aux défauts physiques. Pour l’Architecture des systèmes intégrés), qui apporte pouvoir exploiter cette architecture, des outils de son savoir-faire en micro-fabrication et micro- configuration seront développés, permettant capteurs, a démontré la faisabilité d’une nouvelle contourner les blocs contenant des défauts modalité d’appréhension des déformations d’une physiques et de projeter les applications sur les aiguille. 3S-R (Sols, Solides, Structures, Risques) blocs sains. Le projet comportera 4 volets apporte au consortium son expertise dans le principaux: - Amélioration de la tolérance aux domaine de la physique et mécanique du défauts du FPGA par l'amélioration de la comportement des matériaux et a démontré la robustesse de ses blocs de base. - faisabilité à contraindre activement la déformée Développement de méthodes de test et diagnostic d'une aiguille. TIMC-IMAG (Techniques de afin de générer une cartographie des ressources l’Ingénierie Médicale et de la Complexité - défectueuses. - Développement d’un outil de Informatique, Mathématiques et Applications de synthèse en vue de la tolérance aux défauts de Grenoble) spécialisé dans les systèmes de FPGA. - Développement d’outils de configuration navigation et les gestes médico-chirurgicaux du FPGA tolérant les défauts. Les retombées assistés par ordinateur, propose une nouvelle scientifiques et techniques de ce projet sont le génération d'environnement augmenté. Le CIC-IT développement d’une architecture innovante de (Centre d’Investigation Clinique – Innovation FPGA tolérante aux défauts avec l’introduction de Technologique) du CHU de Grenoble apporte son la notion de synthèse en vue de la robustesse. savoir-faire dans le domaine de Les industriels pourront exploiter les résultats de l’accompagnement de la maturation d’innovations cette étude aussi bien pour les FPGA autonomes technologiques en Santé en vue de déterminer que pour ceux embarqués dans les SoC. En effet, objectivement et précocement les Services les SoC intégreront de plus en plus des blocs Médicaux Attendus associés aux innovations flexibles et reconfigurables en fonction des développées dans le projet. IMACTIS, PME applications à exécuter. spécialisée dans le domaine de la radiologie interventionnelle, apporte son expertise dans le TechSan / GAME-D project - Guidage d'une développement et l'industrialisation de systèmes Aiguille Médicale instrumentéE Déformable de navigation d'aiguilles sur le marché de la (Feb 01, 2013 - Oct 31, 2016) radiologie interventionnelle. La fédération de ces Partners: Université Grenoble I (UJF), CNRS DR- experts au sein d’un même consortium permet de ALPES, Centre Hospitalier Universitaire de couvrir l’ensemble des spécialités (médico-légale, Grenoble IMACTIS. radiologie, logiciel, modélisation, électronique, Les procédures médicales percutanées, guidées micro-système, commande, mécanique, médico- ou non par une imagerie, ont bénéficié des légal) nécessaires pour relever les deux apports des outils de localisation et de navigation. précédents défis. Néanmoins, ces outils restent imparfaits. Dans le Au terme de ce projet de recherche industrielle, cadre de procédures percutanées utilisant une l’ensemble des éléments scientifiques et aiguille, nous voulons démontrer que l’on peut techniques, ainsi que deux premiers offrir au radiologue interventionnel un démonstrateurs, seront disponibles pour valider la environnement augmenté qui lui permettra, d'une faisabilité de l’approche envisagée. Les enjeux part, de répondre à sa problématique de sont perçus comme extrêmement stratégiques, en maximisation du rapport bénéfice/risque et d'autre particulier dans le domaine de la radiologie part, de repousser ses limites dans la réalisation interventionnelle. Nous pensons qu’au moins six de gestes jusqu'à ce jour non envisagés du fait publications majeures seront générées par le d'outils insuffisamment performants. consortium. Enfin, le transfert industriel de ces Deux défis majeurs doivent être relevés pour innovations sera facilité par le partenaire concevoir la nouvelle génération d'outils IMACTIS, qui commercialisera les produits issus d’assistance à la réalisation de gestes de de ces travaux au travers de son réseau de radiologie interventionnelle guidés par une distribution. imagerie. 1/ L’hypothèse simplificatrice d'un modèle d'aiguille linéaire peut être source SACSO project - Solutions pour l'auto- d'imprécisions majeures, pouvant ainsi entraîner adaptation in-situ de systèmes communicants des échecs du geste interventionnel, les (Jan 01, 2012 - Nov 30, 2015) nouveaux systèmes de navigation doivent donc Partners: CNRS Délégation régionale prendre en compte, en temps réel, les LANGUEDOC-ROUSSILLON, NXP, SEMICON- déformations de l'aiguille. 2/ La connaissance de DUCTORS France, TIMA / Grenoble INPG ces déformations et donc des déviations par 102 TIMA Annual Report 2014 – Contracts

Dans le contexte de systèmes très performants et fréquences (10 kHz - 1 MHz) (Feb 01, 2011 - Jul des applications critiques, l'objectif du projet est 31, 2014) de concevoir des Systèmes Auto-adaptatifs Partners: Université de Montpellier II (Sciences capables de prendre en compte leur Techniques du Languedoc), Ecole Centrale de environnement proche et de s'adapter à différents Lyon, TIMA/INP Grenoble-INPG, MICROSONICS scénarios. Dans ce projet, nous adressons deux The objective of this project is to develop an cas d'auto-adaptabilité jusqu’à maintenant non- original sensor for accurate measurements of traités: auto-adaptation à l'application et auto- airborne acoustic pressures in a wide frequency adaptation à l'environnement. 1. Auto-adaptation range (10 kHz to 1 MHz) and high-pressure levels à l'application: le fonctionnement d'un système (up to 4 kPa). Such high-frequency microphone entier dans l'application est limité par le with flat and calibrated frequency response is not fonctionnement de chaque composant. yet commercially available, which limits some Malheureusement, le fonctionnement des advances in the field of aeroacoustics and composants individuels est dans la plupart des nonlinear acoustics. The main project output will cas optimisé pour une grande gamme de be a demonstrator consisting of a sensor itself systèmes ou d’applications et pas pour un associated with a full-custom front-end electronics système ou une application spécifique. and a calibration procedure. To overcome this L'originalité de l'approche proposée dans ce projet technical challenge, micro-electronics and micro- consiste à 'prévoir' l'intégration du système au systems (MEMS) technology will be used. moment de la conception des composants. Le composant est alors conçu avec un Circuit d'Auto- BPI FRANCE adaptation intégré, qui permet au composant de FUI AAP 17 / SPICA project - Safety/Security- modifier ses caractéristiques électriques en toute Oriented Post Instrumentation of Circuits with autonomie une fois qu’il est placé dans Assertions (Mar 26, 2014 - Sep 30, 2017) l'application, de façon à pouvoir optimiser le Partners: UNIVERSITE de BRETAGNE SUD fonctionnement du système entier. 2. Auto- DOLPHIN INTEGRATION adaptation à l'environnement: le fonctionnement STMICROELECTRONICS ROUSSET SAS du système dépend aussi des changements de Le projet SPICA vise une solution innovante pour l'environnement; par exemple un téléphone les domaines de la vérification, de la sûreté et de portable communique différemment lorsqu’un la sécurité des systèmes critiques. L'objectif est le obstacle est placé dans son environnement et développement de méthodes et outils pour vient perturber son comportement. Dans ce cas, l'instrumentation automatique des systèmes sur le composant pourvu d’un Circuit d'Auto- puce complexes critiques par des composants adaptation peut changer lui-même ses dédiés à la vérification d'exigences de bonne caractéristiques électriques en fonction de conception, la sécurisation du dispositif, et la l'environnement pour optimiser le fonctionnement détection de dysfonctionnements et de du système. Le contexte d'e-santé est utilisé malveillance en opération. L'originalité de comme démonstrateur; le projet se concentre sur l'approche proposée réside dans le fait qu'elle la télésurveillance pour laquelle le patient est décline et exploite des concepts similaires dans équipé d'un capteur qui communique avec un les trois principales composantes de la dispositif électronique externe jouant le rôle d'une conception: le système global, le logiciel passerelle vers une infrastructure de réseau. embarqué, et les blocs matériels dédiés. Dans ce projet, nous développons des solutions génériques pour l'adaptation statique et FUI AAP 17 / LISA project - "Ultra low power dynamique d’un dispositif médical utilisé dans des Integrated circuit for Secure RF" (Mar 26, 2014 systèmes de télésurveillance. Nous avons - Sep 25, 2017) identifié trois cas majeurs dans les dispositifs Partners: DOLPHIN INTEGRATION SMART électroniques médicaux : dispositifs avec “front- PACKAGING SOLUTIONS UNIVERSITE D'AIX end” passif, dispositifs avec “front-end” actif et MARSEILLE MORPHO STARCHIP gestion de la puissance consommée. L'objectif de ce projet est d'adresser ces trois cas. Tous les FUI (Fonds Unique Interministériel) / ALTIDE développements seront validés sur deux project - Aide à la Traçabilité Inelligente des prototypes : un circuit NFC pour illustrer un Equipements (Aug 01, 2011 - Sep 30, 2014) exemple de “front-end” passif et une pilule Partners: ECOLE NAT SUPER MECANIQUE électronique pour illustrer un exemple de “front- MICROTECHNIQUE, ALTIM, LES TLESKIS DE end” actif et de la gestion de la consommation. LA CROIX FRY, PICDI Ce projet prépare l’introduction sur le marché SIMMIC project - Microphone de mesure large d’une solution de monitoring basée sur des bande en silicium pour l'acoustique en hautes solutions mécatroniques communicantes autorisant la surveillance en temps réel des TIMA Annual Report 2014 - Contracts 103

installations de remontées mécaniques des INSTITUT POLYTECHNIQUE DE BORDEAUX domaines skiables. La rigueur des conditions CNRS (Marseille) environnemantales, l’exigence de fiabilité et de This project aims at developing optimised durée de vie, 30 ans, de ces installations sont à mitigations for advanced digital and power l’origine d’un ensemble de verrous technologiques electronic systems in order to solve the major à lever. Le résultat est une solution innovante et issue of their reliability against the increasing intelligente à la croisée de la traçabilité et de l’e- problem of soft, firm and hard errors. To reach this maintenance pour les composants de sécurité et goal, end-users, semiconductor manufacturers des contrôles effectués sur les installations. are associated with technology developers and European academic partners. The expected BPI-France ex OSEO deliverables are a set of validated mitigation FUI (Fonds Unique Interministériel)/ COVADEC techniques from layout to applications architecture project - COnception et VAlidation Des levels, customised mitigations for given Systèmes Embarqués d'Aide à la Conduite applications and a strong effort in standardisation. (Sep 18, 2013 - Aug 30, 2016) The expected benefits will be the capability to use Partners: ALL4TEC, CIVITEC, INTEMPORA, advanced electronics in critical end-user MAGILLEM, PEUGEOT CITROEN applications, and ensure reliability of consumer AUTOMOBILES SA, VALEO ETUDES electronic, especially for low power. ELECTRONIQUES, ARMINES Laboratoire, GRENOBLE-INP/TIMA E2V Projet consistant à développer un ensemble de E2V project - "ESSAIS SOUS NEUTRON, méthodes et techniques permettant la Conception rapport de TESTS" (Feb 03, 2014 - Feb 04, et la Validation des systèmes Embarqués d'Aide à 2014) la conduite automobile en conformité avec la Partners: E2V norme ISO 26262 GRENOBLE INP CAISSE DE DEPOT ET CONSIGNATIONS BQR 2011 "PHAMM" project - Déphasage ACOSE project - (Dec 01, 2011 - Dec 01, 2014) accordable aux fréquences millimétriques (Jan Partners: MAGILLEM DESIGN SERVICES, 28, 2014 - Jan 31, 2014) CYBERIO, UJF - Laboratoir VERIMAG, CEA-LETI Partners: GRENOBLE INP BQR en partage avec ACOSE va développer un atelier de l'IMEP-LAHC-TIMA développement rigoureux, permettant de PHAMM "Déphasage accordable aux fréquences concevoir et représenter les systèmes selon millimétriques : utilisation de lignes de différent niveaux de détails, depuis le logiciel propagation coplanaires à ondes lentes et applicatif jusqu'à son implémentation sur une ou accordables" plusieurs plateformes. (appel à projet FSN: Briques Génériques du Logiciel Embarqué). MINISTER CATRENE / RESIST project - RESilient DGCIS Integrated Systems (Sep 01, 2014 - Aug 31, CATRENE / BENEFIC project - Besst ENergy 2017) EFficiency solutions for heterogeneous multi- Partners: STMMicroelectronics (CROLLES2) SAS core Communicating (Jul 01, 2013 - Sep 30, STMicroelectronics SA IROC TECHNOLOGIES 2016) ISEN-TOULON ATMEL NANTES SA Partners: ST Microélectronics (GRENOBLE 2) Les systèmes électroniques des voitures et des SAS, ATRENTA France SAS, ST Microélectronics avions deviennent de plus en plus sophistiqués et SA, Commissariat à l'Energie Atomique et aux nécessitent toujours plus d'intégration et de Energies Alternatives THALES RESEARCH AND performances. Cependant, l'utilisation de TECHNOLOGY THALES COMMUNICATION & technologies fortement intégrées compromet la SECURITY SAS CNRS MOY2000 COTE D'AZUR fiabilité, la sécurité et la durée de vie des Fournir une approche holistique intégrant de systèmes. Il faut donc de nouvelles approches et nouvelles sources de récupération d'énergie solutions de design qui prennent en compte ce ("Harvesting Energy) et des approches novatrices besoin de fiabilité. Le projet RESIST vise ces de distribution d'énergie pour nos systèmes. méthodes de design ainsi que des méthodes d'adaptation en temps réel pour la prochaine DGCIS/STSI génération de systèmes électroniques durcis, CATRENE / OPTIMISE project - Optimisation of résistants et adaptatifs pour en particulier Mitigation for Soft firm and hard Errors (Jul 01, l'automobile, l'avionique et l'aérospatial. RESIST 2009 - Jun 30, 2014) se concentre sur la fiabilité, la résilience, le coût et Partners: EADS France, AIRBUS OPERATIIONS, la qualité des circuits à base de semi- ATMEL NANTES SA, STMICROELECTRONICS conducteurs. (TOURS) SAS, VALEO Etudes Electroniques, CONTINENTAL AUTOMOTIVE France, REGIENOV, IRoc TECHNOLOGIES, CEA,

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MINISTERE et EUROPE de vie limitée, nécessitant le remplacement de ENIAC / ELESIS project - European Library- l’implant lors d’une intervention chirurgicale tous based flow of Embedded Silicon test les 4 ans en moyenne. L’idée est de récupérer Instruments (Jun 01, 2012 - May 31, 2015) l’énergie présente dans l’environnement immédiat Partners: NXP SEMICONDUCTORS France, ST des stimulateurs cardiaques pour les alimenter MICROELECTRONICS (GRENOBLE 2) SAS, afin de les rendre autonomes. L’auto-alimentation ATMEL NANTES SA, CEA, IROC de ces stimulateurs cardiaques limiterait TECHNOLOGIES, CNRS/DELEGATION l’intervention chirurgicale à l’implantation initiale. LANGUEDOC ROUSSILLON, TEMENTO Le plus gros défi scientifique et technologique du SYSTEMS, INFINEON TECHNOLOGIES projet est de développer un microgénérateur d’un AUSTRIA, INPG/TIMA, INESC PORTO, volume maximal de 0.5 cm3 qui fournisse 40µW à UNIVERSITEIT TWENTE, D4T SYSTEMS, JTAG partir de l’énergie mécanique de la contraction TECHNOLOGIES B.V. cardiaque stimulée ou spontanée, ou encore du The ELESIS project is focused on improving the glissement du cœur sur les tissus environnants. industrial test infrastructure for Integrated Circuits, Nous disposons dans le consortium de toutes les leading to safe, reliable, high quality and low cost compétences techniques et médicales semiconductors products in Europe. The project is nécessaires au développement et à la fabrication relevant to the Design Technologies domain and du microgénérateur, de l’électronique, du is addressing the Grand Challenges managing micropackaging et de la mécanique pour réaliser complexity, managing diversity and design for un stimulateur cardiaque d’une taille de 1 cm3 reliability and yield. ELESIS is a very ambitious vissé sur l’épicarde. project which plans to cover the mentioned targets (Safety, reliability, high quality and low cost) for OSEO mixed signal circuits in addition to digital, with OSEO / HICOOL project - Solutions amont special focus on Analog, RF and Sensors. The pour la conception orientée basse ELESIS project will also target a European consommation de circuits intégrés complexes Standard Interface to reduce test complexity and (Aug 01, 2012 - Sep 30, 2016) to manage access to the internal IP blocks from Partners: ST Microélectronics (Grenoble2) SAS, the top level IC. We will address the most DEFACTO TECHNOLOGIE, DOCEA POWER, important aspects of semiconductor testing within CNRS, GRENOBLE-INP/TIMA a framework of so-called “embedded test L’objectif du projet est d’améliorer le processus de instruments” controlled through a common conception des systèmes sur puce exigeant une interface that is needed to ensure the best forte maîtrise de leur dissipation de puissance. solutions to reach our challenging targets. The L’appareillage nomade, le calcul intensif et les proposed standard interface will have a large infrastructures de télécommunications, tireront economic impact by the creation of an Open profit des solutions issues de ce projet. Les Source Platform, which could be used by IP, IDM bénéfices attendus sont une meilleure productivité and Fabless companies in Europe and even des équipes de conception et une qualité accrue worldwide. des circuits développés vis-à-vis de leur consommation. L’innovation soutenue par le MINISTERE, POLES COMPETITIVITE projet consiste à briser le cloisonnement existant OSEO / HBS project - Heart Beat Scavenger entre des niveaux du processus de conception en (Sep 01, 2010 - Aug 31, 2014) usage, et plus particulièrement entre d’une part le Le but du projet HBS est de réduire d’un facteur 8 niveau architectural, propre à définir l’agencement la taille d’un stimulateur cardiaque. La taille des composants d’un circuit, et d’autre part les minimale obtenue à ce jour est de 8 cm3 et celle niveaux RTL et portes logiques, où visée dans le cadre de ce projet est de 1 cm3. l’implementation d’un circuit est menée. Dans ce Cette réduction de taille permettra : o de fixer le cadre, des techniques automatisées portant sur stimulateur directement sur l’épicarde en les aspects d’estimation de la consommation, de thoracoscopie évitant ainsi l’utilisation de sondes vérification des représentations du circuit et par voie veineuse qui sont source d’infection, de d’insertion de structures dites de “low power” défaillance o d’optimiser la position de l’électrode seront proposées. Elle seront unifiées par un flot de stimulation sur le ventricule gauche essentielle formalisé, ascendant et descendant, centré sur le à une thérapie de resynchronisation cardiaque niveau architecture et couvrant en complément efficace chez l’insuffisant cardiaque Pour toutes les niveaux RTL et portes logiques. En ces raisons, nous entrevoyons le futur de la comparaison, les solutions de conception stimulation cardiaque à terme sans sonde. Les actuelles, relativement à la consommation stimulateurs cardiaques sont actuellement d’énergie, forment une succession de tâches alimentés par des piles implantées représentant disparates, fortement manuelles dans le sens environ le tiers du volume du système et de durée ascendant du flot, et centrées au niveau RTL. TIMA Annual Report 2014 - Contracts 105

Grâce à la mise en place d’un flot structuré et STM composé de tâches cohérentes, une réduction Contrat de collaboration d'Emmanuel SIMIEU d’un facteur 10 du temps consacré aux aspects project - "Etude des systèmes de détection basse consommation dans la partie amont du d'erreurs et compensation intégrées dans le cycle de conception est ainsi envisagée. Ceci se décodeur vidéo numérique appuyant sur des traduira par une compétitivité significativement techniques d'analyse statistique" (Apr 02, 2012 améliorée sur le marché des systèmes sur puce à - Apr 01, 2015) faible dissipation de puissance. Partners: ST Microélectronics (Grenoble2) SAS, Grenoble INP & INPG Entreprise SA OSEO / TOUCHIT project - Tactile Open Usage With the evolution of multimedia technologies and with Customized Haptic Inter face Technology requirements in quality of images being viewed by (Mar 01, 2012 - Feb 28, 2015) users, digital video decoders must provide Partners: MENAPIC, ALPHAUI, satisfactory quality to decoded video. . Then a STMicroélectronics (Crolles2) SAS, INRIA (Inst. new challenge arises which consists to ensure the National Recherche Inform. Autom), CEA, Univ. best perceptual quality as possible to images at Sciences Technologies LILLE, France TELECOM, the output of multimedia devices, regarding to EASII IC, STMicroélectronics SA human visual perception. We then attempt to Né d’un challenge d’innovation interne à establish supervision loop of visual quality within a STMicroelectronics, le projet TOUCHIT porte sur digital video decoder. le développement d’une solution pour ajouter la In modern video decoders, concealment of notion de retour haptique à tout système avec un artifacts is mainly processed during a post écran tactile grand public (téléphonie, ordinateur processing stage in the time domain. These portable, tablette PC, touch pad, concealment methods seem to be reaching their télécommande…). Par définition, l’haptique est la limits due to the complexity of sequential systems science du toucher. Dans le cadre du projet, nous architecture. Incorporating a monitoring and appellerons haptique la notion de rendu de conciliation process faithfully with the human texture, contour de forme, relief… La volonté du visual system into the video decoding loop is projet est de révolutionner le domaine des écrans becoming a key challenge for the video decoder tactiles et ceci en suivant plusieurs axes : - designers. This research program consisted in l’implémentation d’une solution de retour haptique studying the error detection and compensation unique, offrant une finesse de restitution tactile systems integrated into a digital video decoder jamais atteinte ; - le développement d’une based on advanced statistical analysis plateforme silicium combinant des technologies techniques. The goal is to develop a video quality de dépôt de couches piézoélectriques et des assessment algorithm which enables real-time solutions de packaging par report puce à puce ; - monitoring of video quality for standardized video la définition de nouvelles applications decoders such as H.264 and achieve satisfactory embarquées avec comme finalité une meilleure correlation with judgment of human observers. interaction homme-machine, plus intuitive, ludique One of the main contributions of the project is the et efficace grâce à la compréhension des supervision of a Multimedia system by a video mécanismes psychophysiques liés au frottement. Quality Monitoring Tool (VQMT) strongly correlated with human visual perception aiming to RRA ensure a high level of visual quality of decoded UROMENS 2011-2013 project - (Jan 27, 2011 - images. Apr 07, 2014) Partners: RRA, TIMA/UJF UROMEMS Création d'entreprise de dispositifs médicaux UROMEMS 2011-2013 project - Etude de UroMEMS se consacre au lancement d'un produit faisabilité portant sur des briques : le Sphincter Urinaire Artificiel (SUAA) pour le technologiques utiles au développement d'un traitement de l'incontinence urinaire masculine sphincter urinaire artificiel (Jul 18, 2011 - Jan 17, 2014) Partners: UROMEMS SAS, ADR/TIMA

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University/industry joint research programs

The CIFRE program allows French companies to hire and host Ph.D. students. The thesis director must belong to a French University or public research laboratory. The research theme of the thesis must be of common interest to the company and the laboratory. TIMA researchers are active in the CIFRE program, and have advised the Ph.D. theses listed in the table below.

Company/Institute Student Dates Theme

ST Microélectronics (Grenoble 2) Ahmed Dec 2013 Management in-situ et endurcissement SAS, TIMA / INPG SA BENHASSAIN Dec 2016 au vieillissement des circuits Système de conversion analogique / STMicroélectronics (Grenoble 2) Cédric Feb 2013 numérique auto-testable à base de SAS, GRENOBLE INP & INPG PASTORELLI Feb 2016 technique Sigma-delta adaptée aux ENTREPRISE SA capteurs d'images CMOS ST Microélectronics SA, Ecole Développement et intégration en 3D de Polytechnique Fédérale de Jun 2012 Emilie TRIOUX matériaux piézoélectriques pour les LAUSANNE, UJF/Laboratoire Jun 2015 applications de récupération d'énergie TIMA, FLORALIS Développement de nouvelles ST Microélectronics (Crolles 2) François Dec 2012 architectures sur silicium hétérogènes SAS, FLORALIS / TIMA BERNARD Dec 2015 dédiées aux interfaces tactiles vibrantes Dynamic and statistical reliability ST Microélectronics (Crolles2) Oct 2012 modeling assessment and circuit/system Marina SALIVA SAS, TIMA/INPG SA Sep 2015 reliability modeling & monitoring enablement Université Jean Mone (UJM) Fabrication d'un prototype de plateforme Laboratoire Curien, CNRS, May 2012 pour l'émulation de NoC et sur un Matthieu PAYET UJF/Laboratoire TIMA, Floralis, May 2015 environnement d'aide à la conception, Sté ADACSYS exploration et évaluation du système ST Microélectronics (Crolles2) Solutions alternatives pour améliorer les Jan 2012 SAS, Grenoble INP & INPG Richun FEI tests de production des capteurs Jan 2015 Entreprise SA optiques en technologie CMOS Méthodologie d'évaluation de la Sabine May2010 EADS France, TIMA/INPG SA sensibilité des microprocesseurs vis-à- HOUSSANY Apr 2013 vis des rayonnments cosmiques ST Microélectronics (Grenoble 2) Victor Architectures multiprocesseurs Aug 2012 SAS, GRENOBLE INP & INPG SCHWAMBACH génériques pour la mise en oeuvre Jul 2015 ENTREPRISE SA COSTA efficace d'algorithme d'analyse de vidéos STMicroelectronics (Rousset), Nov. 2014 Audit processor for safe and secure GRENOBLE INP & INPG Lydie TERRAS Oct. 2016 embedded systems ENTREPRISE SA

TIMA Annual Report 2014 - Contracts 107

108 TIMA Annual Report 2014 – Contracts International activities

This section gives an overview of international activities in which the members of the Laboratory participated.

International cooperation agreements

The Laboratory is engaged or has been recently engaged in a number of cooperations, some of them being officially recognized. They are listed below. These cooperations took various forms, e.g. extended visits of researchers at the cooperative location, organization of joint research, organization of workshops, etc.

TEAM 1 : Architectures for robust and complex integrated systems International cooperation agreements

§ Ain Shams University, Cairo, Egypt (2011-2014) This cooperation is part of a larger cooperation agreement between Grenoble INP and Ain Shams University. It Master internships in TIMA for Egyptian students from Ain Shams, and the co-tutorship of PhD thèses, in the domain of Microelectronic design and CAD. The responsible academic persons are Prof. Ashraf Salem Farghaly from Ain Shams, Prof. Dominique Borrione and Prof. Regis Leveugle from TIMA. § Pontificia Univ. Católica de Perú (PUCP), Instituto de Estudios Avanzados (IEaV) Brazil Comisión Nacional de Energía Atómica (CNEA) Argentina, ONERA France (2012-2014) Title: High Altitude Remotely Monitored Lab. for the Evaluation of the Sensitivity to SEUs. Program: STIC-AMSUD, Leaders: C. Silva Cardenas (PUCP), C. Federico (IEAV), J. Ruzzante (CNEA), G. Hubert (ONERA), R. Velazco (TIMA). § Technical University of Wien (2013-2014) Coopération dans le cadre d'un projet européean COST MEDIAN concernant l'étude des effects de la radiation sur les circuits asynchrones. (L. Anghel) § Politecnico di Torino, Dept. of Mechanical and Aerospace Engineering (2014) Title: Microstructures Integration to Sensors for Telemedicine Networks (MISETEN) Programme: Galileo-PHC (Partenariats H. Curien) Leaders: Giorgio De Pasquale (Polito), L. Rufer (TIMA) § Ecole Nationale d'Ingénieurs de Sousse (ENISo), Sousse, Tunisia and Faculté des Sciences de Monastir (FSM), Monastir, Tunisia (from 2012) This cooperation involves exchanges and collaborations both on research and teaching sides. In terms of research, a co-tutelle thesis has been started in 2014 between TIMA and the laboratory of Electronics and Microelectronics (LEµE) at FSM. A PhD student at LEµE come also at TIMA for a 3-month period in 2014. In terms of teaching, R. Leveugle was invited in June 2013 to contribute on a review of curricula at ENISo. He was also invited in November 2013 to teach a course on hardware security for two departments of ENISo. TIMA also offered 6 trainee positions to last year students of ENISo in 2013 and 2014; two of them are currently pursuing as PhD students. Discussions are on-going to prepare long-term agreements about student exchanges and potentially double-diploma with INP.

TEAM 2 : Design of integrated devices, circuits and systems International cooperation agreements

§ University of São Paulo, Polytechnic School, Microelectronics Laboratory (LME), Brazil (2011-2014) Title: Développement et miniaturisation de filtres, antennes et lignes de propagation intelligentes Programme:CAPES-COFECUB,Leaders: I. Pereyra (USP), Ph. Ferrari (IMEP), L. Rufer (TIMA) TIMA Annual Report 2014 - International activities 109

§ City University Hong Kong, Dept. of El. Eng. (2013-2014) Title: Limits to thermal actuation in high frequency micromechanical resonators for sensing and timing applications (NATRES). Programme: Procore-PHC (Partenariats H. Curien), Leaders: Joshua En-yuan Lee (CityU), L. Rufer (TIMA) § The Hong Kong University of Science & Technology (2010-2014) Title: High Frequency MEMS Sensor for Aeroacoustics Measurements Programme: Joint Doctorate Supervision Program Leaders: Prof. Man Wong (HKUST), L. Rufer (TIMA)

Organisation of International Conferences, Workshops, Forums in 2014

In the following table, TIMA researchers were General or Program chair or co-chairs for the listed events.

ACRONYM TITLE LOCATION ROLE NAME ETS IEEE European Test Symposium Paderborn, Program Co-Chair H. Stratigopoulos Germany IDT IEEE International Design and Test Algiers, Algeria Program co- S. Mir Symposium chair IMS3TW IEEE International Mixed-Signals, Porto Alegre, Steering S. Mir Sensors and Systems Test Workshop Brazil Committee member Program co- H. Stratigopoulos chair IOLTS IEEE International On-Line Testing Costa Brava, General Chair M. Nicolaidis Symposium Spain ITC IEEE International Test Conference Seattle, WA, Steering M. Nicolaidis USA Committee member LATW Latin American Test Workshop PRIME International Conference on Grenoble, General Chair G. Sicard Ph. D. Research in France TPC Committee G. Sicard Microelectronics and Electronics

TVHSAC IEEE Workshop on Test and Validation of High-Speed Analog Circuits VLSI-SoC IFIP/IEEE International Conference on Playa del Steering S. Mir Very Large Scale Integration Carmen, Mexico Committee Chair VTS IEEE VLSI Test Symposium Napa, Ca, USA Vice Program L. Anghel Chair Steering M. Nicolaidis Committee member

Participation to Committees for International Conferences and Symposia in 2014

ACRONYM TITLE LOCATION ROLE NAME AE Applied Electronics Pilsen Program A. Bonvilain République Committee Tchèque Reviewer ASYNC IEEE Symposium on Asynchronous Potsdam, PC Member L. Fesquet Circuits and Systems Germany

110 TIMA Annual Report 2014 - International activities DATE Design Automation and Test in Europe Dresden, Topic Chair L. Anghel Germany Friday Workshop Chair TPC Committee P. Maistri PC Member L. Pierre Program M. Nicolaidis Committee member DDECS IEEE Symposium on Design and Warsaw, Poland PC member L. Anghel Diagnostics of Electronic Circuits and PC member D. Borrione Systems TPC member R. Leveugle DFTS IEEE Symposium on Defect and Fault Amsterdam, TPC member R. Leveugle Tolerance in VLSI and Nanotechnology Netherlands Systems DTIP Design, Test, Integration Cannes TPC Member L. Rufer & Packaging of MEMS/MOEMS DTIS International Conference on Design & Santorini, TPC member H. Stratigopoulos Technology of Integrated Systems in Greece Nanoscale Era ETS IEEE European Test Symposium Paderborn, D Special Session L. Anghel Chair R. Leveugle Track Chair in TPC S. Mir TPC member FDL Forum on specification & Design Munich, PC member D. Borrione Languages Germany PC member L. Pierre FMCAD Formal Methods in Computer Aided Lausanne, PC member K. Morin-Allory Design Switzerland GLSVLSI Great Lakes Symposium on VLSI Houston, Texas, TPC member USA iCBEB International Conference on Biomedical Beijing Reviewer Agnès Bonvilain Engineering and Biotechnology Chine ICCAD IEEE International Conference on San Jose, TPC member Computer-Aided Design California, USA IOLTS IEEE International On-Line Testing Platja d’Aro, PC L. Anghel Symposium Spain TPC member R. Leveugle TPC Member H. Stratigopoulos ISQED International Symposium on Quality Santa Clara, TPC Member L. Rufer Electronic Design USA ITC IEEE International Test Conference Washington, PC Member L. Anghel USA TPC Member S. Mir Memocode 12th ACM/IEEE International Lausanne, PC member D. Borrione Conference on Methods and Models Switzerland for Correct System Design Sensors IEEE Sensors Valencia, Spain TPC Member L. Rufer VLSI-SoC IFIP/IEEE International Conference on Playa del TPC Member, L. Rufer Very Large Scale Integration Carmen, Mexico Track chair "New devices, MEMS and microsystems Co-track chair L. Pierre TPC Member H. Stratigopoulos VTS IEEE VLSI Test Symposium Napa, TPC member H. Stratigopoulos California, USA

TIMA Annual Report 2014 - International activities 111

Participation to Committees for Regional Conferences, International Workshops and Research Schools in 2014

ACRONYM TITLE LOCATION ROLE NAME FDTC Fault Diagnosis and Tolerance in Busan, Korea TPC Committee P. Maistri Cryptography

Participation to Societies and Working Groups in 2014

Co-Chair of IEEE European Computer Society Test Technology Technical Council (L. Anghel) Chair of IFIP 10.5 Working Group (D. Borrione) Member of IFIP 10.5 Working Group (S. Mir) Member of the IEEE P1687 Working Group (M. Portolan) Member of the IEEE System JTAG initiative (M. Portolan) Global Coordinator for the TTTC's E. J. McCluskey Doctoral Thesis Award (M. Portolan) TTTC Award Co-Chair (M. Portolan) IEEE Solid-State Circuits Chapter Chair (L. Fesquet) Chair of the IEEE Computer Society Test Technology Technical Council (M. Nicolaidis)

Awards and distinctions in 2014

§ Best Paper Award at DATE'2014 Project: Authors: Sofiane Lagraa (TIMA and LIG), Alexandre Termier (LIG), Frédéric Pétrot (TIMA) Title: Scalability Bottlenecks Discovery in MPSoC Platforms Using Data Mining on Simulation Traces at EDAA/IEEE/ACM 17th Design Automation and Test in Europe (DATE'2014) Conference, Dresden, Germany, March 24-28, 2014 § Best Paper Award at EFTF’2014 Authors: Haoshen Zhu (CityU), Cheng Tu (CityU), Libor Rufer (TIMA), Joshua E.-Y. Lee (CityU) Title: Active Electronic Cancellation of Nonlinearity in a High-Q Longitudinal-Mode Silicon Resonator by Current Biasing, 28th European Frequency and Time Forum, EFTF, Neuchâtel, Switzerland, June 23-26, 2014

112 TIMA Annual Report 2014 - International activities

Educational tasks

Dealing with problems risen by advanced technologies and proposing advanced design and test methodologies, TIMA members are, as a matter of fact, very concerned in growing public awareness of these topics. Continuing education is the principal form of advanced knowledge dissemination achieved by the Laboratory, and many teaching sessions have been given to industry (engineers) and academy (teachers and post-graduate students) people. These activities are classified in the sequel into three categories : courses and tutorials, seminars, direction of Ph.D. students employed by French industrial companies (CIFRE program).

Open Seminars at TIMA

In addition to internal seminars, the Laboratory regularly publicises talks given by our visiting researchers. Grenoble academic and industrial researchers had the opportunity to listen to the following speakers :

Speaker Institution Date Theme Multi-level framework for exploration of 26/02/14 Dr Luciano OST UM2 / LIRMM, France distributed and dynamic management for emerging many-core embedded systems TIMA Laboratory - MNS 18/06/14 Thermodynamic Feedback and Haoshen ZHU group visitor Nonlinearity Cancellation Effects in Longitudinal-mode Silicon MEMS Resonators : Modeling and Experimental Verification Mobile Computing System Sensor Network on Chip: A HW-SW 04/07/14 Prof. Jiang Xu Lab Collaborated Method for Resilient Electronic and Computer MPSoC Engineering Hong Kong University of Science and Technology Faculté des Sciences de Contre-mesures contre les attaques 15/10/14 Hassen MESTIRI Monastir, Tunisie par fautes pour AES et SHA-2

Faculté des Sciences de Injection de fautes sur descriptions en 16/10/14 Hassen MESTIRI Monastir, Tunisie SystemC pour l'évaluation de contre- mesures contre les attaques par fautes Software attacks against Java Cards, 17/12/14 Jean-Louis LANET Université de Limoges seven years of continuous security (équipe Smart Secure improvements Device) et INRIA Rennes (High Security Labs)

TIMA – Annual Report 2014 - Educational tasks 113

Seminars and invited talks given by TIMA members

Concerning participation to external seminars, the following table lists the courses and seminars given by members of the Laboratory on their specific research work, following the invitation of various institutions :

Institution Location Date Speaker Title or content Seminar GDR Paris 01/12/2014 L. Pierre Dynamic Verification of SystemC TLM SoC-SiP Virtual Platforms HKUST (Hong Hong Kong 27/11/2014 L. Rufer Piezoelectric Transduction Modeling Kong University and Applications in MEMS of Science and Technology) CEITEC Brno, Czech Republic 16/10/2014 L. Rufer MEMS Devices for (not exclusively) (Central Biomedical Applications European Institute of Technology) Aerospace La Paz (Bolivie) 24/07/2014 R. Velazco Error-rate prediction for programmable Bolivien circuits: methodology, tools and studied Conference cases (ABC 2014) Seminar of the Grenoble 01/06/2014 L. Pierre Verification of Correctness and Safety CONVECS Requirements for SoC Models team (INRIA) 5th International Nashville 23/05/2014 L. Fesquet Mitigating the data-deluge by an Conference on adequate sampling for low-power Computational systems Harmonic Analysis Universidad Madrid, Espagne 23/05/2014 R. Velazco Injection de fautes pour l’analyse de la Complutense de sensibilité face aux erreurs transitoires, Madrid (UCM) soft errors, provoquées par les radiations dans des circuits intégrés Forum Toulouse 01/02/2014 L. Pierre Outils de démonstration automatique et Méthodes preuve de circuits électroniques Formelles (Aerospace Valley - Minalogic) Telecom Grenoble 06/01/2014 D. Borrione "Spécifications et Vérification Formelle" Bretagne Telecom Grenoble 08/01/2014 L. Fesquet Thinking and Designing Differently: Bretagne The Asynchronous Alternative

114 TIMA Annual Report 2014 - Educational tasks

Publications

PEER-REVIEWED JOURNAL ARTICLES (ACL)

THEME 1 : Architectures for robust and complex integrated systems

1 Dimopoulos M., Gang Yi, Anghel L., Benabdenbi M., Zergainoh N.-E., Nicolaidis M. Fault-Tolerant Adaptive Routing under an Unconstrained Set of Node and Link Failures for Many-Core Systems-on-Chip Microprocessors and Microsystems, Volume: 38, pp. 620–635, 2014 2 Zhang Z.*, Refauvelet D.**, Greiner A.**, Benabdenbi M., Pecheux F.** On-the-Field Test and Configuration Infrastructure for 2-D-Mesh NoCs in Shared-Memory Many-Core Architectures IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume: 22, pp. 1364 - 1376 , 2014 *INRIA Rocquencourt, **Laboratoire d'Informatique de Paris 6

THEME 2 : Design of integrated devices, circuits and systems

3 Chefi A., Soudani A.*, Sicard G. Hardware compression scheme based on low complexity arithmetic encoding for low power image transmission over WSNs AEU - International Journal of Electronics and Communications, Volume: 68, March, pp. 193-200, 2014 *Laboratory of Electronics and Micro-Electronics 4 Durand S.*, Zakaria H., Fesquet L., Marchand N.* A Robust and Energy-Efficient DVFS Control Algorithm for GALS-ANoC MPSoC in Advanced Technology under Process Variability Constraints Advances in Computer Science : an International Journal, Volume: 3, pp. 97-105, 2014 *GIPSA-lab, Grenoble, France 5 Dutertre J.M.*, Possamai Bastos R., Potin O.*, Flottes M.-L.**, Rouzeyre B.**, Di Natale G.**, Sarafianos A.*** Improving the ability of Bulk Built-In Current Sensors to detect SEEs by using triple-well CMOS Microelectronics Reliability, Volume: 54, pp. 2289–2294, 2014 *Ecole Nationale Supérieure des Mines de Saint-Etienne , **LIRMM, Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, ***STMicroelectronics 6 Qaisar S.-M., Fesquet L., Renaudin M.* Adaptive rate filtering a computationally efficient signal processing approach Signal Processing, Volume: 94, pp. 620-630 , 2014 *TIEMPO SAS 7 Zhou Z.*, Rufer L., Wong M.* Damped Aero-Acoustic Microphone with Improved High-Frequency Characteristics Journal of Microelectromechanical Systems, Volume: 23, pp. 1094 - 1100 , 2014 *Hong Kong University of Science and Technology

THEME 3 : Design and verification of System-on-Chip architectures

8 Mancini S., Larabi Z.*, Mathieu Y.*, Toczek T.**, Pierrefeu L.** Exploration of 3D grid caching strategies for ray-shooting Journal of Real Time Image Processing, Volume: 7, pp. 3-19, 2014 *Institut TELECOM, TELECOM Paris-Tech, Paris, France, **GIPSA-lab, Grenoble, France 9 Simeu-Abazi Z.*, Di Mascolo M.*, Gascard E. Queuing Network-based methodology for designing and assessing performance of centralized maintenance workshops Journal of Manufacturing Technology Management, Volume: 25, pp. , 2014 *G-SCOP Laboratory (CNRS – Grenoble INP – UJF), Grenoble, France

TIMA Annual Report 2014 - Publications 115

THEME 4 : Reliable Mixed-signal / RF circuits and systems

Fast Monte Carlo-Based Estimation of Analog Parametric Test Metrics IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 33, pp. 1977 - 1990 , 2014 *Mentor Graphics Corporation

ARTICLES IN PEER-REVIEWED CONFERENCE PROCEEDINGS (ACT)

THEME 1 : Architectures for robust and complex integrated systems

11 Alberto D., Maistri P., Leveugle R. Electromagnetic attacks on embedded devices: a model of probe-circuit power coupling 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS'14), pp.23-28 , 2014 12 Alexandrescu D.*, Alexandrescu D., Evans A.*, Evans A., Costenaro E.*, Costenaro E. Minimization of SER-Induced Costs through Linear Programming The 10th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE'14), pp., 2014 *iROc Technologies, Word Trade Center, P.O. Box 1510 38025 Grenoble France 13 Anghel L., Savulimedu Veeravalli V.*, Alexandrescu D.**, Alexandrescu D., Steininger A.*, Schneider-Hornstein K.*, Costenaro E.**, Costenaro E. Single Event Effects in Muller C-Elements and Asynchronous Circuits Over a Wide Energy Spectrum The 10th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE'14), pp., 2014 *TU, Vienna University of Technology, **iROc Technologies, Word Trade Center, P.O. Box 1510 38025 Grenoble France 14 Bergaoui S., Vanhauwaert P., Leveugle R. IDSM: an improved disjoint signature monitoring scheme for processor behavioral checking 15th Latin-American Test Workshop (LATW'14), pp.1-6, 2014 15 Bollo M., Maistri P. Composite Fields against Side Channel Analysis for the Advanced Encryption Standard 21st IEEE International Conference on Electronics Circuits and Systems (ICECS'14), pp.542-545, 2014 16 Chibani K., Ben Jrad M., Portolan M., Leveugle R. Fast accurate evaluation of register lifetime and criticality in a pipelined microprocessor 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'14), pp.260-265, 2014 17 Chibani K., Bergaoui S., Portolan M., Leveugle R. Criticality evaluation of embedded software running on a pipelined microprocessor and impact of compilation options IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp.778-781, 2014 18 Chibani K., Portolan M., Leveugle R. Fast register criticality evaluation in a SPARC microprocessor 10th Conference on Ph.D Research in Microelectronics and Electronics (PRIME'14), pp.1-4, 2014 19 Dimopoulos M., Gang Yi, Benabdenbi M., Anghel L. Efficient Fault-Tolerant Adaptive Routing under an unconstrained Set of Node and Link Failures for Many Cores System On Chip Workshop on Dependable Multicore and Transactional Memory Systems (DMTM'14), (joint to HIPEAC event), pp.1-2, 2014 20 Ebrahimi M.*, Evans A., Tahoori M.*, Seyyedi R.*, Costenaro E.**, Alexandrescu D.** Comprehensive Analysis of Alpha and Neutron Particle-induced Soft Errors in an Embedded Processor at Nanoscales Design, Automation & Test in Europe Conference (DATE'14), pp.1-6, 2014 *Karlsruhe Institute of Technology, Institut für Techknik der Informationsverarbeitung, Germany, **iROc Technologies, Word Trade Center, P.O. Box 1510 38025 Grenoble France 21 Evans A., Ferlet-Cavrois V.*, Alexandrescu D.*, Nicolaidis M. New Techniques for SET Sensitivity and Propagation Measurement in Flash-Based FPGAs Nuclear and Space Radiation Effects Conference (NSREC'14), pp., 2014 *iROc Technologies, Word Trade Center, P.O. Box 1510 38025 Grenoble France

116 TIMA Annual Report 2014 - Publications 22 Ganapathy S.*, Canal R.*, Alexandrescu D.**, Costenaro E., Gonzales A.*, Rubio A.* INFORMER: An Integrated Framework for Early-Stage Memory Robustness Analysis Design, Automation & Test in EurpeConference & Exhibition (DATE'14), pp.1-4, 2014 *Department of Electronic Engineering, Universitat Politecnica de Catalunya, 08034 Barcelona, Spain, **iROc Technologies, Word Trade Center, P.O. Box 1510 38025 Grenoble France 23 Lauzeral O.*, Costenaro E.*, Costenaro E., Gaillard R.**, Cawley J.**, Alexandrescu D.*, Alexandrescu D., Evans A.*, Evans A. Supply Chain Management for Reliability: Identifying SER-critical components in a large system-Bill Of Material IEEE International Reliability Innovations Conference (IRIC'14), pp., 2014 *iROc Technologies, Word Trade Center, P.O. Box 1510 38025 Grenoble France, **INFODUC 24 Leveugle R., Maistri P., Vanhauwaert P., Lu F.*, Di Natale G.*, Flottes M.-L.*, Rouzeyre B.*, Papadimitriou A.**, Hély D.**, Beroulle V.**, Hubert G.***, De Castro S.****, Dutertre J.M.****, Sarafianos A.*****, Boher N.*****, Lisart M.*****, Damiens J.*****, Candelier P.*****, Tavernier C.***** Laser-induced fault effects in security-dedicated circuit 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'14), pp.201-206, 2014 *LIRMM, Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, **LCIS, Laboratoire de Conception et d'Intégration des Systèmes, ***ONERA/DESP, ****Ecole Nationale Supérieure des Mines de Saint-Etienne , *****STMicroelectronics 25 Maistri P., Leveugle R., Bossuet L.*, Aubert A.*, Fischer V.*, Robisson B.**, Moro N.**, Maurine P.***, Dutertre J.M.****, Lisart M.**** Electromagnetic analysis and fault injection onto secure circuits 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'14), pp.195-200, 2014 *LHC, Laboratoire Hubert Curien , **CEA, Grenoble, France, ***LIRMM, Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, ****Ecole Nationale Supérieure des Mines de Saint- Etienne 26 Mansour W., Ramos P., Ayoubi R.*, Velazco R. SEU fault-injection at system level: method, tools and preliminary results Latin American Test Workshop (LATW), Fortaleza, Brazil, pp., 2014 *Balamand University 27 Nicolaidis M. Emergence of Euclidian Geometry in a Computational Universe 50th AISB Convention, pp.1-8, 2014 28 Nicolaidis M. Double-sampling Achitectures IEEE International Reliability Physics Symposium (IRPS'14), pp.3D.1.1 - 3D.1.7 , 2014 29 Papadimitriou A.*, Hély D.*, Beroulle V.*, Maistri P., Leveugle R. A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks Design, Automation and Test in Europe Conference (DATE), Dresden, Germany, pp., 2014 *LCIS, Laboratoire de Conception et d'Intégration des Systèmes 30 Papavramidou P., Hély D.*, Beroulle V.*, Maistri P., Leveugle R. FPGA emulation of laser attacks against secure deep submicron integrated circuits Second Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'14), pp., 2014 *LCIS, Laboratoire de Conception et d'Intégration des Systèmes 31 Pontié S. Architecture d’un crypto processeur ECC sécurisé contre les attaques physiques Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'14), pp.4, 2014 32 Pontié S., Maistri P. Randomized Windows for a Secure Crypto-Processor on Elliptic Curves 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2014), pp., 2014 33 Pontié S., Maistri P. Design of a secure architecture for scalar multiplication on elliptic curves 10th Conference on Ph.D Research in Microelectronics and Electronics (PRIME'14), pp., 2014

TIMA Annual Report 2014 - Publications 117

34 Pontié S., Maistri P., Leveugle R. An Elliptic Curve Crypto-Processor Secured by Randomized Windows Digital System Design (DSD), 2014 17th Euromicro Conference on, pp.535 - 542, 2014 35 Saliva M.*, Cacho F.*, Huard V.*, Angot D.*, Durand M.*, Federspiel X.*, Parra M.*, Bravaix A. *, Anghel L., Blanc-Benon P.** New Insight about Oxide Breakdown Occurrence at Circuit Level IEEE International Reliability Physics Symposium (IRPS'14), pp., 2014 *STMicroelectronics, **Laboratoire de Mecanique des Fluides et d'Acoustique, Lyon, France 36 Souari A.*, Thibeault Cl.*, Blaquière Y.**, Velazco R. Towards a realistic SEU effects emulation on SRAM Based FPGAs IEEE Nuclear and Space Radiation Effects Conference (NSREC '14), pp., 2014 *ETS, Ecole de Technologie Supérieure, Département de génie électrique, **UQAM, Université du Québec à Montréal 37 Velazco R., Clemente J.A.*, Hubert G.**, Mansour W., Palomar C., Franco F.*, Baylac M.**, Rey S.***, Rossetto O.***, Villa F.*** Evidences of the robustness of a COTS soft-error free SRAM to neutron radiation IEEE Nuclear and Space Radiation Effects Conference (NSREC'14), pp., 2014 *Universidad Complutense de Madrid, Spain, **ONERA/DESP, ***Laboratoire de Physique Subatomique et de Cosmolo- gie 38 Villa F.*, Baylac M.*, Rey S.*, Rossetto O.*, Mansour W., Ramos P., Velazco R., Hubert G.** Accelerator-Based Neutron Irradiation of Integrated Circuits at GENEPI-2 (France) REDW (Radiation Effects Data Workshop) of IEEE NSREC (Nuclear and Space Radiation Effects Conference), pp.1-5, 2014 *Laboratoire de Physique Subatomique et de Cosmolo- gie, **ONERA/DESP

THEME 2 : Design of integrated devices, circuits and systems

39 Al Khatib Ch., Aupetit C.*, Chagoya A.*, Chevalier C.*, Sicard G., Fesquet L. Distributed Asynchronous Controllers for Clock Management in Low Power Systems 21st IEEE International Conference on Electronics Circuits and Systems (ICECS'14), pp.379-382, 2014 *CIME, INPG, Grenoble 40 Bernard F., Chappaz C.*, Basrour S. Génération d'’un interposeur pour surface tactile vibrante pour rendu haptique Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'14) , pp.3, 2014 *STMicroelectronics 41 Bonnaud O.*, Fesquet L. Trends in Nanoelectronic Education: From FDSOI and FinFET Technologies to Circuit Design Specifications The 10th European Workshop on Microelectronics Education (EWME 2014), pp.106 - 111 , 2014 *Institut d'Electronique et de Télécommunications de Rennes, Université de Rennes 1 – Institut National des Sciences Appliquées (INSA Rennes) – SUPELEC, France 42 Bonnaud O.*, Fesquet L. A Prospective on Education of New Generations of devices in the FDSOI and FinFET Technologies: from the technological process to the Circuit Design Specifications 29th Symposium on Microeletronics Technology and Devices (SBMicro'14), pp.1-4, 2014 *Institut d'Electronique et de Télécommunications de Rennes, Université de Rennes 1 – Institut National des Sciences Appliquées (INSA Rennes) – SUPELEC, France 43 Bonnaud O.*, Nouet P.**, Fesquet L., Tayeb M.-B*** FINMINA: a French national project to promote Innovation in Higher Education in Microelectronics and Nanotechnologies International Conference on Information Technology Based Higher Education and Training (ITHET'14), pp.1-8, 2014 *Institut d'Electronique et de Télécommunications de Rennes, Université de Rennes 1 – Institut National des Sciences Appliquées (INSA Rennes) – SUPELEC, France, **LIRMM, Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, ***CCMO, University of Rennes 1 44 Bonnaud O.*, Salaün A-C**, Bsiesy Ah.**, Fesquet L. Improvement of doctoral studies in Electrical and Information Engineering through the High level courses in Europe 25th EAEEIE Annual Conference, pp., 2014

118 TIMA Annual Report 2014 - Publications *Institut d'Electronique et de Télécommunications de Rennes, Université de Rennes 1 – Institut National des Sciences Appliquées (INSA Rennes) – SUPELEC, France, **CIME, INPG, Grenoble 45 Bonvilain A., Gangneron M. First experimentations of microsensors microfabricated on a long and thin medical needle Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP 14), Cannes, France, pp., 2014 46 Casset F.*, Danel J.*, Renaux Ph.*, Chappaz C.**, Le Rhun G.*, Dieppedale C.*, Gorisse M.***, Basrour S., Fanget S.*, Ancey P.**, Devos A.***, Defay E.* Characterization and post simulation of thin-film PZT actuated plates for haptic applications 15th international conference on Thermal, mechanical and multi-physics simulation and experiments in microelectronics and microsystems (eurosime'14), Ghent, Belgium , pp.1–4, 2014 *CEA-LETI, Laboratoire d'Electronique de Technologie de l'Information, **STMicroelectronics, ***Institut d'électronique, de microélectronique et de nanotechnologie, U. Lille 47 Chefi A., Sicard G. SPIHT-based image compression scheme for energy conservation over Wireless Vision Sensor Networks 21st IEEE International Conference on Electronics Circuits and Systems (ICECS'14), pp.678-681, 2014 48 Darwish A., Fesquet L., Sicard G. 1-level Crossing Sampling Scheme for Low Data Rate Image Sensors 12th IEEE International New Circuits and Systems Conference (NEWCAS'14), pp.289-292, 2014 49 Darwish A., Sicard G., Fesquet L. Low data rate architecture for smart image sensor Image Sensors and Imaging Systems, San Francisco, California, USA, pp.9022-5, 2014 50 Dutertre J.M.*, Possamai Bastos R., Potin O.*, Flottes M.-L.**, Rouzeyre B.**, Di Natale G.** Design of Bulk Built-In Current Sensors to Detect Single Event Effects and Laser-Induced Fault Injection Attempts Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'14), pp., 2014 *Ecole Nationale Supérieure des Mines de Saint-Etienne , **LIRMM, Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier 51 Faix M.*, Mazer E.*, Fesquet L. An asynchronous CMOS probabilistic computer Idea 20th International Symposium on Asynchronous Circuits and Systems (ASYNC), Fresh Idea Session, Postdam, Germany, pp., 2014 52 Fesquet L., Cherkaoui A., Elissati O. Self-timed rings as low-phase noise programmable oscillators 12th IEEE International New Circuits and Systems Conference (NEWCAS'14), pp.409 - 412 , 2014 53 Fesquet L., Morin-Allory K., Robin R.* Contrôle autonome d'un nano-drone par caméra externe 13ème journées pédagogiques du CNFM (JPCNFM), pp., 2014 *CIME, INPG, Grenoble 54 Naimi A., Bonvilain A. Expérimentations de microjauges de déformation réalisées par microfabrication sur des aiguilles médicales Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'14) , pp.4, 2014 55 Possamai Bastos R., Dutertre J.M.*, Torres F.S.** Comparison of Bulk Built-In Current Sensors in terms of Transient-Fault Detection Sensitivity European Workshop on CMOS Variability (VARI'14), pp.1-6, 2014 *Ecole Nationale Supérieure des Mines de Saint-Etienne , **Fed. Univ. of Minas Gerais, Dept. of Electron. Eng., Belo Honzonte, Brazil 56 Roa G., Le Pelleter T., Bonvilain A., Chagoya A.*, Fesquet L. Designing ultra-low power systems with non-uniform sampling and event-driven logic 27th Symposium on Integrated Circuits and Systems Design (SBCCI'14), pp.1-6, 2014 *CIME, INPG, Grenoble 57 Sicard G., Abbas H., Chefi A., Amhaz H. Simple intra-pixel interaction for smart CMOS image sensors 14th International Workshop on the Cellular Nanoscale Networks and their Applications (CNNA'14), pp.1-2, 2014

TIMA Annual Report 2014 - Publications 119

58 Tu C.*, Zhu H.*, Rufer L., Lee J.* Low Impedance Very-High-Frequency (VHF) Band Thermal Piezoresistive Silicon Bulk Acoustic Resonator The 7th Asia-Pacific Conference on Transducers and Micro/Nano Technologies (APCOT'14), pp.2, 2014 *Department of Electronic Engineering, City University of Hong Kong, Kowloon, Hong Kong

THEME 3 : Design and verification of System-on-Chip architectures

59 Bel Hadj Amor Z., Pierre L., Borrione D. A Tool for the Automatic TLM-to-RTL Conversion of Embedded Systems Requirements for a Seamless Verification Flow International Conference on Very Large Scale Integration (VLSI-SoC'14), pp.1-6, 2014 60 Bel Hadj Amor Z., Pierre L., Borrione D. System-on-Chip Verification: TLM-to-RTL Assertions Transformation 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME'14), Grenoble, France, pp.1-4, 2014 61 Bourge A., Ghiti A., Muller O., Rousseau F. Méthode de sélection de checkpoint matériel avec outil de synthèse de haut niveau Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'14), pp.4, 2014 62 Chabot M., Pierre L. A Customizable Monitoring Infrastructure for Hardware/Software Embedded Systems Proc. 26th IFIP International Conference on Testing Software and Systems (ICTSS'2014), pp.173-179, 2014 63 Fesquet L., Morin-Allory K., Robin R.* Contrôle autonome d'un nano-drone par caméra externe 13ème journées pédagogiques du CNFM (JPCNFM), pp., 2014 *CIME, INPG, Grenoble 64 Gascard E., Simeu-Abazi Z.*, Suiphon B.* A Polynomial-Time Algorithm for Diagnosability Verification of Discrete Event Systems 2nd World Conference on Complex Systems (WCCS'14), pp., 2014 *G-SCOP Laboratory (CNRS – Grenoble INP – UJF), Grenoble, France 65 Lagraa S.*, Termier A.*, Pétrot F. Scalability bottlenecks discovery in MPSoC platforms using data mining on simulation traces Best Paper Award in Design Automation and Test in Europe (DATE'14), Dresden, Germany, pp.1-6, 2014 *LIG (CNRS-INPG-UJF), Grenoble, France 66 Mancini S. Adaptation dynamique en boucle fermée d'un pré-chargement stochastique dans les tableaux Conférence en Parallélisme, Architecture et Système (COMPAS'14), pp., 2014 67 Saadé J., Goulahsen A.*, Picco A.*, Huloux J.*, Pétrot F. A Scalable Low Overhead Line Coding For Asynchronous High Speed Serial Transmission 18th IEEE Workshop on Signal and Power Integrity (SPI'14), Ghent, Belgium, pp.1-4, 2014 *STMicroelectronics 68 Sarrazin G.*, Sarrazin G., Pétrot F., Fournel N., Gerin P.* Simulation native de systèmes many-cœurs pouvant avoir des caractéristiques architecturales non génériques Conférence d’informatique en Parallélisme (COMPAS'14), Architecture et Système, pp., 2014 *Kalray, Montbonnot-Saint-Martin 38330, France 69 Suiphon B.*, Simeu-Abazi Z.*, Gascard E. Premiers pas vers le diagnostic de défaillances par exploitation d'un modèle 19e Congrès de Maîtrise des Risques et Sûreté de Fonctionnement (LambdaMu 19), pp., 2014 *G-SCOP Laboratory (CNRS – Grenoble INP – UJF), Grenoble, France 70 Vincent L., Mancini S. Closed-loop Adaptive and Stochastic Prefetch Mechanism for Data Array Conference on Design and Architectures for Signal and Image Processing (DASIP'14), pp., 2014

120 TIMA Annual Report 2014 - Publications THEME 4 : Reliable Mixed-signal / RF circuits and systems

71 Alhakim R., Simeu E. Efficient tracking design in UWB communication systems IEEE International Conference on Ultra-Wideband (ICUWB'14), pp.211-216, 2014 72 Andraud M., Deluthault A.*, Dieng M.*, Azais F.*, Bernard S.*, Cauvet P.**, Comte M.*, Kervaon T.***, Kerzerho V.*, Mir S., Pugliesi-Conti P.***, Renovell M.*, Soulier F.*, Simeu E., Stratigopoulos H. Solutions for the self-adaptation of communicating systems in operation IEEE International On-line Test Symposium (IOLTS'14), pp.234-239, 2014 *LIRMM, Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, **--, ***NXP Semiconductors, Caen, France 73 Andraud M., Stratigopoulos H., Simeu E. One-shot calibration of RF circuits based on non-intrusive sensors Design Automation Conference, San Francisco, CA, USA, pp.1-6, 2014 74 Barragan M., Leger G.* Feature selection for Alternate Test using wrappers: application to an RF LNA case study 1st Workshop on Statistical Test Methods (STEM'14), Paderborn, Germany, pp.6, 2014 *IMSE, Instituto de Microelectronica de Sevilla 75 Dimakos A., Stratigopoulos H., Siligaris A.*, Mir S., De Foucauld E.* Non-intrusive built-in test for 65nm RF LNA IEEE International Mixed-signals, Sensors and Systems Test Workshop (IMS3TW'14), pp.1-6, 2014 *CEA-LETI, Laboratoire d'Electronique de Technologie de l'Information 76 Dubois M., Stratigopoulos H., Mir S., Barragan M. Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs IFIP/IEEE 22nd International Conference on Very Large Scale Integration (VLSI-SoC'14), pp.1-6, 2014 77 Ekobo Akoa B., Simeu E., Lebowsky F.* Using statistical analysis and artificial intelligence tools for automatic assessment of video sequences Color Imaging XIX: Displaying, Processing, Hardcopy, and Applications, pp.1-11, 2014 *STMicroelectronics 78 Renaud G., Barragan M., Mir S. On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test 23rd IEEE Asian Test Symposium (ATS'14), pp.212-217, 2014 79 Serhan A.*, Abdallah L., Stratigopoulos H., Mir S. Low-cost EVM built-in test of RF transceivers 9th IEEE International Design and Test Symposium (IDT'14), pp.51-54, 2014 *IMEP, Grenoble, France 80 Stratigopoulos H., Sunter S.* Fast Monte Carlo-Based Estimation of Analog Parametric Test Metrics 1st Workshop on Statistical Test Methods (Fringe event to ETS 2014) , pp., 2014 *Mentor Graphics Corporation 81 Stratigopoulos H., Sunter S.* Efficient Monte Carlo-Based Analog Parametric Fault Modelling IEEE VLSI Test Symposium, Napa, CA, USA, pp.1-6, 2014 *Mentor Graphics Corporation

INVITED CONFERENCE PRESENTATION (INV)

THEME 1 : Architectures for robust and complex integrated systems

82 Bhasin S.*, Maistri P., Regazzoni F.** Malicious Wave: a Survey on Actively Tampering Using Electromagnetic Glitch International Symposium on Electromagnetic Compatibility (EMC 2014), Raleigh Convention Center Raleigh, NC, USA, pp., 2014 *Institut TELECOM, TELECOM Paris-Tech, Paris, France, **ALaRI - USI, Lugano, Switzerland 83 Schlichtmann U.*, Kleeberger Veit B.*, Abraham J.**, Evans A., Gimmler-Dumont Ch.*, Glaβ M.***, Herkersdorf A.*, Nassif, Sani R. ****, Wehn N.* Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test Design, Automation & Test in Europe Conference & Exhibition (DATE'14), pp.1-8, 2014

TIMA Annual Report 2014 - Publications 121

*Technische hoschschule Universität Darmstadt, **GMD - Forschungszentrum Informationstechnik GmbH, ***FAU - Friedrich-Alexander-Universität Erlangen-Nürnberg, ****IBM, Wireless Test Development Group, VT, USA 84 Vanhauwaert P., Maistri P., Leveugle R., Papadimitriou A.*, Hély D.*, Beroulle V.* On error models for RTL security evaluations 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS'14), pp.115-120, 2014 *LCIS, Laboratoire de Conception et d'Intégration des Systèmes

THEME 2 : Design of integrated devices, circuits and systems

85 Fesquet L., Le Pelleter T., Darwish A., Beyrouthy T., Bidegaray-Fesquet B.* Mitigating the data-deluge by an adequate sampling for low-power systems 5th International Conference on Computational Harmonic Analysis, pp.17, 2014 *Laboratoire Jean Kuntzmann (CNRS, UJF, Grenoble INP), France

THEME 3 : Design and verification of System-on-Chip architectures 86 Pétrot F. Some Design Issues for 3D NoCs : From Circuits to Systems Keynote in 8th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'14), pp., 2014 87 Pétrot F. Advanced Virtual Prototyping of Multiprocessor SoCs IEEE Symposium on Low-Power and High-Speed Chips (Cool Chips'14), pp., 2014

THEME 4 : Reliable Mixed-signal / RF circuits and systems

88 Altet J.*, Aldrete-Vidrio E.*, Reverter F.*, Gomez D.*, Gonzalez J.L.**, Onabajo M.***, Silva- Martinez J.*, Martineau B.****, Perpinà X.*****, Abdallah L., Stratigopoulos H., Aragonès X.*, Jordà X.*, Vellvehi M.******, Dilhaire S.*, Mir S., Mateo D.* Review of temperature sensors as monitors for RF mmW built-in testing and self-calibration schemes 57th IEEE Midwest Symposium on Circuits and Systems (MWSCAS'14), pp.1081-1084, 2014 *Department of Electronic Engineering, Universitat Politecnica de Catalunya, 08034 Barcelona, Spain, **CEA-LETI, Laboratoire d'Electronique de Technologie de l'Information, ***Dept. of Electronic Engineering, Univ. of Roma, Italy, ****STMicroelectronics, *****BNR, Ottawa, Ontario, Canada, ******Centre Nacional de Microelectronica, Bellatera, Spain 89 Dubois M., Stratigopoulos H., Barragan M., Alhakim R., Mir S. Analog/RF test problem solving with statistically sampled data IEEE VLSI Test Symposium (VTS'14), pp., 2014 90 Mir S. Analog/RF test techniques 14th European Test Symposium, Test Spring School, pp., 2014 91 Mir S. Trends in mixed-signal test cost in current and future ICs Panel moderator at 19th IEEE International Mixed-Signals, Sensors and Systems Test Workshop (IMS3TW'14), pp., 2014 92 Stratigopoulos H. RF Built-In Test with Non-Intrusive Sensors IEEE VLSI Test Symposium (VTS'14), pp., 2014

POSTER PRESENTATION IN CONFERENCE (AFF)

THEME 3 : Design and verification of System-on-Chip architectures

93 Schwambach V.*, Cleyet-Merle S.*, Issard A.*, Mancini S. Optimisation de performance au niveau applicatif: étude de cas de vision embarquée sur STHORM Conférence en Parallélisme, Architecture et Système (COMPAS'14), pp., 2014 *STMicroelectronics

122 TIMA Annual Report 2014 - Publications THESES (TH)

THEME 1 : Architectures for robust and complex integrated systems

94 Costa-Marques G. Study of ..... These de Doctorat, Université de Grenoble, spécialité "Nanoélectronique et Nanotechnologies", October 24th, 2014 95 Evans A. Abstraction techniques for scalable soft error analysis and mitigation These de Doctorat, Université de Grenoble, spécialité "Micro et Nano Electronique", June 19th, 2014 96 Papavramidou P. Memory Repair Architectures for High Defect Densities These de Doctorat, Université de Grenoble, spécialité "Nanoélectronique et Nanotechnologies", November 19th, 2014

THEME 2 : Design of integrated devices, circuits and systems

97 Abbas H. Local adaptive control in a sensor CMOS vision These de Doctorat, Université de Grenoble, spécialité "Nanoélectronique et Nanotechnologies", July 4th, 2014 98 Chefi A. Design of Low Power CMOS Image Sensor for Wireless Sensor Networks These de Doctorat, Université de Grenoble, spécialité "Physique", January 28th, 2014 99 Cherkaoui A. Ring oscillator based true random number generators These de Doctorat, Université Jean Monnet, St.Etienne, France, spécialité "Microélectronique", June 16th, 2014

THEME 3 : Design and verification of System-on-Chip architectures

100 Bel Hadj Amor Z. Validation of complex systems on a chip, from TLM level to RTL These de Doctorat, Université de Grenoble, spécialité "Nanoélectronique et Nanotechnologies", December 17th, 2014 101 Lagraa S. New MPSoC profiling tools based on data mining techniques These de Doctorat, Université de Grenoble, spécialité "informatique", June 13th, 2014 102 Michel L. Contributions to Dynamic Binary Translation: instruction parallelism support and optimized translators generator These de Doctorat, Université de Grenoble, spécialité "Nanoélectronique et Nanotechnologies", December 18th, 2014 103 Prost-Boucle A. Fast hardware accelerator generation using high-level synthesis under resource constraints These de Doctorat, Université de Grenoble, spécialité "Nanoélectronique et Nanotechnologies", January 8th, 2014 104 Xu Yan Lightweight Software Services for Dynamic Partial Reconfiguration of FPGAs These de Doctorat, Université de Grenoble, spécialité "Micro et Nano Electronique", March 13th, 2014

THEME 4 : Reliable Mixed-signal / RF circuits and systems

105 Bousquet L. Enriched high level model generation for heterogeneous and multiphysic systems These de Doctorat, Université de Grenoble, spécialité "Micro et Nano Electronique", January 29th, 2014 106 Ekobo Akoa B. TIMA Annual Report 2014 - Publications 123

Error detection and concealment integrated in a video decoder using technics of statistical analysis These de Doctorat, Université de Grenoble, spécialité "Nanoélectronique et Nanotechnologies", October 31st, 2014

SOFTWARE AND PATENTS

THEME 2 : Design of integrated devices, circuits and systems

107 Alleysson D.*, Sicard G. Capteurs CMOS à Photosites standard Brevet N° FR2014/051307, delivered on Jan 1st, 2014 *Laboratoire de psychologie et neurocognition (LPNC), UPMF, Grenoble, France 108 Colin M., Basrour S. Générateur implantable à poutre piézoélectrique Brevet N° 14/54616, delivered on May 22nd, 2014 109 Trioux E., Ancey P., Monfray S., Skotnicki T.*, Basrour S., Muralt P. Procédé de fabrication de lamelles bistables de courbures différentes Brevet N° 14/51833, delivered on Mar 6th, 2014

THEME 4 : Reliable Mixed-signal / RF circuits and systems

110 Fei R.*, Mir S., Moreau J. Circuit and method for on-chip testing of a pixel array Brevet N° , delivered on Oct 21st, 2014

124 TIMA Annual Report 2014 - Publications

Social life

The Laboratory had the pleasure to congratulate some of its members for births.

Born children of Laboratory's members:

Mariam ALHAKIM 01/04/2014 Nathan EKOBO AKOA 30/05/2014 Gaspart et Lucie CHEVROT 12/01/2014

TIMA – Annual Report 2014 - Social life 125

SEMBA'2014 TIMA participants

Best paper award DATE 2014

126 TIMA – Annual Report 2014 - Social life

TIMA – Annual Report 2014 - Social life 127