TIMA Laboratory ANNUAL REPORT 2014 May 2015 _______________________________________________________________ 46, Avenue Félix Viallet 38031 Grenoble Cedex France Tel. :+33 4 76 57 45 86 Fax :+33 4 76 57 49 81 http://tima.imag.fr Foreword TIMA is a public research laboratory sponsored by Synthesis (SLS), Verification and modeling of Centre National de la Recherche Scientifique (CNRS), Digital Systems (VDS). Grenoble Institute of Technology (Grenoble INP) and Université Joseph Fourier (UJF). TIMA addresses Theme 4: Reliable Mixed-signal / RF circuits and some of the most urgent and ambitious challenges systems (RMS). CAD tools, design-for-test, testing related to the design of tomorrow’s circuits and techniques for mixed-signal, RF, microsystem devices. systems on a chip. The research topics of TIMA cover the specification, design, verification, test, CAD tools The 2014 edition of TIMA annual report presents a and design methods for integrated systems, from brief and synthetic presentation of each research analog and digital components on one end of the theme, followed by a scientific summary of its main spectrum, to multiprocessor Systems-on-Chip projects; each project is well identified with the together with their basic operating system on the other relevant key-words, investigators, cooperation and end. contracts. For detailed scientific information, the reader is referred to the relevant articles. A complete In 2014, TIMA is structured in four research themes, list of publications, classified by category and by topic, according to the domain of expertise and research is also provided at the end of the document. communities of their members. The projects reported in this document are grouped according to these A large part of the research is financed by research themes. grants and contracts. Some are large cooperative projects with industrial and academic partners, at the Theme 1: Architectures for robust and complex national, European or world level; others are bilateral integrated systems (ARIS). Reconfigurable and industrial collaborations, linked to a CIFRE doctoral massively parallel multi-core architectures; fault co-tutorship. Most contracts run for 3 to 4 years. In tolerant and self-adaptive architectures; evaluation of 2014, 34 contracts were in operation, out of which 12 robustness and qualification; secured architectures; new projects were started. Page 101 gives an architectures for nanotechnologies overview of our contractual activity. Theme 2: Design of integrated devices, circuits Among the highlights of the year, two publications and systems. Design, fabrication and characterization were distinguished in an international conference: for integrated micro and nano systems; energy Sofiane Lagraa and Frédéric Pétrot for their paper scavenging and power management for autonomous "Scalability Bottlenecks Discovery in MPSoC devices; Bio-MEMS; asynchronous circuits and Platforms Using Data Mining on Simulation Traces" systems (asynchronous IPs, NoCs, GALS, etc…); non- obtained a Best Paper Award at DATE 2014, and uniform sampling and signal processing (algorithms, Libor Rufer who co-authored the paper " Active architectures, circuits); reconfigurable asynchronous Electronic Cancellation of Nonlinearity in a High-Q logic; safe and secured circuit design; smart CMOS Longitudinal-Mode Silicon Resonator by Current vision sensors. This theme is further decomposed into Biasing" got a Best Paper Award at EFTF2014. And two groups: Concurrent Integrated Systems (CIS), one patent was filed by Mickael Colin and Skandar Micro and Nano Systems (MNS) Basrour: "Générateur implantable à poutre piézoélectrique" Theme 3: Design and verification of System-on- Chip architectures. Architectures, CAD and Members of TIMA were active in the Technical verification techniques for MPSOC’s and integrated Program Committee of 16 conferences and workshop, NoCs; modeling, simulation techniques and with a particular involvement in the organization of reconfigurable prototyping platform for system PRIME as General Chair, and VTS as Co-Program validation; specification and implementation of Chair. The details of these contributions to the hardware-dependent software; assertion-based scientific community is listed starting page 109. verification and synthesis; automatic generation of hardware checkers; verification of logic and temporal Finally, TIMA takes an active part in the new properties at the system level; formal methods for organization of the research in the Grenoble Alpes robustness analysis. This theme is further University, being linked to the two poles decomposed into two groups: System Level "Mathematics, Informatics and Communication" TIMA Annual Report 2014 - Foreword 3 (MSTIC) and "Physics, Engineering and Materials" Starting January 2015, a reorganization of Themes 1 (PEM). TIMA is also a member of the Carnot LSI and 3 will take place, resulting in a total number of 5 Institute and a member of Persyval Lab. research teams for TIMA. Dominique Borrione Further information may be obtained from : D. BORRIONE, TIMA, 46 avenue Félix Viallet, 38031 GRENOBLE Cedex, FRANCE. Tel : +33 4 76 57 45 86, Fax : +33 4 76 57 49 81, E-mail : [email protected], http://tima.imag.fr 4 TIMA Annual Report 2014 - Foreword 4 TIMA Annual Report 2014 - Foreword Table of Contents 07 87 Theme 1 / ARIS Group Academic and research member Architectures for complex and Robust Integrated Systems 93 Staff members 29 Theme 2 / CIS Group Design of Integrated devices, circuits and 95 Systems Ph.D. candidates 41 99 Theme 2 : MNS Group Other members of TIMA Micro and Nano Systems 101 51 Contracts Theme 3 : SLS Group : Design Design and Verification of Systems on a 119 Chip architectures International activities 61 113 Theme 3 : VDS Group : Verification Educational tasks Design and Verification of Systems on a Chip architectures 115 67 Publications Theme 4 : RMS Group Reliable Mixed-signal / RF circuits and 125 Systems Social life TIMA Annual Report 2014 - Table of contents 5 6 TIMA Annual Report 2014 - Table of contents Theme 1 / ARIS Group Architectures for complex and Robust Integrated Systems Themes Robust massively parallel single-chip architectures Power management from the OS down to silicon Fault tolerant and self-adaptative architectures 3D NOC Robust Architectures Design in Reliability face to aging, process variation and soft errors Evaluation of robustness and qualification : radiation testings, fault injection Secured architectures Architectures for Nanotechnologies Expertise Scientific Hardware/software techniques for the design of fault and malicious attacks resistant components and embedded systems Fields of expertise Test, Security, Self-Repair, Fault-tolerance : Methodologies, Tools and Architectures Know-how Multilevel platforms for fault simulation and robustness automatic insertion at several abstraction levels; 3D integration solutions test platform for radiation faults measurement ; SEE error-rate prediction of circuits and systems Industrial transfer Patent pending with SYNOPSYS HIT hardened cell patent transferred to ESA SEU emulation tool transferred to ST Research keywords Fault tolerance, security, multi-core systems robustness, 3D circuits, aging, fault-injection Contact Raoul VELAZCO Michael NICOLAIDIS CNRS Research Director - TIMA CNRS Research Director – TIMA (+33) 476 57 46 89 (+33) 476 57 46 96 [email protected] [email protected] TIMA – Annual Report 2014 (ARIS) 7 8 TIMA – Annual Report 2014 (ARIS) The Cells Framework: Overal Description Members: Michael Nicolaidis, Lorena Anghel, Mounir Benabdenbi, Nacer-Eddine Zergainoh, Michael Dimopoulos, Fabien Chaix, Yi Gang, Panagiota Papavramidou Keywords: Ultimate CMOS and post-CMOS technologies, high defect densities, reliability, yield, low-power, massively parallel single-chip tera-device computers, Cooperation: STmicroelectronics, iRoC, Atmel, EADS Contracts: TOETS, Optimise, ELESIS, 3DIM3 Ultimate-CMOS and post-CMOS technologies single-chip massively parallel processors avoids promise integrating trillions devices in a single die, massive redundancy by using self-tests (hardware leading to single-chip massively parallel architectures implemented or software implemented to detect comprising thousands interconnected processors, and failures and create routing tables that are used enabling the next computation turn. But the subsequently to avoid failed processing nodes or aggressive technology scaling that paves the way to failed routes. However, such approaches could not the ultimate CMOS nodes has dramatic impact to: cope with the issues affecting ultimate CMOS and process, voltage and temperature (PVT) variations; post CMOS technologies as: sensitivity to electromagnetic interferences (EMI), to - In highly defective technologies, the vast majority of atmospheric radiation (neutrons and protons) and to nodes (processing elements and routers) may include alpha particles; and circuit aging. It also imposes one or another kind of faults (e.g. timing faults stringent power dissipation constraints. The resulting produced by process, voltage and temperature high defect levels, heterogeneous behavior of identical variations, EMI, or aging). Thus, declaring defective circuits, accelerated circuit degradation over time, and the nodes affected by any kind of faults will quickly extreme complexity, affect adversely fabrication yield waste the computational resources of the chip. and/or prevent fabricating reliable chips in ultimate -Achieving high fault coverage for timing faults