OCTEON Fusion CNF95xx Press Briefing Presentation CNF95xx Product Introduction Announcing Next Generation Family of OCTEON Fusion

. Industry-leading merchant silicon 5G macro cell baseband family . Supports traditional all-in-one macro and disaggregated Distributed Unit (DU) base station architectures . Delivers the performance of an ASIC with the flexibility of a processor CNF95xx is in volume production . May be tailored via differentiated IP integration with a Tier 1 OEM on a per customer basis

© 2020 Marvell confidential. All rights reserved. 2 A Long History of Compute Innovation

OCTEON Fusion OCTEON Fusion CNF75xx CNF95xx Macro Cell Macro Cell

OCTEON Fusion OCTEON Fusion OCTEON Fusion CNF7130 CNF73xx Semi-custom Small Cell Micro Cell Beamformer

2010 2015 2019 2020 2021

LTE LTE LTE 3G 2G 3G 2G 3G R9 R13 R14 5G

© 2020 Marvell confidential. All rights reserved. 3 OCTEON Fusion CNF95xx Architecture

PHY Subsystem OCTEON TX2 CPU Cores

• Software defined PHY cnMBP2 cnSBP2 DSP Core DSP Core Power • Arm v8.2 Architecture, Up to subsysatem Baseband BTS Sec Vault TrustZone 64K IS + 64K IMEM optimized DSPs 64K IMEM Management 2.6 GHz • Multi-core DSPs 128K DMEM x40 2x 256K DMEM SerDes

6x25G • Quad Issue, Out-of-order • 4G/5G Specific HW PHY SMEM BPHY Ethernet 24MB Pipeline accelerator blocks (ROE/Chip2Chip) SIMD SIMD DENC AES AES • 128b SIMD and floating-point • Dedicated large internal FPU FPU DLFE TDEC OCTEON TX2 System support XBAR SMMU 6 Cores SMEM VGIC MMU VGIC ULFE VDEC • Full ARM virtualization spec • High-speed non-blocking multi- FDEQ RDEC OCTEON TX2 OCTEON TX2 supporteda ported Interconnect Fabric DMAP LDEC • PHY Ethernet for and 66K I- 66K I-cache PDEC very low-latency chip-to-chip RMAP 41K D-cache 41K D-cache interface LENC PENC PHY Scheduler Up to 1.25MB iMLC Timers Low Latency SerDes

4x25G I/O & Co-Proc Ethernet Networks Crossbar at Core frequency SoC Interfaces 1/10/25GE NIX 50/100GE NPA Cache, Interconnect 3x Hyper App Acc Manager Up to 3.5MB Access • 25G SerDes support Misc I/O* Coherent LLC Memory • 100G/50G/25G/10G/1GbE Controller • Coherent MLC and LLC • Low-latency interconnect at core support *Boot/Flash, eMMC, SPI, GPIO, UART, 12C 2x 72b DDR4-2666 • Application acceleration speed manager for core workload • Up-to 2x DDR4-2666 MHz distribution • Packet IO acceleration support

© 2020 Marvell confidential. All rights reserved. 4 Multiple Business Model Options

BUY PARTNER BUILD

OCTEON Fusion Semi-custom CNF95xx- ASIC designed around CNF95xx Merchant based solutions OCTEON Fusion IP Solution Customer IP

Leading cellular baseband Leverage OCTEON Fusion for End-to-end technology supplier to infrastructure market related processing functions development Proven 10+ year track record Leading nodes and IP Software and ecosystem support

© 2020 Marvell confidential. All rights reserved. 5 5G Macro Cell All-in-One Example

Integrates to OCTEON TX2 Radio Units implements Layer using eCPRI 2 and 3 as well as Transport functions RoE/eCPRI RU (4x4 100Mhz) OCTEON TX2 OCTEON Fusion 25GbE 10/25/40GbE RU CN92XX (4x4 100Mhz) CNF95XX Midhaul/Backhaul

RU Layer 2 / Layer 3 (4x4 100Mhz) Layer 1 (MAC Scheduler RLC, PDCP, Transport, RU IPSec, Control) (4x4 100Mhz)

OCTEON Fusion implements 5G Layer 1

© 2020 Marvell confidential. All rights reserved. 6 5G O-RAN Architecture Design Example

Marvell complete Portfolio enables 5G system architectures, such as the one proposed by the ORAN Alliance, to scale deployments and achieve the best OPEX and CAPEX in the industry

RoE/eCPRI 4xRF 4x4x OCTEON Fusion RFRF4x4 100MHzRF CNF95XX 10/25GbE 25GbE 25GbE 25GbE 25GbE 4xRF OCTEON TX2 4x4x OCTEON Fusion OCTEON TX2 Prestera Prestera RFRF4x4 CN96XX ThunderX2 100MHzRF CNF95XX CN96XX 98CX85xx 98CX85xx (5G CORE) Ethernet Ethernet (PDCP, Transport, 4xRF 4x4x OCTEON Fusion (MAC Scheduler RLC) switch RF4x4 IPSec, Control) 100MHzRFRF CNF95XX

Lower L1 Upper L2 & Core Upper L1 Lower L2 RF L3 Network

Split 7.2 Split 6 Split 2

© 2020 Marvell confidential. All rights reserved. 7 OCTEON Fusion – Key Takeaways

. Industry-leading merchant silicon 5G macro cell baseband processor family . Supports traditional all-in-one macro and disaggregated Distributed Unit (DU) base station architectures . Delivers the performance of an ASIC with the flexibility of a processor . Currently in Volume production with a Tier1

© 2020 Marvell confidential. All rights reserved. 8