Digital Signal Processors: a Review

Total Page:16

File Type:pdf, Size:1020Kb

Digital Signal Processors: a Review International Journal of Scientific Engineering and Applied Science (IJSEAS) – Volume-2, Issue-5,May 2016 ISSN: 2395-3470 www.ijseas.com Digital Signal Processors: A Review 1 2 3 Nitin Lokhande , Satish Shirsath , Vilas Jadhav 1, 2, 3 Department of Instrumentation and Control, Pravara Rural Engineering College, Loni, Maharashtra, India Abstract such as mobile phones, PDA and different IT Digital Signal Processings is one of the challenging peripherals. These processors are uses distinct field and stand as important technology since last memory architecture which able to fetch multiple three decades. There are many revolutionary changes data and instructions in parallel way. This processor have been made in different fields such as provides low cost solution with good performance communication field, medical imaging, Radar, Sonar with lower latency, no requirement for specialized which involves the signal processing. This Signal cooling or large batteries. The architecture of such Processings includes many mathematical operations processors is specially designed and elevates to and data Processings. Signal related operation and handle discrete signals and their Processings with processing of data is carried out using specialized effectively less power consumption. Figure 1 shows microprocessor design to handle this type of task are the different footsteps involve in the digital signal digital signal processors. In this paper, we take Processings of any real time signal which is analog in review of DSP processors with types, architecture nature. Analog signals are generally audio, video or and applications, Programming aspects. similar type of analog signals. This type of signals converted in form of digital signal using analog to Keywords: DSP, Signal Processings, DSP digital conversion. Processors, DSP Architectures, Texas Instruments (TI), 1. Introduction Digital signal processing is different from other engineering field in terms of distinguishing feature, Fig. 1 Digital signal processing steps. signal as a data type. Signal data in most of time is The subsequent part of paper discusses the different real word signal data obtain from sensor or types of architectures, applications etc. transducers which is in form of speech, image, vibration, sound, seismic etc. To process this data we need mathematical operation, algorithms and some 2. Architectures of DSP Processor special techniques used to manipulate the signal i.e. Hardware architectures of DSP processors are varies for enhancement, compression, modulation, from general microprocessors. Following are conversion, etc. In the decades of 1960 and 1970, this different hardware architecture of processors. field is limited to some specific task such as security, • Von Neumann Architecture space, application in which data is irreplaceable and • Harvard Architecture where cost is not matter. After 1990 the DSP is used • Super Harvard Architecture for commercial application such as smart phone, CD players, voice devices, cameras and many types of such portable and processing devices. Now day’s different fields are dominated by DSP i.e. Space, Medical, Telephone, Security, Communication, Audio & Video applications, Vision System, Video Fig.2.a Von Neumann Architecture game etc. DSP processors are more efficient than microprocessors in terms power efficiency due to which they are faster and suitable in portable devices 393 International Journal of Scientific Engineering and Applied Science (IJSEAS) – Volume-2, Issue-5,May 2016 ISSN: 2395-3470 www.ijseas.com • Unsigned Integer: it takes number from 0- 65535. • Signed Integer: it takes number from -32768 Unsigned to 32768. • Unsigned fraction: the 65,536 levels are spread Fig.2.b Harvard Architecture uniformly between 0 and 1. • Signed fraction negative numbers, equally spaced between -1 and 1. In fact fixed-point means that the position of the fractional point is assumed to be fixed and to be the same for the operands and the result of an operation. Number of versatile embedded applications use fixed point processors because the priority is on low cost and low power. ADI DSP BF53X, TI’s TM320C54x, TM320C55x, TM320C62x, TM320C64x, Motorola MSC810x are types of fixed point processor. Fig.2.c Super Harvard Architecture (SHARC) 2.2 Floating Point Processors Programme and data memory for processing hence programme instructions and data can be fetched In the floating-point notation the position if the simultaneously leads to fast processing. Today’s binary point is explicitly represented in the data word. most of DSP processor of this designed type. Fig.2.c Floating point DSPs typically use a minimum of 32 shows next level of architecture designed and is bits to store each value. Distinct feature of floating called as SHARC which is abbreviation of Super point notation is that the represented numbers are not Harvard Architecture. It has some more features uniformly spaced. All floating point DSPs can which improve the output such as instruction cache process the fixed point numbers, a necessity to and I/O controller for interfacing of high speed implement counters, loops, and signals coming from devices. It has both parallel and serial communication the ADC and going to the DAC. ports. The SHARC DSPs are designed and optimized for DSPs are usually optimized for processing data and both floating point and fixed point operations, and used distinct memory architectures that are able to executes them with equal efficiency. Floating-point fetch multiple data and/or instructions at the same DSP processors can easily program than their fixed time, such as the Harvard architecture or point processors, but usually are also more expensive Modified von Neumann architecture.DSP processors and have higher power consumption. ADI ADSP are divided in two parts according to type of data 2116x/2126x, TI’s TMS320c67x are types of floating format it uses. According to that they are fixed point point processors. and floating point processors. There are many issue to select the floating and fixed point processor i.e. power requirement, cost and field of application. 3. Manufacturers of DSP Processor One of the most fundamental characteristics of a In DSP processor manufacturing LSI (Lucent, Agere), programmable digital signal processor is the type of Free scale Semiconductor (Motorola), Analog native arithmetic used in the processor. Devices, ZiLOG, Renesas, Microchip and Verisilicon, NJR,NXP, ON semiconductor, are manufacturing 2.1 Fixed Point Processors floating as well as fixed point processors. Analog In fixed point DSPs, each numbers is represented devices and TI DSP’s are mostly used for different with minimum 16 bits, although a different length operation and real time applications because they can be used. There are different pattern are used offer signal control, Power efficiency, high 216 = 65,535 represent the number for example, is performance and Multiprocessing task. represented in following different bit pattern. Table 1: DSP Manufacturer and family 394 International Journal of Scientific Engineering and Applied Science (IJSEAS) – Volume-2, Issue-5,May 2016 ISSN: 2395-3470 www.ijseas.com Manufacturer Families 4.2 PC code development tools Analog ADSP-21xx 16 bit, fixed Every DSP applications require the user interface Devices point on the PC. ADSP-21xxx 32 bit, floating For these purpose various software interfaces are provided. These interfaces allow a designer to DSP16xxx 16 bit fixed point Lucent develop PC applications that can access and use the Technologies DSP board. DSP32xx 32 bit floating • Several Dynamic Link Libraries (DLLs) are Motorola DSP561xx 16 bit fixed point provided to develop PC applications using any DSP560xx 24 bit, fixed development environment that supports the use of DLLs. Microsoft’s Visual Studio is an example. DSP96002 32 bit, floating Using these DLLs, the PC application can load DSP Texas TMS320Cxx 16 bit fixed code, execute it, and communicate with the board at TMS320Cxx 32 bit floating high and low levels. • An interface library is provided to develop PC applications using the Lab VIEW development environment from National Instruments. Using this 4. Programming of DSP library, the PC application can load DSP code, execute it, and communicate with the DSP board. DSP code can be developed using the Code MATLAB Code Generation and embedded target Composer Studio i.e. abbreviated as CCS products. development environment. This development environment is provided by Texas Instruments, and 4.3 DSP Peripheral-serial Interface contains the main following tools; Optimizing C Peripherals are considered amount of supported compiler, Assembler, Linker, Simulator. These tools interconnect and data I/O is huge. allow the development of DSP code in C++, C, or 1. Serial Peripheral Interface: It is synchronous assembly language, and generate an executable file serial link that supports communication with that can be downloaded to the DSP using the multiple SPI compatible devices. It has industry debugger. standard. High-performance simulators, emulator and 2. Multichannel buffered serial port this serial debugging facilities allow the developer to have a interface is based upon the standard serial port high visibility into the DSP without disturbing the found in different DSP. program execution. Additionally, multiple DSPs can 3. Multichannel Audio Serial Port on TI DSP be accessed in the same JTAG chain for both code this is a serial port optimized for the needs of development and debugging. multichannel audio applications.
Recommended publications
  • Chapter 5 Multiprocessors and Thread-Level Parallelism
    Computer Architecture A Quantitative Approach, Fifth Edition Chapter 5 Multiprocessors and Thread-Level Parallelism Copyright © 2012, Elsevier Inc. All rights reserved. 1 Contents 1. Introduction 2. Centralized SMA – shared memory architecture 3. Performance of SMA 4. DMA – distributed memory architecture 5. Synchronization 6. Models of Consistency Copyright © 2012, Elsevier Inc. All rights reserved. 2 1. Introduction. Why multiprocessors? Need for more computing power Data intensive applications Utility computing requires powerful processors Several ways to increase processor performance Increased clock rate limited ability Architectural ILP, CPI – increasingly more difficult Multi-processor, multi-core systems more feasible based on current technologies Advantages of multiprocessors and multi-core Replication rather than unique design. Copyright © 2012, Elsevier Inc. All rights reserved. 3 Introduction Multiprocessor types Symmetric multiprocessors (SMP) Share single memory with uniform memory access/latency (UMA) Small number of cores Distributed shared memory (DSM) Memory distributed among processors. Non-uniform memory access/latency (NUMA) Processors connected via direct (switched) and non-direct (multi- hop) interconnection networks Copyright © 2012, Elsevier Inc. All rights reserved. 4 Important ideas Technology drives the solutions. Multi-cores have altered the game!! Thread-level parallelism (TLP) vs ILP. Computing and communication deeply intertwined. Write serialization exploits broadcast communication
    [Show full text]
  • Computer Organization & Architecture Eie
    COMPUTER ORGANIZATION & ARCHITECTURE EIE 411 Course Lecturer: Engr Banji Adedayo. Reg COREN. The characteristics of different computers vary considerably from category to category. Computers for data processing activities have different features than those with scientific features. Even computers configured within the same application area have variations in design. Computer architecture is the science of integrating those components to achieve a level of functionality and performance. It is logical organization or designs of the hardware that make up the computer system. The internal organization of a digital system is defined by the sequence of micro operations it performs on the data stored in its registers. The internal structure of a MICRO-PROCESSOR is called its architecture and includes the number lay out and functionality of registers, memory cell, decoders, controllers and clocks. HISTORY OF COMPUTER HARDWARE The first use of the word ‘Computer’ was recorded in 1613, referring to a person who carried out calculation or computation. A brief History: Computer as we all know 2day had its beginning with 19th century English Mathematics Professor named Chales Babage. He designed the analytical engine and it was this design that the basic frame work of the computer of today are based on. 1st Generation 1937-1946 The first electronic digital computer was built by Dr John V. Atanasoff & Berry Cliford (ABC). In 1943 an electronic computer named colossus was built for military. 1946 – The first general purpose digital computer- the Electronic Numerical Integrator and computer (ENIAC) was built. This computer weighed 30 tons and had 18,000 vacuum tubes which were used for processing.
    [Show full text]
  • Parallel Computer Architecture
    Parallel Computer Architecture Introduction to Parallel Computing CIS 410/510 Department of Computer and Information Science Lecture 2 – Parallel Architecture Outline q Parallel architecture types q Instruction-level parallelism q Vector processing q SIMD q Shared memory ❍ Memory organization: UMA, NUMA ❍ Coherency: CC-UMA, CC-NUMA q Interconnection networks q Distributed memory q Clusters q Clusters of SMPs q Heterogeneous clusters of SMPs Introduction to Parallel Computing, University of Oregon, IPCC Lecture 2 – Parallel Architecture 2 Parallel Architecture Types • Uniprocessor • Shared Memory – Scalar processor Multiprocessor (SMP) processor – Shared memory address space – Bus-based memory system memory processor … processor – Vector processor bus processor vector memory memory – Interconnection network – Single Instruction Multiple processor … processor Data (SIMD) network processor … … memory memory Introduction to Parallel Computing, University of Oregon, IPCC Lecture 2 – Parallel Architecture 3 Parallel Architecture Types (2) • Distributed Memory • Cluster of SMPs Multiprocessor – Shared memory addressing – Message passing within SMP node between nodes – Message passing between SMP memory memory nodes … M M processor processor … … P … P P P interconnec2on network network interface interconnec2on network processor processor … P … P P … P memory memory … M M – Massively Parallel Processor (MPP) – Can also be regarded as MPP if • Many, many processors processor number is large Introduction to Parallel Computing, University of Oregon,
    [Show full text]
  • Digital Signal Processing – II
    www.jntuworld.com Digital Signal Processing – 8 December 24, 2009 VIII. DSP Processors 2007 Syllabus: Introduction to programmable DSPs: Multiplier and Multiplier-Accumulator (MAC), Modified bus structures and memory access schemes in DSPs, Multiple access memory, Multiport memory, VLSI architecture, Pipelining, Special addressing modes, On-chip peripherals. Architecture of TMS 320C5X – Introduction, Bus structure, Central Arithmetic Logic Unit, Auxiliary register, Index register, Auxiliary register, Compare register, Block move address register, Parallel Logic Unit, Memory mapped registers, Program controller, Some flags in the status registers, On-chip registers, On-chip peripherals. Contents: 8.1 DSP Processors – Market 8.2 DSP Processors – Features 8.3 Multiply-and-Accumulate 8.4 Interrupts – handling incoming signal values 8.5 Fixed- and Floating-point 8.6 Real-time FIR filter example We shall use “DSP” to mean Digital Signal Processor(s) and sometimes even refer to them as DSP processors, also as programmable digital signal processors (PDSPs). This includes 1. General purpose DSPs (such as the TMS320’s of TI and DSP563’s of Motorola and others) 2. Special purpose DSPs tailored to specific applications like FFT However, the so-called programmability of DSPs mentioned above pales in comparison to that of general purpose CPUs. In what follows, for the most part, we contrast general purpose CPUs (whose strength is in general purpose programmability) with DSPs (whose strength is in high throughput, hardwired, number crunching). For a
    [Show full text]
  • Computer Memory Architecture Pdf
    Computer memory architecture pdf Continue The methods used to implement the electronic computer storage memory architecture describe the methods used to implement electronic computer data storage, in such a way that it is a combination of the fastest, most reliable, most durable and least expensive way to store and obtain information. Depending on the application, one of these requirements may need to be compromised to improve the other requirement. Memory architecture also explains how binary digits are converted into electrical signals and then stored in memory cells. As well as the structure of the memory cell. For example, dynamic memory is commonly used for primary storage because of the fast speed of access. However, dynamic memory must be repeatedly updated with a spike of current dozens of times per second, or stored data will disintegrate and be lost. Flash memory allows you to store for years, but it's much slower than dynamic memory, and static memory storage cells wear out when used frequently. Similarly, the data bead is often designed to meet specific needs such as serial or parallel access to data, and memory can be designed to detect parity errors or even correct errors. The earliest memory architectures are Harvard Architecture, which has two physically separate memories and data transfer paths for the program and data, and Princeton's architecture, which uses a single path of memory and data for both the program and the storage of data. Most general-purpose computers use a hybrid split-cache modified Harvard architecture, which appears to be an application program to have a clean Princeton architectural machine with gigabytes of virtual memory, but internally (for speed) it works with a cache of instructions physically separate from a data cache more like the Harvard model.
    [Show full text]
  • Introduction to Computer Architecture
    Introduction to Computer Architecture Mark Bull, EPCC Building Blocks of HPC Systems Four principal technologies which make up HPC systems: • Processors • to calculate • Memory • for temporary storage of data • Interconnect • so processors can talk to each other (and the outside world) • Storage • disks for storing input/output data and tapes for long term archiving of data • These talks will focus on the first two of these. 2 Processors • Basic functionality • execute instructions to perform arithmetic operations (integer and floating point) • load data from memory and store data to memory • decide which instructions to execute next • Arithmetic is performed on values in registers (local storage in the processor) • moving data between memory and registers must be done explicitly by load and store instructions • separate integer and floating point registers • typical size ~100 values • Basic characteristics: • Clock speed • Peak floating point capability 3 Processors (cont.) • Clock speed determines rate at which instructions are executed • modern chips are around 2-3 GHz • integer and floating point calculations can be done in parallel • can also have multiple issue, e.g. simultaneous add and multiply • peak flop rate is just clock rate x no. of floating point operations per clock cycle • Whole series of hardware innovations • pipelining • out-of-order execution, speculative computation • ... • Details of these become important for extracting high performance • most features are fairly generic 4 Moore’s Law • “CPU power doubles every
    [Show full text]
  • Programmable Address Generation Unit for Deep Neural Network Accelerators
    DEGREE PROJECT IN ELECTRICAL ENGINEERING, SECOND CYCLE, 30 CREDITS STOCKHOLM, SWEDEN 2020 Programmable Address Generation Unit for Deep Neural Network Accelerators MUHAMMAD JAZIB KHAN KTH ROYAL INSTITUTE OF TECHNOLOGY SCHOOL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE KTH ROYAL INSTITUTE OF TECHNOLOGY Electrical Engineering and Computer Science Programmable Address Generation Unit for Deep Neural Network Accelerators Muhammad Jazib Khan Master in Electrical Engineering Supervisor KTH: Yu Yang Examiner: Prof. Ahmed Hemani School of Electrical Engineering and Computer Science Host company: Robert Bosch GmbH Supervisor Bosch: Sebastian Vogel and Dr. Leonardo Ecco Abstract The Convolutional Neural Networks are getting more and more popular due to their applications in revolutionary technologies like Autonomous Driving, Biomedical Imaging, and Natural Language Processing. With this increase in adoption, the complexity of underlying algorithms is also increasing. This trend entails implications for the computation platforms as well, i.e. GPUs, FPGA, or ASIC based accelerators, especially for the Address Generation Unit (AGU), which is responsible for the memory access. Existing accelerators typically have Parametrizable Datapath AGUs, which have minimal adaptability towards evolution in algorithms. Hence new hardware is required for new algorithms, which is a very inefficient approach in terms of time, resources, and reusability. In this research, six algorithms with different implications for hardware are evaluated for address generation, and a fully Programmable AGU (PAGU) is presented, which can adapt to these algorithms. These algorithms are Standard, Strided, Dilated, Upsampled and Padded convolution, and MaxPooling. The proposed AGU architecture is a Very Long Instruction Word based Application Specific Instruction Processor which has specialized components like hardware counters and zero-overhead loops and a powerful Instruction Set Architecture (ISA), which can model static and dynamic constraints and affine and non-affine Address Equations.
    [Show full text]
  • FPGA Implementation of RISC-Based Memory-Centric Processor Architecture
    (IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 10, No. 9, 2019 FPGA Implementation of RISC-based Memory-centric Processor Architecture Danijela Efnusheva1 Computer Science and Engineering Department Faculty of Electrical Engineering and Information Technologies Skopje, North Macedonia Abstract—The development of the microprocessor industry in by the strict separation of the processing and memory resources terms of speed, area, and multi-processing has resulted with in the computer system. In such processor-centric system the increased data traffic between the processor and the memory in a memory is used for storing data and programs, while the classical processor-centric Von Neumann computing system. In processor interprets and executes the program instructions in a order to alleviate the processor-memory bottleneck, in this paper sequential manner, repeatedly moving data from the main we are proposing a RISC-based memory-centric processor memory in the processor registers and vice versa, [1]. architecture that provides a stronger merge between the Assuming that there is no final solution for overcoming the processor and the memory, by adjusting the standard memory processor-memory bottleneck, modern computer systems hierarchy model. Indeed, we are developing a RISC-based implement different types of techniques for "mitigating" the processor that integrates the memory into the same chip die, and occurrence of this problem, [10], (ex. branch prediction thus provides direct access to the on-chip memory, without the use of general-purpose registers (GPRs) and cache memory. The algorithms, speculative and re-order instructions execution, proposed RISC-based memory-centric processor is described in data and instruction pre-fetching, and multithreading, etc.).
    [Show full text]
  • A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets
    IEEE TRANSACTIONS ON COMPUTERS, VOL. (VOL), NO. (NO), (MONTH) (YEAR) 1 A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets Fabian Schuiki, Michael Schaffner, Frank K. Gürkaynak, and Luca Benini, Fellow, IEEE Abstract—Most investigations into near-memory hardware accelerators for deep neural networks have primarily focused on inference, while the potential of accelerating training has received relatively little attention so far. Based on an in-depth analysis of the key computational patterns in state-of-the-art gradient-based training methods, we propose an efficient near-memory acceleration engine called NTX that can be used to train state-of-the-art deep convolutional neural networks at scale. Our main contributions are: (i) a loose coupling of RISC-V cores and NTX co-processors reducing offloading overhead by 7× over previously published results; (ii) an optimized IEEE 754 compliant data path for fast high-precision convolutions and gradient propagation; (iii) evaluation of near-memory computing with NTX embedded into residual area on the Logic Base die of a Hybrid Memory Cube; and (iv) a scaling analysis to meshes of HMCs in a data center scenario. We demonstrate a 2:7× energy efficiency improvement of NTX over contemporary GPUs at 4:4× less silicon area, and a compute performance of 1:2 Tflop=s for training large state-of-the-art networks with full floating-point precision. At the data center scale, a mesh of NTX achieves above 95% parallel and energy efficiency, while providing 2:1× energy savings or 3:1× performance improvement over a GPU-based system.
    [Show full text]
  • Computer Architectures & Hardware Programming 1
    COMPUTER ARCHITECTURES & HARDWARE PROGRAMMING 1 Dr. Varga, Imre University of Debrecen Department of IT Systems and Networks 06 February 2020 Requirements Practice (signature, only Hardware Programming 1) Visit classes (maximum absences: 3) 2 practical tests • All tests at least 50% 1 re-take chance (covers the whole semester) Lecture (exam, CA & HP1) Written exam Multiple choice + Calculation/Programming + Essay • At least 40% Computer Architectures Warning Lexical knowledge about the slides are necessary, but not enough to pass. Understanding is necessary, that is why active participating on lectures are advantages. Other literature can be also useful. Computer Architectures Computer Science Engineering computer science… …engineering Assembly Electronics programming Computer Programming Digital architectures languages 1-2 design Physics Operating Database systems systems Embedded Signals and systems systems System programming Computer Architectures Topics Number representation, datatype implementation Essential structure and work of CPUs Modern processors Concrete processor architecture Instruction-set, programming Aspects of programming closely related to the hardware Basics of digital technology from the point of view of the hardware Assembly programming Mapping high-level programming to low-level Computer Architectures The goal of the subject Giving knowledge about hardware Creating connection between … ‚programming’ and ‚electronics’ ‚abstract’ and ‚fundamental’ knowledge Deeper understanding of high-level programming
    [Show full text]
  • Choosing a DSP Processor Berkeley Design Technology, Inc
    Choosing a DSP Processor Berkeley Design Technology, Inc. Introduction A second feature shared by DSP processors is the ability to complete several accesses to memory in a sin- DSP processors are microprocessors designed to per- gle instruction cycle. This allows the processor to fetch form digital signal processing—the mathematical ma- an instruction while simultaneously fetching operands nipulation of digitally represented signals. Digital signal and/or storing the result of a previous instruction to processing is one of the core technologies in rapidly memory. For example, in calculating the vector dot prod- growing application areas such as wireless communica- uct for an FIR filter, most DSP processors are able to per- tions, audio and video processing, and industrial control. form a MAC while simultaneously loading the data Along with the rising popularity of DSP applications, the sample and coefficient for the next MAC. Such single- variety of DSP-capable processors has expanded greatly cycle multiple memory accesses are often subject to since the introduction of the first commercially success- many restrictions. Typically, all but one of the memory ful DSP chips in the early 1980s. Market research firm locations accessed must reside on-chip, and multiple Forward Concepts projects that sales of DSP processors memory accesses can only take place with certain in- will total U.S. $6.2 billion in 2000, a growth of 40 per- structions. To support simultaneous access of multiple cent over 1999. With semiconductor manufacturers vy- memory locations, DSP processors provide multiple on- ing for bigger shares of this booming market, designers’ chip buses, multi-ported on-chip memories, and in some choices will broaden even further in the next few years.
    [Show full text]
  • PRIME: a Novel Processing-In-Memory Architecture for Neural Network Computation in Reram-Based Main Memory
    PRIME: A Novel Processing-in-memory Architecture for Neural Network Computation in ReRAM-based Main Memory Ping Chi∗, Shuangchen Li∗, Cong Xu†, Tao Zhang‡, Jishen Zhao§, Yongpan Liu¶,YuWang¶ and Yuan Xie∗ ∗Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106, USA †HP Labs, Palo Alto, CA 94304, USA; ‡NVIDIA Corporation, Santa Clara, CA 95950, USA §Department of Computer Engineering, University of California, Santa Cruz, CA 95064, USA ¶Department of Electronic Engineering, Tsinghua University, Beijing 100084, China ∗Email: {pingchi, shuangchenli, yuanxie}@ece.ucsb.edu Abstract—Processing-in-memory (PIM) is a promising so- by leveraging 3D memory technologies [6] to integrate lution to address the “memory wall” challenges for future computation logic with the memory. computer systems. Prior proposed PIM architectures put ad- Recent work demonstrated that some emerging non- ditional computation logic in or near memory. The emerging metal-oxide resistive random access memory (ReRAM) has volatile memories, such as metal-oxide resistive random showed its potential to be used for main memory. Moreover, access memory (ReRAM) [7], spin-transfer torque mag- with its crossbar array structure, ReRAM can perform matrix- netic RAM (STT-RAM) [8], and phase change memory vector multiplication efficiently, and has been widely studied to (PCM) [9], have the capability of performing logic and accelerate neural network (NN) applications. In this work, we arithmetic operations beyond data storage. This allows the propose a novel PIM architecture, called PRIME, to accelerate NN applications in ReRAM based main memory. In PRIME, memory to serve both computation and memory functions, a portion of ReRAM crossbar arrays can be configured as promising a radical renovation of the relationship between accelerators for NN applications or as normal memory for a computation and memory.
    [Show full text]