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Xilinx Vivado HLS) “Using C Language (Tutorial & Implementation)” ENGG*6530: Reconfigurable Computing Systems Assignment #5: High Level Synthesis (Xilinx Vivado HLS) “Using C Language (Tutorial & Implementation)” Prof. Shawki Areibi School of Engineering, University of Guelph Winter 2021 Start Date: Wednesday, Week #7, 2021 Due Date: Wednesday, 11:00 PM, Week #8, 2021 Report in dropbox, Demo: - 1 Objectives: The purpose of this assignment is to: • Learn the basics of the Xilinx Vivado High Level Synthesis (HLS) CAD Flow: Design Entry, Synthesis and Simulation. • Learn how to improve performance using directives. • Learn how to improve area and resource utilization. • Understand the meaning of design exploration. • Create a complete Hardware/Software Co-design that integrates the Arm PS with an IP that you will create. 2 Introduction With ever-increasing system complexities, all major semiconductor road-maps have identified the need for moving to higher levels of abstraction in order to increase productivity in electronic system design. Most re- cently, many approaches and tools that claim to realize and support a design process at the so-called electronic system level (ESL) have emerged such as Xilinx Vivado HLS and Mentor Graphics Handel-C. The Vivado HLS tool converts an algorithmic description written in C-based design flow into hardware de- scription (RTL) This flow elevates the abstraction level from RTL to algorithms. High-level synthesis is essential for maintaining design productivity for large designs. High-Level Synthesis creates an RTL imple- mentation from C level source code, extracts control and dataflow from the source code implements the design based on defaults and user applied directives. Many implementation are possible from the same source de- scription: Smaller designs, faster designs, optimal designs. It also enables design exploration using different solutions. 1 3 Xilinx HLS Tutorials and Labs The main tools you will be using in this assignment are the Xilinx Vivado HLS and Xilinx Vivado Embedded Design Suite. The Xilinx Vivado HLS provides a flow where the user can enter his/her C/C++ program, simulate, and create a hardware implementation that can be mapped onto the FPGA. 1. First the Instructor/Lab Instructor will introduce you to the tools using a simple example (Matrix Mul- tiplication) without applying any directives. 2. You will then learn in more detail how to use the CAD tool, improve performance, improve area and create an IP that can be mapped onto and FPGA by going through the following Tutorials prepared by Xilinx: (a) Xilinx HLS Workshop Lab #1: This Xilinx lab provides a basic introduction to high-level synthe- sis using the Vivado HLS tool flow. No directives are applied in this tutorial. You will use Vivado HLS in GUI mode to create a project. You will simulate, synthesize, and implement the provided design. Go through the tutorial “Vivado HLS Design Flow Lab” which targets the Zed Board. Lab #1 Tutorial, Matrix Multiply (Vivado HLS Design Flow Xilinx Lab Handout) • Create a directory structure as follows: "C:\xup\hls\labs\lab1" • Copy the files matrixmul.cpp, matrixmul.h and matrixmul test.cpp from resources of lab1 on the web page to the directory you just created "C:\xup\hls\labs\lab1" • Follow the Tutorial step by step. • Find the answers to some questions posed in the Tutorial. • Notice that even though in this Xilinx Tutorial the baseline design (i.e., solution with no directives are applied) is exported, you will not be able to import it later with Vivado embed- ded unless you add the “INTERFACE” directive to the I/O ports (formal parameters of the matrixmul mat a t, mat b t and result t). • The user can use several interface directives such as blockram, s axilite, e.t.c • The Lab Instructor will help you to understand how you apply this directive. • There are also several questions posed in this Xilinx Workshop Lab#1 handout. Try to find the answers to the questions as you go through the handout. (b) Xilinx HLS Workshop Lab #2: This Xilinx lab introduces various techniques and directives which can be used in Vivado HLS to improve design performance. The design under consideration ac- cepts an image in a (custom) RGB format, converts it to the YUV color space, applies a filter to the YUV image and converts it back to RGB. Go through the tutorial “Improving Performance Lab” which targets the Zed Board. Lab #2 Tutorial, RGBYUV (Improving Performance Xilinx Lab Handout) • Create a directory structure as follows: 2 "C:\xup\hls\labs\lab2" • Copy the necessary files for this tutorial from resources of lab2 on the web page to the direc- tory you just created "C:\xup\hls\labs\lab2" • Follow the Tutorial step by step. • Try to find the answers to some questions posed in the Tutorial. • Helpful Hints: i. If you try to save the “Makefile” it will be saved with Makefile.txt extension. Remove the .txt extension from the Makefile.txt. ii. The same applies to the input.dat, output.dat and output.golden.dat files. Save them as .dat files. iii. The input.dat, output.dat and output.golden.dat should be saved in a sub-directory called test data. (c) Xilinx HLS Workshop Lab #3: This Xilinx lab introduces various techniques and directives which can be used in Vivado HLS to further improve design performance as well as area and resource utilization. The design under consideration performs discrete cosine transformation (DCT) on an 8x8 block of data. Follow the same instructions provided above for Lab#1 and Lab#2. Go through the tutorial “Improving Area and Resource Utilization Lab” which targets the Zed Board. Lab #3 Tutorial, DCT (Improving Area and Resource Utilization Xilinx Lab Handout) (d) Helpful Hints: i. If you try to save the “Makefile” it will be saved with Makefile.txt extension. Remove the .txt extension from the Makefile.txt. (e) Xilinx HLS Workshop Lab #4: This Xilinx lab introduces a design flow to generate a IP-XACT adapter from a design using Vivado HLS and using the generated IP-XACT adapter in a processor system using IP Integrator in Vivado. Go through the tutorial “Creating a Processor System Lab” which targets the Zed Board. Lab #4 Tutorial, FIR Filter (Creating a Processor System Xilinx Lab Handout) • Follow the same instructions provided above for Lab#1 and Lab#2. • Notice in this lab, you will be taught how to apply the INTERFACE directive to the formal parameters of the top function so that it can be exported correctly and later on imported as an IP that can communicate with the Processing System (i.e., ARM) via the s axilite. 3. All source code, makefile, data files are available on the website. 4. Each Workshop Lab section has its related resources. 3 4 Requirements 1. Follow the instructions and steps found in the Xilinx Workshop (Lab#1-Lab#4) and familiarize yourself with design entry and design exploration. 2. Answer all questions posed in the Tutorials of Xilinx Workshop (Lab#1 and Lab#2). 3. Apply different types of directives to the Matrix Multiplications of Xilinx Workshop Lab#1. (a) Show all possible solutions after applying individual directives (e.g., (A) loop unrolling, (B) Pipelining, (C) dataflow, (D) Function In-lining, (E) Array Partitioning Then find the effect of combining a subset of these directives. Create a table with all different solutions as the one shone in Table1 below. (b) This part is optional: (exporting your design and creating an IP) • It is important to notice that you will have to apply the INTERFACE Directive to the IO ports of the matrixmul before exporting it from HLS to be used later on with the Vivado Embedded. • For this assignment you will use the Option mode blockram. • A C code “matrixmul SDK.c” is created for you to be used in the SDK to initialize the block- ram and communicate values between the Matrix Multiplication IP and the ARM processor. (c) The Lab Instructor will assist you if you need help. Directives CLK CYC DSPs FFs LUTs Latency Speedup Baseline - - - - - - A(Unroll) - - - - - - B(Pipeline) - - - - - - C(Dataflow) - - - - - - D(Inline) - - - - - - E(Part) - - - - - - AE - - - - - - BE - - - - - - CE - - - - - - DE - - - - - - ABE - - - - - - ACE - - - - - - ADE - - - - - - BCE - - - - - - BDE - - - - - - CDE - - - - - - ABCE - - - - - - ABDE - - - - - - ACDE - - - - - - BCDE - - - - - - ABCDE - - - - - - Table 1: HLS: Design Exploration for Matrix Multiplication 4. Submit a detailed report summarizing your findings in terms of: (a) Design exploration of the Matrix Multiplication application. (b) Report Speedup achieved while applying directives (How to obtain Speedup?) (c) Discussion of the results you obtained. 4 (d) Any feedback on the usage of the Vivado HLS Tool. (e) Any problems you encountered during your implementations. (f) Any suggestion and future recommendation for the assignment. (g) Include your source C code if necessary. 5 5 Report Name your report ENG6530 W21 Assignment#5 LastNameFirstName.pdf When completed, you will hand in a report with the following deliverables: 1. The front page (i.e. title page) should contain only the following: • Course #, Course Name and Date • Your Name and ID • Assignment # and title of the assignment. 2. Explain your implementation by providing the following: (a) Problem Statement, i. Briefly describe the problem solved in the assignment. (b) Tools used: Vivado Revision used, locally installed on your computers or the version installed in RICH 1531 lab. (c) Assumptions and Constraints. (d) System Overview & Justification of Design i. Give an overview of the system to be designed. ii. Briefly explain how the system works and reasons behind the design. 3. Circuit/Block Diagram (a) Brief explanation of the hardware. (b) The schematic you produced using Xilinx Vivado HLS tool. 4. Software (a) List any new C code you developed based on the requirements. 5. Error Analysis (a) Describe any problems with the system (i.e., At what point in the tutorial you failed to complete the step.) (b) If no problems in the final system, describe problems/errors encountered during the development and how they were resolved.
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