3.1.1.AK Sequential Logic: D Flip-Flops and J/K Flip-Flops (15 Pt)

3.1.1.AK Sequential Logic: D Flip-Flops and J/K Flip-Flops (15 pt)

Introduction Flip-flops are the fundamental building blocks of sequential logic. There are a variety of different flip-flop types and configurations. In this activity (and this course) we will only be studying two types of flip-flop: the D flip-flop which was introduced in Unit 1 and the J/K flip-flop. After reviewing the basic operation of the 74LS74 D and the 74LS76 J/K flip-flops, this activity will examine two applications of flip-flops.

Note: Where did these flip-flops get their name? The D in the D flip-flop stands for data. No one is absolutely sure where the J/K name originated but one theory is that it is named after Jack Kilby, the inventor of the integrated circuit. Equipment  Circuit Design Software (CDS)  Digital MiniSystem (DMS) o myDAQ o myDigital Protoboard o Cmod S6 FPGA Module  #22 Gauge solid wire

Procedure Before we jump into a discussion of practical applications of J/K or D flip-flops, let’s first make sure that you have a solid understanding of how these flip-flops work.

© 2014 Project Lead The Way, Inc. Digital Electronics ANSWER KEY 3.1.1 Sequential Logic: D Flip-Flops and J/K Flip-Flops – Page 1 1. For the 74LS74 D flip-flop shown below, complete the timing diagram for the output signal Que. Note that the CLK input for this flip-flop is a positive edge trigger and both the PR and CLR asynchronous inputs are active low. (1pt)

Que

Dee

Preset

Clear

Clock

2. For the 74LS76 J/K flip-flop shown below, complete the timing diagram for the output signal Que. Note that the CLK input for this flip-flop is a negative edge trigger and both the PR and CLR asynchronous inputs are active low. (1pt)

Que

Jay

Kay

Preset

Clear

Clock

3. When flip-flops were discussed briefly back in unit (1), we saw that a D flip-flop could be used to create a Divide-By-Two circuit. Remember, a Divide-By-Two circuit is one that generates a clock output that is half the frequency of the clock input. Likewise, a Divide-By-Two circuit can be implemented with a J/K flip-flop. See below.

J/K Divide-By-Two Circuit

a. Complete the timing diagram shown below for a J/K Divide-By-Two circuit. (1pt)

Clock_Out

Clock_In

b. Using the CDS, enter the Divide-By-Two circuit. Add an oscilloscope to monitor the two signals Clock_In and Clock_Out. Run the simulation and capture several periods of the output signal. Verify that the circuit is working as expected and that the output signal matches the predictions from step (a). If the results do not match, review your work and make any necessary corrections. Either print this off or demonstrate it for your instructor. (1pt)

© 2014 Project Lead The Way, Inc. Digital Electronics ANSWER KEY 3.1.1 Sequential Logic: D Flip-Flops and J/K Flip-Flops – Page 3 4. Change the frequency of Clock_In to 20 kHz and re-simulate. What effect did this change have on the frequency of the output signal Clock_Out? (1pt) No change. The output frequency is still half of the input frequency.

5. The circuit shown below generates two non-overlapping signals at the same frequency. These signals, C-OUT1 and C-OUT2, were frequently used by early microprocessor systems that required four different clock transitions all synchronized by one clock. Either print this off or demonstrate it for your instructor. (1pt)

Non-Overlapping Signal Generator

a. Complete the timing diagram shown below for the Non-Overlapping Signal Generator circuit. (2pt)

C-OUT2

C-OUT1

Que_Not

Que

Clock

© 2014 Project Lead The Way, Inc. Digital Electronics ANSWER KEY 3.1.1 Sequential Logic: D Flip-Flops and J/K Flip-Flops – Page 4 b. Using the CDS, enter the Non-Overlapping Signal Generator circuit. Add an oscilloscope to monitor the three signals Clock, C-OUT1, and C-OUT2. Run the simulation and capture several periods of the output signals. Verify that the circuit is working as expected and the output signals match the predictions from step (a). If the results do not match, review your work and make any necessary corrections.

c. The input signal, Clock, was a 1 kHz square wave with a 50% duty cycle. What is the frequency and duty cycle of the output signals C-OUT1 and C-OUT2? Frequency = 500Hz; Duty Cycle = 25% (1pt) d. Change the frequency of Clock to a 2 KHz and re-simulate. What effect did this change have on the frequency of the output signals C-OUT1 and C-OUT2? No change. The output frequency is still half of the input frequency. (1pt)

e. What effect did this change have on the duty cycle of the output signals C-OUT1 and C-OUT2? None (1pt)

© 2014 Project Lead The Way, Inc. Digital Electronics ANSWER KEY 3.1.1 Sequential Logic: D Flip-Flops and J/K Flip-Flops – Page 5 Conclusion 1. Flip-flops have both synchronous and asynchronous inputs. Describe each input type and give an example of each. (1pt)  Asynchronous inputs - Flip-flop inputs that can affect the operation of the flip-flop independent of the synchronous and clock inputs. (Preset and Clear)  Synchronous inputs – Inputs that are read in the rising or falling edge of the clock signal. (J-K and D) 2. Match each of the four input symbols with their signal type. (2pt)

Positive Edge Trigger

Active Low Input

Negative Edge Trigger

Active High Input

3. Describe the functional difference between a D flip-flop and a D latch. (1pt)  The primary difference between a D flip-flop and D latch is the EN/CLOCK input.  The flip-flop’s CLOCK input is edge sensitive, meaning the flip-flop’s output changes on the edge (rising or falling) of the CLOCK input.  The latch’s EN input is level sensitive, meaning the latch’s output changes on the level (high or low) of the EN input.