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Hamming Weight Attacks on Cryptographic Hardware – Breaking Masking Defense?
Hamming Weight Attacks on Cryptographic Hardware { Breaking Masking Defense? Marcin Gomu lkiewicz1 and Miros law Kuty lowski12 1 Cryptology Centre, Poznan´ University 2 Institute of Mathematics, Wroc law University of Technology, ul. Wybrzeze_ Wyspianskiego´ 27 50-370 Wroc law, Poland Abstract. It is believed that masking is an effective countermeasure against power analysis attacks: before a certain operation involving a key is performed in a cryptographic chip, the input to this operation is com- bined with a random value. This has to prevent leaking information since the input to the operation is random. We show that this belief might be wrong. We present a Hamming weight attack on an addition operation. It works with random inputs to the addition circuit, hence masking even helps in the case when we cannot control the plaintext. It can be applied to any round of the encryption. Even with moderate accuracy of measuring power consumption it de- termines explicitly subkey bits. The attack combines the classical power analysis (over Hamming weight) with the strategy of the saturation at- tack performed using a random sample. We conclude that implementing addition in cryptographic devices must be done very carefully as it might leak secret keys used for encryption. In particular, the simple key schedule of certain algorithms (such as IDEA and Twofish) combined with the usage of addition might be a serious danger. Keywords: cryptographic hardware, side channel cryptanalysis, Ham- ming weight, power analysis 1 Introduction Symmetric encryption algorithms are often used to protect data stored in inse- cure locations such as hard disks, archive copies, and so on. -
AVRDUDE a Program for Download/Uploading AVR Microcontroller flash and Eeprom
AVRDUDE A program for download/uploading AVR microcontroller flash and eeprom. For AVRDUDE, Version 6.0rc1, 16 May 2013. by Brian S. Dean Send comments on AVRDUDE to [email protected]. Use http://savannah.nongnu.org/bugs/?group=avrdude to report bugs. Copyright c 2003,2005 Brian S. Dean Copyright c 2006 - 2008 J¨orgWunsch Permission is granted to make and distribute verbatim copies of this manual provided the copyright notice and this permission notice are preserved on all copies. Permission is granted to copy and distribute modified versions of this manual under the con- ditions for verbatim copying, provided that the entire resulting derived work is distributed under the terms of a permission notice identical to this one. Permission is granted to copy and distribute translations of this manual into another lan- guage, under the above conditions for modified versions, except that this permission notice may be stated in a translation approved by the Free Software Foundation. i Table of Contents 1 Introduction............................... 1 1.1 History and Credits ......................................... 2 2 Command Line Options .................... 4 2.1 Option Descriptions ......................................... 4 2.2 Programmers accepting extended parameters ................. 15 2.3 Example Command Line Invocations ........................ 18 3 Terminal Mode Operation ................. 22 3.1 Terminal Mode Commands.................................. 22 3.2 Terminal Mode Examples ................................... 23 4 Configuration -
2.5 Classification of Parallel Computers
52 // Architectures 2.5 Classification of Parallel Computers 2.5 Classification of Parallel Computers 2.5.1 Granularity In parallel computing, granularity means the amount of computation in relation to communication or synchronisation Periods of computation are typically separated from periods of communication by synchronization events. • fine level (same operations with different data) ◦ vector processors ◦ instruction level parallelism ◦ fine-grain parallelism: – Relatively small amounts of computational work are done between communication events – Low computation to communication ratio – Facilitates load balancing 53 // Architectures 2.5 Classification of Parallel Computers – Implies high communication overhead and less opportunity for per- formance enhancement – If granularity is too fine it is possible that the overhead required for communications and synchronization between tasks takes longer than the computation. • operation level (different operations simultaneously) • problem level (independent subtasks) ◦ coarse-grain parallelism: – Relatively large amounts of computational work are done between communication/synchronization events – High computation to communication ratio – Implies more opportunity for performance increase – Harder to load balance efficiently 54 // Architectures 2.5 Classification of Parallel Computers 2.5.2 Hardware: Pipelining (was used in supercomputers, e.g. Cray-1) In N elements in pipeline and for 8 element L clock cycles =) for calculation it would take L + N cycles; without pipeline L ∗ N cycles Example of good code for pipelineing: §doi =1 ,k ¤ z ( i ) =x ( i ) +y ( i ) end do ¦ 55 // Architectures 2.5 Classification of Parallel Computers Vector processors, fast vector operations (operations on arrays). Previous example good also for vector processor (vector addition) , but, e.g. recursion – hard to optimise for vector processors Example: IntelMMX – simple vector processor. -
SIMD Extensions
SIMD Extensions PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 12 May 2012 17:14:46 UTC Contents Articles SIMD 1 MMX (instruction set) 6 3DNow! 8 Streaming SIMD Extensions 12 SSE2 16 SSE3 18 SSSE3 20 SSE4 22 SSE5 26 Advanced Vector Extensions 28 CVT16 instruction set 31 XOP instruction set 31 References Article Sources and Contributors 33 Image Sources, Licenses and Contributors 34 Article Licenses License 35 SIMD 1 SIMD Single instruction Multiple instruction Single data SISD MISD Multiple data SIMD MIMD Single instruction, multiple data (SIMD), is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously. Thus, such machines exploit data level parallelism. History The first use of SIMD instructions was in vector supercomputers of the early 1970s such as the CDC Star-100 and the Texas Instruments ASC, which could operate on a vector of data with a single instruction. Vector processing was especially popularized by Cray in the 1970s and 1980s. Vector-processing architectures are now considered separate from SIMD machines, based on the fact that vector machines processed the vectors one word at a time through pipelined processors (though still based on a single instruction), whereas modern SIMD machines process all elements of the vector simultaneously.[1] The first era of modern SIMD machines was characterized by massively parallel processing-style supercomputers such as the Thinking Machines CM-1 and CM-2. These machines had many limited-functionality processors that would work in parallel. -
UNIT 8B a Full Adder
UNIT 8B Computer Organization: Levels of Abstraction 15110 Principles of Computing, 1 Carnegie Mellon University - CORTINA A Full Adder C ABCin Cout S in 0 0 0 A 0 0 1 0 1 0 B 0 1 1 1 0 0 1 0 1 C S out 1 1 0 1 1 1 15110 Principles of Computing, 2 Carnegie Mellon University - CORTINA 1 A Full Adder C ABCin Cout S in 0 0 0 0 0 A 0 0 1 0 1 0 1 0 0 1 B 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 C S out 1 1 0 1 0 1 1 1 1 1 ⊕ ⊕ S = A B Cin ⊕ ∧ ∨ ∧ Cout = ((A B) C) (A B) 15110 Principles of Computing, 3 Carnegie Mellon University - CORTINA Full Adder (FA) AB 1-bit Cout Full Cin Adder S 15110 Principles of Computing, 4 Carnegie Mellon University - CORTINA 2 Another Full Adder (FA) http://students.cs.tamu.edu/wanglei/csce350/handout/lab6.html AB 1-bit Cout Full Cin Adder S 15110 Principles of Computing, 5 Carnegie Mellon University - CORTINA 8-bit Full Adder A7 B7 A2 B2 A1 B1 A0 B0 1-bit 1-bit 1-bit 1-bit ... Cout Full Full Full Full Cin Adder Adder Adder Adder S7 S2 S1 S0 AB 8 ⁄ ⁄ 8 C 8-bit C out FA in ⁄ 8 S 15110 Principles of Computing, 6 Carnegie Mellon University - CORTINA 3 Multiplexer (MUX) • A multiplexer chooses between a set of inputs. D1 D 2 MUX F D3 D ABF 4 0 0 D1 AB 0 1 D2 1 0 D3 1 1 D4 http://www.cise.ufl.edu/~mssz/CompOrg/CDAintro.html 15110 Principles of Computing, 7 Carnegie Mellon University - CORTINA Arithmetic Logic Unit (ALU) OP 1OP 0 Carry In & OP OP 0 OP 1 F 0 0 A ∧ B 0 1 A ∨ B 1 0 A 1 1 A + B http://cs-alb-pc3.massey.ac.nz/notes/59304/l4.html 15110 Principles of Computing, 8 Carnegie Mellon University - CORTINA 4 Flip Flop • A flip flop is a sequential circuit that is able to maintain (save) a state. -
Type I Codes Over GF(4)
Type I Codes over GF(4) Hyun Kwang Kim¤ San 31, Hyoja Dong Department of Mathematics Pohang University of Science and Technology Pohang, 790-784, Korea e-mail: [email protected] Dae Kyu Kim School of Electronics & Information Engineering Chonbuk National University Chonju, Chonbuk 561-756, Korea e-mail: [email protected] Jon-Lark Kimy Department of Mathematics University of Louisville Louisville, KY 40292, USA e-mail: [email protected] Abstract It was shown by Gaborit el al. [10] that a Euclidean self-dual code over GF (4) with the property that there is a codeword whose Lee weight ´ 2 (mod 4) is of interest because of its connection to a binary singly-even self-dual code. Such a self-dual code over GF (4) is called Type I. The purpose of this paper is to classify all Type I codes of lengths up to 10 and extremal Type I codes of length 12, and to construct many new extremal Type I codes over GF (4) of ¤The present study was supported by Com2MaC-KOSEF, POSTECH BSRI research fund, and grant No. R01-2006-000-11176-0 from the Basic Research Program of the Korea Science & Engineering Foundation. ycorresponding author, supported in part by a Project Completion Grant from the University of Louisville. 1 lengths from 14 to 22 and 34. As a byproduct, we construct a new extremal singly-even self-dual binary [36; 18; 8] code, and a new ex- tremal singly-even self-dual binary [68; 34; 12] code with a previously unknown weight enumerator W2 for ¯ = 95 and γ = 1. -
Arxiv:1311.6244V1 [Physics.Comp-Ph] 25 Nov 2013
An efficient implementation of Slater-Condon rules Anthony Scemama,∗ Emmanuel Giner November 26, 2013 Abstract Slater-Condon rules are at the heart of any quantum chemistry method as they allow to simplify 3N- dimensional integrals as sums of 3- or 6-dimensional integrals. In this paper, we propose an efficient implementation of those rules in order to identify very rapidly which integrals are involved in a matrix ele- ment expressed in the determinant basis set. This implementation takes advantage of the bit manipulation instructions on x86 architectures that were introduced in 2008 with the SSE4.2 instruction set. Finding which spin-orbitals are involved in the calculation of a matrix element doesn't depend on the number of electrons of the system. In this work we consider wave functions Ψ ex- For two determinants which differ by two spin- pressed as linear combinations of Slater determinants orbitals: D of orthonormal spin-orbitals φ(r): jl hDjO1jDiki = 0 (4) X Ψ = c D (1) jl i i hDjO2jDiki = hφiφkjO2jφjφli − hφiφkjO2jφlφji i All other matrix elements involving determinants Using the Slater-Condon rules,[1, 2] the matrix ele- with more than two substitutions are zero. ments of any one-body (O1) or two-body (O2) oper- An efficient implementation of those rules requires: ator expressed in the determinant space have simple expressions involving one- and two-electron integrals 1. to find the number of spin-orbital substitutions in the spin-orbital space. The diagonal elements are between two determinants given by: 2. to find which spin-orbitals are involved in the X substitution hDjO1jDi = hφijO1jφii (2) i2D 3. -
AVRDUDE a Program for Download/Uploading AVR Microcontroller Flash and Eeprom
AVRDUDE A program for download/uploading AVR microcontroller flash and eeprom. For AVRDUDE, Version 5.10, 19 January 2010. by Brian S. Dean Send comments on AVRDUDE to [email protected]. Use http://savannah.nongnu.org/bugs/?group=avrdude to report bugs. Copyright c 2003,2005 Brian S. Dean Copyright c 2006 - 2008 J¨orgWunsch Permission is granted to make and distribute verbatim copies of this manual provided the copyright notice and this permission notice are preserved on all copies. Permission is granted to copy and distribute modified versions of this manual under the con- ditions for verbatim copying, provided that the entire resulting derived work is distributed under the terms of a permission notice identical to this one. Permission is granted to copy and distribute translations of this manual into another lan- guage, under the above conditions for modified versions, except that this permission notice may be stated in a translation approved by the Free Software Foundation. i Table of Contents 1 Introduction::::::::::::::::::::::::::::::::::::: 1 1.1 History and Credits :::::::::::::::::::::::::::::::::::::::::::: 2 2 Command Line Options :::::::::::::::::::::::: 3 2.1 Option Descriptions :::::::::::::::::::::::::::::::::::::::::::: 3 2.2 Programmers accepting extended parameters :::::::::::::::::: 13 2.3 Example Command Line Invocations :::::::::::::::::::::::::: 15 3 Terminal Mode Operation :::::::::::::::::::: 19 3.1 Terminal Mode Commands :::::::::::::::::::::::::::::::::::: 19 3.2 Terminal Mode Examples ::::::::::::::::::::::::::::::::::::: -
An Introduction to Gpus, CUDA and Opencl
An Introduction to GPUs, CUDA and OpenCL Bryan Catanzaro, NVIDIA Research Overview ¡ Heterogeneous parallel computing ¡ The CUDA and OpenCL programming models ¡ Writing efficient CUDA code ¡ Thrust: making CUDA C++ productive 2/54 Heterogeneous Parallel Computing Latency-Optimized Throughput- CPU Optimized GPU Fast Serial Scalable Parallel Processing Processing 3/54 Why do we need heterogeneity? ¡ Why not just use latency optimized processors? § Once you decide to go parallel, why not go all the way § And reap more benefits ¡ For many applications, throughput optimized processors are more efficient: faster and use less power § Advantages can be fairly significant 4/54 Why Heterogeneity? ¡ Different goals produce different designs § Throughput optimized: assume work load is highly parallel § Latency optimized: assume work load is mostly sequential ¡ To minimize latency eXperienced by 1 thread: § lots of big on-chip caches § sophisticated control ¡ To maXimize throughput of all threads: § multithreading can hide latency … so skip the big caches § simpler control, cost amortized over ALUs via SIMD 5/54 Latency vs. Throughput Specificaons Westmere-EP Fermi (Tesla C2050) 6 cores, 2 issue, 14 SMs, 2 issue, 16 Processing Elements 4 way SIMD way SIMD @3.46 GHz @1.15 GHz 6 cores, 2 threads, 4 14 SMs, 48 SIMD Resident Strands/ way SIMD: vectors, 32 way Westmere-EP (32nm) Threads (max) SIMD: 48 strands 21504 threads SP GFLOP/s 166 1030 Memory Bandwidth 32 GB/s 144 GB/s Register File ~6 kB 1.75 MB Local Store/L1 Cache 192 kB 896 kB L2 Cache 1.5 MB 0.75 MB -
Cuda C Programming Guide
CUDA C PROGRAMMING GUIDE PG-02829-001_v10.0 | October 2018 Design Guide CHANGES FROM VERSION 9.0 ‣ Documented restriction that operator-overloads cannot be __global__ functions in Operator Function. ‣ Removed guidance to break 8-byte shuffles into two 4-byte instructions. 8-byte shuffle variants are provided since CUDA 9.0. See Warp Shuffle Functions. ‣ Passing __restrict__ references to __global__ functions is now supported. Updated comment in __global__ functions and function templates. ‣ Documented CUDA_ENABLE_CRC_CHECK in CUDA Environment Variables. ‣ Warp matrix functions now support matrix products with m=32, n=8, k=16 and m=8, n=32, k=16 in addition to m=n=k=16. www.nvidia.com CUDA C Programming Guide PG-02829-001_v10.0 | ii TABLE OF CONTENTS Chapter 1. Introduction.........................................................................................1 1.1. From Graphics Processing to General Purpose Parallel Computing............................... 1 1.2. CUDA®: A General-Purpose Parallel Computing Platform and Programming Model.............3 1.3. A Scalable Programming Model.........................................................................4 1.4. Document Structure...................................................................................... 5 Chapter 2. Programming Model............................................................................... 7 2.1. Kernels......................................................................................................7 2.2. Thread Hierarchy........................................................................................ -
Faster Population Counts Using AVX2 Instructions
Faster Population Counts Using AVX2 Instructions Wojciech Mula,Nathan Kurz and Daniel Lemire∗ ?Universit´edu Qu´ebec (TELUQ), Canada Email: [email protected] Counting the number of ones in a binary stream is a common operation in database, information-retrieval, cryptographic and machine-learning applications. Most processors have dedicated instructions to count the number of ones in a word (e.g., popcnt on x64 processors). Maybe surprisingly, we show that a vectorized approach using SIMD instructions can be twice as fast as using the dedicated instructions on recent Intel processors. The benefits can be even greater for applications such as similarity measures (e.g., the Jaccard index) that require additional Boolean operations. Our approach has been adopted by LLVM: it is used by its popular C compiler (Clang). Keywords: Software Performance; SIMD Instructions; Vectorization; Bitset; Jaccard Index 1. INTRODUCTION phy [5], e.g., as part of randomness tests [6] or to generate pseudo-random permutations [7]. They can help find We can represent all sets of integers in f0; 1;:::; 63g duplicated web pages [8]. They are frequently used in using a single 64-bit word. For example, the word 0xAA bioinformatics [9, 10, 11], ecology [12], chemistry [13], (0b10101010) represents the set f1; 3; 5; 7g. Intersections and so forth. Gueron and Krasnov use population-count and unions between such sets can be computed using instructions as part of a fast sorting algorithm [14]. a single bitwise logical operation on each pair of words The computation of the population count is so (AND, OR). We can generalize this idea to sets of important that commodity processors have dedicated integers in f0; 1; : : : ; n − 1g using dn=64e 64-bit words. -
With Extreme Scale Computing the Rules Have Changed
With Extreme Scale Computing the Rules Have Changed Jack Dongarra University of Tennessee Oak Ridge National Laboratory University of Manchester 11/17/15 1 • Overview of High Performance Computing • With Extreme Computing the “rules” for computing have changed 2 3 • Create systems that can apply exaflops of computing power to exabytes of data. • Keep the United States at the forefront of HPC capabilities. • Improve HPC application developer productivity • Make HPC readily available • Establish hardware technology for future HPC systems. 4 11E+09 Eflop/s 362 PFlop/s 100000000100 Pflop/s 10000000 10 Pflop/s 33.9 PFlop/s 1000000 1 Pflop/s SUM 100000100 Tflop/s 166 TFlop/s 1000010 Tflop /s N=1 1 Tflop1000/s 1.17 TFlop/s 100 Gflop/s100 My Laptop 70 Gflop/s N=500 10 59.7 GFlop/s 10 Gflop/s My iPhone 4 Gflop/s 1 1 Gflop/s 0.1 100 Mflop/s 400 MFlop/s 1994 1996 1998 2000 2002 2004 2006 2008 2010 2012 2014 2015 1 Eflop/s 1E+09 420 PFlop/s 100000000100 Pflop/s 10000000 10 Pflop/s 33.9 PFlop/s 1000000 1 Pflop/s SUM 100000100 Tflop/s 206 TFlop/s 1000010 Tflop /s N=1 1 Tflop1000/s 1.17 TFlop/s 100 Gflop/s100 My Laptop 70 Gflop/s N=500 10 59.7 GFlop/s 10 Gflop/s My iPhone 4 Gflop/s 1 1 Gflop/s 0.1 100 Mflop/s 400 MFlop/s 1994 1996 1998 2000 2002 2004 2006 2008 2010 2012 2014 2015 1E+10 1 Eflop/s 1E+09 100 Pflop/s 100000000 10 Pflop/s 10000000 1 Pflop/s 1000000 SUM 100 Tflop/s 100000 10 Tflop/s N=1 10000 1 Tflop/s 1000 100 Gflop/s N=500 100 10 Gflop/s 10 1 Gflop/s 1 100 Mflop/s 0.1 1996 2002 2020 2008 2014 1E+10 1 Eflop/s 1E+09 100 Pflop/s 100000000 10 Pflop/s 10000000 1 Pflop/s 1000000 SUM 100 Tflop/s 100000 10 Tflop/s N=1 10000 1 Tflop/s 1000 100 Gflop/s N=500 100 10 Gflop/s 10 1 Gflop/s 1 100 Mflop/s 0.1 1996 2002 2020 2008 2014 • Pflops (> 1015 Flop/s) computing fully established with 81 systems.