Eindhoven University of Technology
MASTER
A main-processor board for THE KUNix machine based on the 68010 microprocessor
v.d. Heuvel, W.
Award date: 1984
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UNIVERSITY OF TECHNOLOGY EINDHOVEN DEPARTMENT OF ELECTRICAL ENGINEERING Group Digital Systems
Graduation report:
A main-processor board
for THE KUNix machine based
on the 68010 micro-processor
by
W. v.d. Heuvel
Coach ing. L. v. 80khoven Supervising coach: prof. ir. A. Heetman
Period 01/09/1984-30/08/1984
Eindhoven, august 1984
The DEPARTMENT of ELECTRICAL ENGINEERING of the UNIVERSITY of TECHNOLOGY EINDHOVEN does not accept any responsibility for the contents of graduation reports. SUMMARY
This report describes the hardware of the new 68919 board for THE KUNix machine. It also contains some specifications of THE KUNix machine itself. Special attention is paid to the interprocessor communications mechanisms in the machine. On a number of points the considerations, leading to a certain implementation of a function, are clarified. The new board supports stand alone operation. It can be used not only in THE KUNix machine environment but also in a work station. Provisions are made to allow for a network controller to be used as communications device. The new design has not yet been tested. This report must serve as a guide during the test phase. It also contains some hints as to where improvement is possible. For software developers this report contains the information necessary to write the system software for the new design.
ACKNOWLEDGEMENT
I want to express my sincere thanks to all staff members of the Digital Systems group of the department of Electrical Engeneering. In particular mister Leo van Bokhoven, my coach, for his excellent coaching and professor A. Heetman my supervising coach. Special thanks to mister A. Chambone and mister Q. van Laarhoven who put the design drawings in the computer. From the University of Nijmegen I want to thank mister Jelte Feenstra for his suggestions. And last but not least my fellow students who helped me in times of distress.
w. v.d. Heuvel TABLE OF CONTENTS
1 INTRODUCTION 3 2 SPEC IFI CAT IONS AND GENERAL DESCR I PT ION 8 2.1 VHE bus and local extension bus 19 2.2 Memory considerations 11 2.3 Inter-processor communication 16 2.4 On-board I/O 21 2.5 Address mappi ng 22 2.5.1 Local address map 22 2.5.2 VHE address map 24 2.6 Miscellaneous functions 26 3 IMPLEMENTATION AND BLOCK DIAGRAMS 28 3.1 CPU and memory management 29 3.1.1 Central processing unit: 68010 39 3.1.2 Memory management mechanism 31 3.1.3 Interrup logic 33 3.1.4 Bus request arbitration 39 3.1.5 Halt and reset control 49 3.2 Local I/O and ROM 41 3.2.1 Error register 42 3.2.2 Identity register 44 3.2.3 Parallel interface 44 3.2.4 Timers 46 3.2.5 Serial I/O 47 3.2.6 Read only memory 48 3.3 Local address decoder 49 3.4 Local functions 50 3.5 Dual ported memory 52 3.6 Dual port I/O and interrupt vector register 56 3.7 VHE address decoder 59 3 •8 VHE fun c t i ons 6 1 3.8.1 Bus requester module 61 3.8.2 Bus master module 63 3.8.3 Interrupter module 64 4 CONCLUSIONS AND RECOHMENDATIONS 66 5 LITRATURE 69
PAGE 1 TABLE OF CONTENTS (continued)
APPENDICES:
A Schematic drawings 71 B Programmable logic functions 85 C Timing diagrams 117 D Local address map 125 E VME address maps 127 F Strap usage 131 G Error register bit specification 134 H Local bus extension specification 136 I Baudrate programming 138
PAGE 2 1 INTRODUCTION
A new computer system, THE KUNix machine, is being developed by the group Digital Systems of the department of electrical engeneering at the Technical University Eindhoven (THE) and the department of computer science of the Catholic University Nijmegen (KUN). THE KUNix machine is, as the name indicates, primarily intended for use with the operating system Unix. The system is built using the 68000 (or 68010) as main processor and the VME bus as communications bus between modules. Hardware and software (Unix implementation) for the first prototype were all designed at the university of Nijmegen. Prototype 0, it was not yet called THE KUNix machine then, consisted of one 68090 processor board, a system support module, a memory board and a parallel interface used to communicate with a PDPll/79 as a virtual disc.
PAGE 3 VME BUS
SYSTEM DISC 68000 SUPPORT MEMORY, MODULE ------SERIAL PORT PARALLEL PORT 1 1 Q
Fig. 1.1 Prototype 8
In order to improve performance of the system a new concept was developed in co-operation with the Technical University. This new concept has lead to a machine consisting of one or more 6S888 systems and a number of intelligent I/O boards. An 6S800 system being a processor with its own memory, accessible through a local bus. However, this memory is also accessible through the VHE bus: it is udual por~ed•• The I/O boards are independent processors with there own on-board memory. They communicate with the 68880 systems and other I/O boards using the VHE bus PAGE 4 ____..,.... VME BUS--..,.....----r----'r 68000 BOARD MEMORY 10 CPU MEMORY MODULE MODULE ~ ~ LOCAL BUS Fig. 1.2 THE KUNix machine When I started work in september 1983, there was not yet a fixed set of specifications for the new machine. Preliminary reports only gave a description of the new machine in general terms. Only the means of communication between the different subsystems in the machine were specified in greater detail. Before I could start the design of an 68000 board for the new machine, I had to make a more detailed set of specifications for it. Of course this was done in close co-operation between the other members of the team both in Eindhoven and in Nijmegen. Parallel to my PAGE 5 design a design was made for the I/O controller boards. The idea for the I/O boards was to maKe a microprocessor system with a VHE bus interface that could be used for all I/O controllers. Each controller consisting of this microprocessor system plus a piece of hardware performing the actual input and output functions (Fig. 1.3). VME VME INTERFACE ~ + + + MEMORY PROCESSOR ('la6) -r- I t I/O ~ Fig. 1.3 An I/O controller in THE KUNix machine The design of a memory board with dual ported memory was completed in october ~83. The board provided not only dual ported access but also error detection and correction facilities. The incorporation of the latter being a strong wish from our group in Eindhoven. This report will give a description of the new 68919 board. It is intended for everybody who has to worK with the new hardware, THE KUNix machine in PAGE 6 general or the 68919 board in particular, and for those who have to write new software for it. Chapter 2 will give a list of specifications of the 68919 board. In particular it will describe the interprocessor communications protocol which is of interest for everybody worKing with THE KUNix machine. The next chapter will set out a more detailed picture of the interior of the 6S919 board. Block diagrams will give a complete view of the on-board logic, the data paths and interrupt structure. Finaly chapter 4 contains some conclusions about the new board and the new machine. PAGE 7 2 SPECIFICATIONS AND GENERAL DESCRIPTION This chapter deals with two Kinds of specification. First the specification of demands and wishes that we have for the 68999 board such as VHE bus compatibility or stand alone operation. The second Kind of specification is the description of what the board actualy looKs liKe, what it can do and how it worKs. Almost all of the specifications of the first Kind and partly those of the second Kind are dealt with in this chapter. Before starting a detailed discussion of the design specifications let's see how the 68999 board will be used. First of all it is intended as a main processor in THE KUNix machine running under the operating system UNIX. And second it must be possible to use the board as a stand alone micro-computer, for instance in a worK station. This leads to the following demands for the 68990 board : VHE bus compatible -A local bus for memory extension. - Use of the 68919 for virtual memory support (68919 board here after) Hardware memory management (demanded by Unix) Timer interrupts (Unix is a timesharing o.s.) - Serial I/O for communication with a console - On board memory with error detection and correction -A networK interface, preferably for ETHERNET. PAGE 8 VME V~E INTERFA9E + ~ MEMORY. 68010 -"- LOCAL I/o -~ EXTENSION BUS Fig 2.1 68818 Board and local bus An important constraint in implementing all the functions of the board is its physical size. Due to the limited board area it was decided not to implement a networ~ interface on the 68818 board. However, provisions were made to allow for a networ~ controller, situated on the extension bus, to access local resources on DHA basis. The above mentioned specifications will be discussed in the next paragraphs. PAGE 9 2.1 VME bus and local extension bus Prototype 0 used the VME bus as data path to memory and peripherals. The new 68010 board has two data paths, one local bus for normal memory access and local I/O and the VME bus for access to other boards in the machine. For exact specifications of the VME bus you are advised to read the VME bus manual [LIT. 1]. The 68010 board can act as a master or as a slave to the VME bus. As a master the processor can access other boards on the VME bus. Acting as slave, on-board memory and other resources of the 68010 board can be accessed. In designing the new board I tried to conform to the VME specifications as much as possible. However on the following two points the new design conflicts with these specifications: - The board is longer (26 cm) then the allowed 16 centimeters. This goes for other boards in THE KUNix machine as well (186 boards). - The load and drive specifications for some of the signal lines (address bus and address modifier lines) are not conformed to. Considering the maximum size of our machine of maybe ten or fifteen boards, this is no real problem. Stronger still, during the design fase there was always the consideration that some of the VME signal-line recievers could be omitted, if necessary, to maV-e room for more important functions. What can the 68010 do on the VME bus? 1) It can generate interrupts on the VME bus at any desired level. The level is software programmable 2) It supports 'release on request' and 'release when done' bus requester options. Requests can be generated at only one level (selectable via jumpers). 3) Any address modifier can be generated but there is no actual support for extended or ascending access. 4) The 68010 board can handle two interrupt levels from the VME bus, one with a hjgh priority and one with a low priority. The levels can independently be selected by DIP switches. It is prohibited to have the 68010 generate an interrupt via the VME bus on a level that is also handled by that same processor. If this happens the interrupt acV-nowledge cycle of the PAGE 10 processor is terminated by the time-out generator on the 68919 board. The next question is: What can other boards on the VME bus do with the 68919 board? Or rather: what can they do with the 68919 subsystem (68919 + memory ex tensi ons)? 1) Using an I/O address modifier a bus master can get access to a semaphore, a waKe up register and a data buffer. These things are used in a communications protocol between intelligent boards in the machine. It will be discussed in detail in paragraph 2.3 2) A standard address modifier can give the bus master access to the on board memory of the 68919. As with the I/O address modifiers no destinction is made between priviliged and non-priviliged access nor is there a destinction between program or data access. 3) One of the user definable address modifiers, called system address modifier (SYSAM) , will give a master device access to almost the entire subsystem: its memory, on-board memory and extension memory, its local I/O and the internal registers of the memory management units. The address mapping for all these address modifiers and the local address map are explained in greater detail in paragraph 2.5. Appendix 0 and appendix E give the address maps of the 68919 board and THE KUNix machine respectively. 2.2 Memory considerations Memory is one of the most frequently used resources in a computer system. Therefore speed and size are the mai n fa.c torsi n memory desi gn. In mu 1 ti-user multi-processor systems relaiblility is another. Before I started worK on the 68919 board, a memory board had already been developed. It used the Intel 8297 as dynamic RAM controller; the design was made for the 8 Mhz versions of both 68999 and 8297. The 8297 allows dual ported access. The memory board has port A connected to the 68919 local bus using synchronous access and port B is used by the VME bus PAGE 11 for memory access. Since VME is asynchronous, port B is programmed for asynchronous operation (Fig 2.2) [LIT 5J. LOCAL ADDRESS VME ADDRESS PORT A PORT B REQUE ST - - REQUE ST A B 1207 + IEIORY PORT PORT LoeAL DATA A B VME DATA Fig 2.2 Dual ported memory. The 8287 can address no more then 2 mega bytes of memory. The memory board is designed for 64K ram chips and 256K ram chips giving a tota.l of 512K bytes and 2M bytes respectively. _ Cooperating with the 8287 is the 8286 error detection and correction unit (EDCU). This device generates 6 checKbits during memory write cycles. These checKbits are written into memory next to the actual data word. Memory width is then 16 data + 6 checK bits is 22 bits. During a read cycle the 8286 recieves all 22 bits and is able to checK data validity. All single bit errors will be corrected, the 8296 puts the corrected data on the data bus. All double bit errors are detected, but can not be PAGE 12 corrected. Figure 2.3 shows the data flow structure of the memory board. LOCAL ADDRESS VME ADDRESS ROW & 8207 ADDRESS COLUMN II ADDRESS ERROR CORRECTION MEMORY DATA & UNIT CHECK BITS OUT BANKS 8206 ------""""i t-_...;C:;;.H;.;;E,;;,CK;.;...B;:.:I:.;,T..=.S "" II II ~--..." MPX -DATA LOCAL DATA VME DATA Fig. 2.3 Memory board, data flow. For more information on the memory board see the design report [LIT 7]. In order to remain compatible with existing hardware and seeing the fact that there were no real alternitives for the 8286/87 the on-board memory of ~he 68818 is configured in almost the same way as the memory boards are. The following changes had to be made: - a bidirectional address buffer between VME address bus and local address bus. This enables the 68818 to access the VME bus and the VME bus can get access to PAGE 13 the local bus of the 68919. data to and from VME, from and to local data bus, could go via the data latches and the MPX data bus. However the 8296/97 use the MPX data bus during error scrubbing and memory refresh. This can not be inhibited so there must be a separation between memory and MPX data bus. In order to save circuits this separation is done by latches and the old data latches are replaced by bidirectional tri-state buffers. (Fig. 2.4) • LOCAL ADDRESS VME ADDRESS ROW 8t 8207 COLUMN ADDRESS II ADDRESS ERROR CORRECTION MEMORY . DATA. & UN IT ...... _CH_E_C_K_B_IT_s ....,OUT BANKS 8206,...... _...;C;.;.H;.;;E..;;,C~K.....:.B;..;IT..;;,S "'" II DATA LOCAL. DATA MPX- DATA Fig. 2.4 68919 on-board memory, data flow. On-board memory size is 128~ byte or 1M byte for 64~ and 256~ r~ chips respectively. Both on-board memory PAGE 14 and the memory boards are designed to allow the 6801~ + MMU combination to access memory with a processor delay of four wait states (excluding refresh or port B access delay times) = two clocK cycles at 8 Mhz. This lengthens the 68010 access cycle (8 states) by 50h which is unavoidable in this system. The 8207 can perform a memory cycle in no less then 5 clocK cycles. The MMU needs more then one half clocK cycle for address translation (measured value). ~ ~ SI U SO 52 CPU CLOCK D:I CPU AS I IIIU liAS e I I az07 CAS q 'I . ..U I /t-OElH -1 ~ mORY CYCLE ~ Memory access cycle timing. With maximum HMU delay the 68010 would have six wait states (= three clocK cycles) for each memory access. Summarizing the specification of the on-board memory the following points hold: - Memory cycle request of 68010 on port A, VME requests on port B of the 8207. Read and write access cycle port A minimal 5 clocK cycles using the 8207 early advanced acKnowledge. - Read with error port A, minimal 8 clocK cycles. - Size 128K bytes (64K ic's) or maximum 1M bytes (256K i c's) • - Error correction of all single bit errors. PAGE 15 - Error detection of all double bit errors. Detection of most errors with more then two erroneous bits. Latching of syndrome and bank-selection signals on memory errors (readable to the 68919 for error 1oggi ng) . 2.3 Inter-processor communication. The 68919 can communicate with VHE modules in three ways. First it can generate an interrupt at any level of the VHE bus by programming the desired level into a register and then writing the interrupt vector to another register. This interrupt vector will be used in response to the corresponding interrupt acknowledge from the VHE bus. Because there are only seven interrupt levels on the VHE bus and because each level is handled by one module, there are only seven modules that can be accessed in this way. Cleary this is to few and to primitive a means of communication in a machine with multiple 68910 sUbsystems, several disc controllers, terminal controllers and other modules. Therefore there is a second way of communication. It uses the VHE I/O page. In the local address map of the 68919, 64K is used to get access to the VHE bus using the VHE I/O address modifiers. If the 68910 does an access to this 64k, the bus requester requests bus mastership. If the 68919 becomes master it releases its local address and an, independently generated, I/O address modifier on the VHE bus. Other modules, on detecting the I/O address modifier code will decode the lower 15 address bits on the bus. Each board in the system has 1k byte reserved for it in the VHE I/O space. In this 1k byte area we find a data buffer called instruction buffer or communication buffer, a semaphore and a wake up register. These are used in our second communications channel. An example will show how it operates. PAGE 16 Suppose the operating system wants to read a sector on a disc. It knows the exact identification of the sector and it knows the addresses of the instruction buffer, semaphore and wake up register of the controller board controlling the disc. Other information that is available is the address where the information from disc is supposed to goto and the operating system knows the system address modifier (SYSAH) of the 68818 subsystem. All this information must be relayed to the disc controller. The controller will read the sector from disc and will put it directly into the subsystems memory. To start the process, the 68810 on which the operating system runs, reads the value of the semaphore. A value of 1 indicates that somebody else is using the instruction buffer of the disc controller board. The 68010 waits for a while and then reads the semaphore again. If it is zero the instruction buffer is free and the 68010 may use it. At the end of the read cycle of the semaphore, the value is automatically set to 1, no read- modify- write cycle is necessary. Having gained access to the instruction buffer the 68010 puts all information, necessary for the disc controller to perform the r~quired function, in the instruction buffer. After the last transfer, the 68010 writes to the wake up register. This write operation will generate an interrupt to the processor on the disc controller board (186). The interrupt handler routine transfers the contents of the buffer to somewhere in the processors local memory reserved for this purpose. PAGE 17 IUU ...... t;.~~ 88010 PROCESS 188 BOARD I p SEMAPHORE LOCAL MEMORY INSTRUCTION INSTRUCTION BUFFER BUFFER ":V:"-_~ l-__ SEMAPHORE I Fig 2.5 Communication using instruction buffer If the contents is saved the handler routine clears the semaphore, indicating to other modules that the buffer is. free for use again. Some time later the instructions of the 68818 to the disc controller are evaluated and processed. Data from disc is written directly to the 68818 subsystems memory at the address mentioned in the instruction. After completion of the transfer the disc controller board will try to gain access to the 68818~s instruction buffer by reading the 68818~s semaphore. On getting access the disc controller will instruct the 68818 that the requested data transfer has been completed. A write to the 68818~s waV-e up register generates an interrupt for this processor. The handler routine of the 68818 saves the contents of the buffer and clears the semaphore. The message is later interpreted by the operating PAGE 18 system. In chapter 3 you will see that the instruction buffer is not a separate blocV- in the system. Instead it is part of the on-board memory. At a fixed address in memory, 896 bytes (1924 - 128) are reserved solely for use as instruction buffer. Since the UNIX operating system has some difficulty in handling fixed reserved data areas in RAM it was decided to maV-e the instruction buffer part of the Unix V-ernel data area. This is the only fixed data area the operating system can handle without a problem. It always starts at address 999999h where the exception vector table of the 68919 resides; immediately followed by the intruction buffer at address 999499h. Any access from the VHE to the 68919's intruction buffer is in reality an access to this part of the 68919's local memory. Note that the waV-e-up routine transfers the data from this part in local memory to some other part, also in local memory, where the operating system V-eeps a queue of instructions still to be processed. A third way for performing data transfers is through the VHE window. Within the local address space of the 68919 (16M byte) 4M bytes are reserved to give the processor access to the VHE bus using a progr~able address modifier. The 4M space is mapped into the 16M VHE address space with the aid of a global segment register (GSR). This two bit register holds the upper two address bits for the VHE bus. An access of the 68919 within the 4M window will initiate a request for bus mastership in the same way as mentioned before. On getting the bus, the lower 21 address bits plus the two bits from the GSR are released on the VHE address bus. At the same time the contents of the address modifier register (AMR) is released on the address modifier lines. Both the AMR and GSR are progr~able. PAGE 19 VME ADDRESS SPACES T 16M WINDOW 4M Fig 2.6 Access to VME bus. GSR and AMR. One of the address modifiers it could hold is the I/O address modifier. Why then still the need for an independent source for this particular modifier. Suppose there is a DHA controller on the local extension bus. A DHA process in progres, transfering data from memory or from an I/O device to somewhere in the VHE space would require use of the GSR and address modifier register. The processor would be unable to access a module on the VME bus because it may not temporarily change the contents of the GSR and AMR PAGE 29 while the DMA process is active. Halting the DMA could mean loss of data because the DHA reqeusts of an I/O device are not serviced in time. This is the mean reason for having two independently generated address modifiers. The 64k window with its I/O address modifier allow the processor to put out messages to other modules. Meanwhile a DMA device can access the VME bus through the 4H window with the address modifier in the AMR. Summarizing the above, the 68919 board supports: - Interrupt request generation at all levels of the VME bus with a fully programmable vector. -A hardware semaphore: 9 = free, 1 = occupied Semaphore can be cleared and set by both 68919 and VME. -A wake up register, a write to its address in VME I/O space will interrupt the 68919, write data is not used and lost. - Instruction buffer 896 bytes (lk - 128). - 4H byte VME access window (standard window) + 64k byte window to VME I/O space. Two bit global segment register and 6 bit address modifier register (fully programmable). 2.4 On-board I/O On the 68919 board only one real I/O device usable by the application programmer is present. It is the 8274 Multi-protocol serial controller (MPSC). The MPSC supports two independent full duplex serial channels, several communications protocols, data rates of maximal IMbaud and modem control signals. This combination is the main reason for the choice of the 8274, there are no 68999 series components offering the same possibilities. A disadvantage of the 8274 is the fact that it does not offer on-chip baud rate generation. The baud rate clocks must be presented externaly. Devices that did offer internal baud rate generation either lacked synchronous operation (WD2131) or two channels (2661) or were just not available at the time (68564). Baud rates are now PAGE 21 generated by the 8254 programmable timer. Data and modem control signals to and from the MPSC are connected to 26 pin connectors via RS232 transmitters/recievers. Appart from this application I/O the 68818 board has some system I/O devices used for a number of system functions liV-e the GSR, AHR and the VHE interrupter. They are an error register, one word of error status information, and an 68239 parallel interface/timer (PI/T). Their operation will be discussed in chapter 3. 2.5 Address mapping There are two different address maps to be considered. First the local address map of the 68919 and second the address map of the VHE with its different address modifiers. I will discuss the address maps in global terms in the following two subsections, detailed maps can be found in appendices D and E. 2.5.1 Local address map The 68919 issues 23 address bits (logical address), two data strobes (accessing 16M bytes) and three function code bits on each bus cycle. Function code bits specify the cycle type: user/supervisor and program/data access or a CPU space cycle [LIT 2]. The MMU uses the function codes for address translation and the interrupt decoding logic uses them to determine whether an interrupt acV-nowledge cycle is in progress or not. Address bits 1 to 7 are not translated by the MMU, the upper sixteen bits are modified according to the information in the MMU~s segment descriptors. The translated upper address part and the not translated lower address part are then combined to form the physical address. This address is used in the local address decoder unit of the 68019 PAGE 22 boa.....d; so eve.... y add.... ess f .... om the p .... ocessor is t .... anslated by the MMU befo.... e it is used in add.... ess decod i ng (F i g. 2. 7) • Al A7 ADDRESS - DECODER - ilia I a - LAS PAS - - I-- LOGICAL liMO PHYSICAL LA23 PA23 Fig. 2.7 Add.... ess t .... anslation and decoding. How is the 16M of the 68919's local add.... ess space used? The Unix ope.... ating system would liKe to have RAM at add.... ess location 999889h, it uses the lowest pa.... t of add.... ess space as Ke .... nel data and Ke .... nel p .... og.... am a .... ea. The.... efo.... e the fi .... st 11M bytes a .... e .... ese.... ved fo.... RAM; 256K byte 0 .... 1M byte is on-boa.... d RAM, the .... est is .... ese.... ved fo.... extension RAM via the extension bus connecto..... It was mentioned ea.... lie.... that the VHE bus is accessible th .... ough a 4H byte window in local add.... ess space. The highest 4H bytes in the local map constitute this window. This leaves 1M byte between the top of RAM and the sta.... t of the window. The fi .... st th .... ee qua.... te.... s of this space a .... e not used, the last qua.... te.... is in use fo .... local I/O, VHE I/O page window and ROM. PAGE 23 o 11 12 16 M lr---r--I-----H t LOCAL EXTENSION LOCAL VME RAM RAM I/O WINDOW Fig. 2.8 Local address map A network controller (82586) residing on the local extension bus requires start up information in the upper part of address space. A first idea would be to use the upper 1M, with ROM at the top, as I/O space. The network controller would then always find its setup information in ROM. The VME window would have to range from B99999h to EFFFFFh. On an access to the VME bus through this window, address bits A21-A91 will be released on the VME bus, VME address bits 23 and 22 come from the global segment register. Suppose the GSR holds 99, where would an access to local address B99999h lead us? Due to the strange starting address of the VME window they would lead us to VME address 399999h. In order to get to VME address 999999h we would have to do a local access to address C99999h. This is clearly not what we want, the 4M window has to start at a 4M border in the local address space or we have to change the address before releasing it onto the VME bus. The latter will cost extra hardware and address translation time. Making the choice for the address map shown in figure 2.6 leaves it to the network controller board to put out the right addresses during initialisation. 2.5.2 VME address map Address maps of the VME bus depend on the address modlfier issued for the bus cycle. THE KUNix machine uses the following modifiers: - I/O access, no destinction between privileged and non-privileged. 1k Byte is reserved for each master board in the VME I/O space. PAGE 24 - Standard access, no destinction between privileged and non-privileged nor between program and data access. 1M Byte is reserved for each 68919 board and 1/2H is reserved for every 186 board in the standard VHE address space. - Subsystem access using one of the sixteen user definable address modifiers PAGE 25 1/0 ADDqESS MODIFIER 32 48 64K II------Ir --.- .. I,.!., Ii Ii II ...... rl~----I 012m 11~1 3 56 1 SUBSYSTEM NUMBERS STANDARD MODIFIER r-o---.r--.--2-1:-1-4""T'"------r-14--r1-1-5~lrM SUBSYSTEM NUMBERS 68010 SYSTEM ADDRESS MODIFIER .r 1H_2 ~yM D-R AM (PO RT B) MMU. EMPTY ROM &SERIAL I/O Fig. 2.9 VME address maps 2.6 Miscellaneous functions In order to remain independent of the VME bus for stand alone operation we need a clock circuit. The clock circuit on the 68919 board generates 16, 8 and 4 Mhz clock signals. They are all needed on board. The 8 Mhz clock is used by the processor. It is also inverted and then used by the 8297 and connected to the extension bus. Also for the sake of stand alone operation the 68010 has its own power on reset generator and reset switch. A special BOOT switch selects one of two start up vectors in ROM. It also determines whether or not memory is initialized to all zero during reset. ATTENTION: During power-up memory must be initialized to all zero in order to prevent errors during memory reads from non initialized locations. The boot switch must be in the BOOTO position during power up. This second function of the BOOT switch was added for PAGE 26 test purposes at a time then the design was almost completed. It does not do exactly what is wanted and should be chanced if a re-design of the board is made. In order to maKe it worK properly, two switches are neseccary, a BOOT switch selecting the boot vecor and a ·SOFT RESET- switch, to reset the system without erasing memory. The 68919 may be halted with the RUN/HALT switch. In the halt state the STEP switch allows one cycle to be run. This provides the 68919 with a single step feature. Sometimes it is possible, due to wrong addressing, system failure or heavy traffic over the VHE bus, that an access cycle of the processor is not terminated by a transfer acKnowledge within a specific amount of time. The system will hang if the cycle is not terminated at all. Therefore it is necessary to have another way of terminating the cycle. The bus error signal provides the escape route. To ensure that all cycles will terminate within certain time, the 68919 board has a watch dog timer monitoring the local bus. If a cycle is not terminated in time the timer generates a bus error signal in order to terminate it. The time-out circuit is only one of several bus error sources. These are: the HMU signaling a page fault, the VHE bus during access to this bus, the address decoder detecting an illegal address, the time-out generator. In order to provide the software handling the bus errors with a means of quicKly determining the source of the error a bus error latch is present on the 68919 board. After a bus error the processor can read this latch and determine the nature of the error. Next to these bus error sources we have the correctable and non-correctable memory errors which are signaled to the processor by an interrupt. When these errors occur the syndrome and banK selection (in this case the CAS lines) of the memory are latched. This allows the operating system to calculate which memory circuit is faulty and by logging all errors indicate which circuits are eligible for replacement. The bus error latch and syndrome latch have been combined to one word of error status information. PAGE 27 3 IMPLEMENTATION AND BLOCK DIAGRAMS In this chapter I will describe the newly designed 68919 board with the aid of blocV. diagrams. Figure 3.1 gives you an overall view of the new board. ~ t<1 /l / - 1/ Ij '--- E 1 t LOCAL VME ADDRESS \ ADDRESS / MULTIPLEXERR ADDRESS DECODER DECODER ~ I INTtRRUPT V ~ ~ M ~ LOGIC N LOCAL I/O E B CPU a MMU .. o-RAM VME B U FUNCTIONS U 5 ROM 5 LOCAL l FUNCTIONS DPIO r t1! J roo-- I I ~ V1 ~ "- " - ~-- --Fi> Fig. 3.1 BlocV. diagram of the 68919 board. In the next sections and sub-sections I will go over the diagram one blocV. after the other, starting wi th the 68919 itself and finishing with the blocV. 'VME PAGE 28 functions'. 3.1 CPU. and memory management. Figure 3.2 gives you a more detailed view of the immediate surroundings of the 68919. FUNCTION CODE -:::: IRO'S IAcn LEHI INTERRUPT L RESET, LOGIC RESlT HALT I HAlT Al SINGLE Il ADDRESS STEP LATCH H A7 LOCAL ...... ADDRESS BUS 68010 AI / ftU FUMr.TIRI r.nRF MMU BUS REQUEST DAISY cufit t LOCAL DATA BUS 1)~!mL 1 - " cmmz Fig. 3.2 CPU, MHU's and interrupt logic PAGE 29 3.1.1 Central processing unit: 68010 It should be clear by now that the cpu of the new main processor board in THE KUNix machine is not an 68000 but an 68010. The 68010 offers some extra facilities to the operating system in particular concerning virtual memory. To support virtual memory the 68010 needs no extra hardware. This in contrast to the 68000 where virtual memory support could only be given by using a second 68000 processor for processing bus errors. The 68010 itself can give full virtual memory support. On a bus error it suspends instruction execution and pushes the contents of its internal registers on the system stacV-. After restoring the error condition, for instance by loading a new page of data or program into memory and changing the MHU decriptors in the proper way, the suspended instruction is resumed. NB. it is not restarted. Care should be taV-en in determining which instruction caused the error. Information on the stacV- reports the address causing the fault and the program counter among other things. The 68010 has a two word prefetch queue, this means that the program counter may not point to the address immediately following the address of the instruction now being executed. It also means that the address causing the error need not be related to the instruction currently being executed. Consider for example a return instruction at the highest address of the last page for that program. After the instruction fetch, the instruction is loaded into the prefetch queue. Just before or when the return instruction is transferred to the instruction decoder, the prefecth mechanism will try to fetch the next instruction. Since this instruction would be in the next page the MHU is not able to translate the address and generates a bus error. The software handling the page faults is unable to load a new page of instructions because there is none. So it is important to taV-e such events into account when writing the virtual memory support software. In the new board it is still possible to replace the 68010 by the cheaper 68000. Virtual memory is then PAGE 30 no longer supported. For more detailed information on the 68010 see [LIT. 23. 3.1.2 Memory management mechanism. The UNIX operating system, like many other multi user operating systems, requires a hardware memory management mechanism. Such a mechanism can ensure memory protection and it allows paging or segmentation for virtual memory support. In order to implement the mechanism the 68010 board is equiped with two 68451 Memory Management Units (HMU's). Each HHU can contain the description of 32 different segments, each segment being a contingeous piece of memory. The length of a segment in bytes is a power of 2, with a minimum of 256 bytes (256, 512, 1k, 2k ••• 16M). The two HHU's operate in parallel, a memory management mechanism could be made with just one HHU using only 32 segments; two HMU's provide a total of 64 segments. A detailed description of how the HHU's work can be found in [LIT. 3J. I will now describe its operation in less detai 1. The HHU's main task is to translate the address issued by the processor (logical address) to an address used for memory access (physical address). To do this the HHU has segment descriptors (internal registers of the HHU). A segment descriptor consists of a logical base address register, a physical base address register a segment length register and some other information about the segment (e.g. write protection). Since the minimum length of the segment is 256 bytes, the lower 7 address bits (A1-A7) are never changed during translation, the HHU does not need them. The 68010 issues 23 address bits and 3 function code bits at the start of every cycle. Function codes indicate the cycle type [LIT. 2J. They are used to select a subset of segment descriptors to be used in the translation process. The upper 16 logical address bits are inputs to the HHU. The HHU compares the incoming address to the logical base addresses and segment lengths in all descriptors. A PAGE 31 match is found if the logical address is within the range described by one of the desciptors. The HHU outputs the sum of the physical base address of that descriptor and the offset of the 68818's logical address within the segment (fig. 3.3). LOGICAl PHYSICAL ADDRESS ADDRESS MMU PHYSICAL BASE } OFfSET ~--t~EMORY ACCESS LOGICAL ",' Off SET 68010 ACCESS--'"4~ I~"~ - Fig. 3.3 MHU address translation mechanism. The HHU does not expand the address, it merely translates the upper 16 address bits of the logical address to upper 16 bits of the physical address. This physical address, together with the not translated lower part (7 bit) of the logical address, is latched in the address latch. The output of the address latch, the local address, is used in the local address decoder for selection of resources. The address latch is necessary in order to free the address outputs of the MHU after translation. After the address is latched, the address outputs of the MHU may be used as data in- or outputs. This way the MHU registers can be read from or written to. A bidirectional buffer in the HHU's data path is necessary to prevent short circuiting the address output bus and local data bus during address translation. The second buffer serves PAGE 32 as a protection for the CPU's data bus output drivers. Why the lower three data bits go through the interrupt logic block will be made clear in the next subsection. 3.1.3 Interrupt logic. Before going into greater detail of the implementation, the philosophy behind the interrupt mechanism must be explained. Seven interrupt levels are directly supported by the 68919. Six of them can be used in our system, level 1 having lowest priority is reserved for use in the software. Six levels for external use is to few, there are 11 or 12 sources of interrupts on the board. Creating daisy chains on one or more levels expands the number of interrupts that can be handled. What are the interrupt sources? - The VHE bus has seven interrupt lines; we want to be able to handle two of them. One line must have high pr i or i t Y , the 0 t her.one a 1ow pr i or i t yin the 689 19' s interrupt hierarchy. This way the 68919 can service ~xternal devices with different urgency of requests. -A timer interrupt having high priority in order to allow the operating system to update its time dependent administration (e.g. accounting). - The wake up register interrupt also with a high priority. This is needed to ensure that the instruction buffer is saved and ready to recieve new instructions as soon as possible. Other boards may be actively waiting for the 68919's instruction buffer. - The parallel interface is used to generate interrupts to the VHE bus. When the interrupt has been acknowledged the PI/T (68239) will generate an interrupt to the 68919 in order to inform it of the fact that the resource 'interrupter' is available again. This message is of low priority. - Another source of interrupts is the serial controller (8274 HPSC). Because the acknowledge cycle needed for this Intel chip differs strongly from the 68919's lACK-cycle the 8274 is programmed in autovector mode. The interrupt request pin of the HPSC is connected to a handshake pin of the PI/T (68239). PAGE 33 The 68239 then takes care of the interrupt request and acknowledge cycle toward the processor. -A manual interrupt is required so the operator may terminate error situations that may occur, without reseting the system. This break switch interrupt must be non-maskeble. - The memory management unit can request processor attention if a descriptor in which the interrupt bit is set is matched in normal translation. This feature is probably seldom used and needs no high priority. - One of the timers of the baud rate generator (8254) is not used. In future it might be used as the operating systems watch dog. It generates an interrupt if the operating system fails to restart the watch dog timer before its count is exhausted. This interrupt should be non-maskable or of very high priority. - The last interrupt source is the error detection and correction unit (EDCU). Due to timing problems it is not possible to use the error strobe (ESTB) of the 8297 to generate a bus error to the 68919. Memory errors are therefore signaled to the processor by interrupts, one interrupt for non-correctable memory errors (fatal error), and another interrupt for correctable memory errors. A bus error must come within one clock cycle after data transfer acknowledge (DTACK). The 8297 generates the DTACK very early in the cycle, at a time when the memory has not yet presented its data to the EDCU. The error strobe is asserted at a time when the 68919 has already terminated its current bus cycle (appendix C). There are two solutions to this problem. 1) Delay the DTACK signal until data is sure to be valid (or not). A bus error is generated if a memory fault occurred, the processor will not use corrupted data if the fault was not correctable by the EDCU (fatal error). This solution will slow down the processor by at least one clock period per memory access. The decrease in system throughput is unacceptable considering the fact that fatal memory errors PAGE 34 will be very rare. Correctable errors present no problem, the processor will always read the correct data, the bus error is then used for error logging. Although the second solution is less elegant, system performance does not suffer from it. 2) A fatal memory error results in a non-masKable interrupt. The CPU will read corrupted data and use it. The current instruction is executed till the end or aborted because of the invalid data read from memory. Assuming the prefetch queue was empty an intruction operation code may be corrupted. This can result in an illegal instruction, software traps (trap instruction), reset (reset instruction), jump instruction (destroys the old program counter), a legal intruction corrupting data somewhere in memory or registers or a legal instruction with no data in memory corrupted. All these errors can occur simultaneously with the non-masKeble interrupt. Some of them (address error, bus error) have higher priority then the interrupt, this means that the stacK is updated for these errors first. Before continueing with the first instruction of the error service routine however, interrupt exception processing starts. On leaving the interrupt service routine, the processor continues with the first instruction of the error service routine. These service routines must be able to recognize that the initial error was a memory fault which lead to an error (or errors) and to an interrupt. The hardware bus error register provides some support in recognizing this situation (see section 3.2.15. The operating system, on finding a fatal memory error, reports the error condition to the operator. Non-fatal errors are reported to the operating system by an interrupt of low priority, error logging can be performed. The following tabel shows how the interrupts are PAGE 35 distributed over the 68919 J s seven request levels. Level 4 and level 2 are extended to three requests each by a daisy chain mechanism. The PI/T has two interrupts, one for the timer at level 6, the other for the parallel interface at level 3. This last interrupt combines the requests from three handshaKe pins of the PI that can generate interrupts. Multiple requests on one level are listed from high to low priority; Keep in mind that the priority within the PI is fully programmable. LEVEL INTERRUPT SOURCE 7 Fatal memory errors; BreaK swi tch 6 Timer (68239) 5 ~aKe up register 4 VHE (high priori ty) ; Extention connector; reserved (daisy chain) ; 3 Serial controll er (8274); Interrupter; Reserved; (all three trough the 68239) 2 MHU; VHE (low priority); Non fatal memory error; 1 reserved for use in the software One of the reserved levels can be used to implement the operating systems watch dog. However the watch dogJs priority might then be to low. The VHE interrupt at level 4 is the high priority interrupt. It is selected from the seven VHE levels by DIP switches. And so is the VHE interrupt with low priority at level 2. Of course it is not allowed to select the same VHE request level for both high and low priority. It is possible to use only one or neither of the two interrupt lines. Figure 3.4 shows the interrupt request structure. PAGE 36 SELECT1 ¥ME IRO 1-7 BREAl 7 8 EnElT. eLI 5 WAlE UP 68010 PRIORITY TIMER REDUEST 4 LEVEl ENCODER 3 68230 2 EoeD IOHATAL ¥ME 'RO 1-7 SELECT 0 Fig. 3.4 Interrupt request structure. To indicate an interrupt ac~nowledge cycle the 68919 performs a read cycle using function code '111' and address lines 4-23 in the high (1) state. Addres lines 1 to 3 indicate the level currently being ac~nowledged [LIT. 2]. The interrupt ac~nowledge logic decodes the function code and address lines and generates six interrupt ac~nowledge signals, one for each level (level 1 is not used). Because the wa~e up register, the brea~ switch and the memory errors are not supported by an interrupt vector, the autovector feature of the 68019 is used. The autovector signal from the decoding logic is always activated when level 7 or level 6 is being ac~nowledged. It will also be PAGE 37 activated when one of the autovector request inputs is asserted (Fig. 3.5) AV. RE U STS LAS 7 NM lACK FCO-3 • TIMER LA1' 5 WAKE· UP LA2' DECODER .- LA3' 3 PI LA4 Z BREAKPOINT ~------AUTOVECTOR Fig. 3.5 Interrupt acKnowledge logic. The autovector request lines can be connected to an interrupt acKnowledge output of a daisy chain. In that case, the device for which the acKnowledge was intended need not provide an interrupt vector. On the 68919 board the correctable memory error interrupt acKnowledge is handled in this way. The interrupt acKnowledge of a VME interrupt presents an extra problem. Suppose the 68919 board handles VME level 1 as a high priority interrupt. The interrupter, somewhere on the VME bus, waits for an 'interrupt acKnowledge for level 1. The 68919 receives the request from the VME bus at level 4 and it does an interrupt acKnowledge for level 4. At this level the daisy chain then asserts the interrupt acKnowledge signal corresponding to the VME request. It informs other logic on the 68919 board that an interrupt acKnowledge cycle to the VME bus must be performed. The correct level (1) must now be put on the VME address bus. To do this, the same DIP switches are PAGE 38 used that select the VHE interrupt level to be handled as high priority request by the 68919. This is done by the ~level shifter~. It is a three input multiplexer for the lower three address lines. Normaly it puts out the lower three address bits from the 68919. During interrupt acknowledge of one of the two VHE levels it puts the state of the DIP switches, corresponding with the level being acknowledged, on the address lines. SELECT 0 LA1 LA1" LA2' LA2 LA3' SELECT 1 VMEIACKO VMEIACK 1 Fig. 3.6 Level shifter for VME interrupts 3.1.4 Bus request arbitration. On two occasions the 68919 must relinquish control of the local bus: 1) If a DHA device on the extension bus wants to use it or 2) if someone on the VHE bus wants to gain access to 68919~s local resources. This is achieved by performing a bus request and waiting for the bus grant from the 68919. There is only one bus grant from the 68919 so an external arbitration mechanism must be provided to arbitrate between the two bus request sources. The bus request arbitration is a daisy chain mechanism. A request from the PAGE 39 extension bus has higher priority then a request from the VHE bus. BR 68010 BUS UilTER B8 8R D SRI BD 0 881 VM E EXTENS I ON Fig. 3.7 Bus request arbitration N.B. This bus request must not be confused with the bus requests of the VHE bus and its arbitration, they are quite different. 3.1.5 Halt and reset control This functional blocK allows the 68010 to be reset, halted and single cycled. The 68010 is reset for 2 seconds after power up, after VHE's SYSRESET or after a manual reset. These 2 seconds are necessary in order to give the 8207/06 enough time to initialize the memory banKs to all zero. The 68010 is halted by a manual switch. One bus cycle is performed if the processor is in the halt state and the step switch is pressed once. PAGE 40 SURESET RESET ~ r----AS HALT & t----HALT RESET STEP f---RESET CONTROL ~_~207RESET .....__IOOTO RUII/HALT Fig. 3.8 Halt. reset and single cycle Memory is reset and initialized to all zero if the 68919 is reset and the BOOT switch is in the BOOT9 state. MaV-e sure this is the case during power up. The BOOT switch thus serves a double function: 1) selection of the boot vector. 2) selection of the memory reset mode. When memory reset mode is on, boot vector 9 is selected (BOOT9 state). Memory reset mode is off and boot vector 1 is selected when the switch is in the BOOT 1 state. This double function is an undesirable situation, caused by the fact that the memory reset function was added in a late stage of the design process. At that time it was impossible to add an independent reset mode-selection circuit. 3.2 Local I/O and ROM Loca 1 I/O i nthi s bloc V- i s not on 1y rea1 input/output (8274 serial contoller), it also stands for devices used to support local functions. These local functions are ports (byte or word) that can be read from or written to. They supply status information (error register), timing information (68239 timer and 8254 timers) and VHE support (PI with PAGE 41 GSR, AMR and interrupter module) • 3.2.1 Error register This two byte register records the state of all incomming bus error signals at the time a bus error or interrupt from the EDCU (8296) occurs. This is done in the lower of the two bytes, the upper byte of the register latches the syndrome and CAS signals at the time of a memory error in the on-board memory banV-s. The software handling the bus errors can find the address in error on the system stacV-. The bus error source is read from the lower byte of the error register: - Time out, there was no response from the addressed device within a certain time. - NO Periphiral (NOP) , on the specified address no device is present. This condition is detected by the local address decoder for part of the address range that is not used. Unused addresses not decoded by the local address decoder will give rise to a time out error. - VHE bus error, the addressed device on the VHE bus generated the bus error or was not present (t ime ou t of VHE bus cycle). A VHE bus error may also occur if the 68919 try's to get access to its own resources through the VHE bus. - MHU fault, page fault detected by the MMU. The memory management was not capable of translating the processors logical address. The other signal lines that are latched at the time of an error are the fatal and non-fatal memory error interrupt 1ines, the Master Has Bus (MHB) line - indicating that the 68919 is VHE bus master - and the bus grant acV-nowledge (BGACK) line - differentiates between 68919 and DMA cycles. It was mentioned in section 3.2.3 that fatal memory errors may induce several other errors, including a bus error, maV-ing it difficult for the software to recover properly from 'normal' errors. The error register can be of help in this. As long as the interrupt request caused by the memory error (fatal or PAGE 42 not) is asserted, the lower byte of the error register remains unchanged. New errors caused by the memory fault will not change its contents but since bus and address errors have higher priority the 68919 enters error exception processing. Before starting the actual error service routine however, interrupts are serviced. If the fatal memory error occured in a user process the user process is terminated and reports are sent to the operator. When the system continues processing after this error it will encounter the bus error or other errors caused by the memory failure. Therefore all error service routines should look at the error register. If the error register indicates that a memory error was the last error to occur, the service routine may terminate. A 'legitimate' address error after this, will leave the error register in the fatal memory error state and the service routine will assume wrongly that the error was caused by a memory fault. This problem oly ocurrs for address errors because other errors set the error register to the correct state. The problem can be solved by setting the error register to a defined state at the end of all error handling routines. The high order byte of the error register is only meaningful 1 during memory error processing, it latches the syndrome and CAS signals during memory errors. ERROR STATUS 000 007 008 015 Fig. 3.9 Error register PAGE 43 From this byte it is possible to determine the circuit causing the correctable error or the bank in which the non-correctable error occured. Logging of correctable errors can inform maintenance personel about the state of each memory circuit. Circuits causing a lot of faults must be replaced. 3.2.2 Identity register Each 68010 subsystem in THE KUNix machine has its own subsystem number (SN), see section 2.5.2. In order to allow the software running on each of the subsystems to determine its own subsystem number an lOR (identity register) is provided. The subsystem number can be read from the lower four bits of this register. 3.2.3 Parallel interface The parallel interface/timer 68230 [LIT. 4] performs 5 different functions for the 68910 board. The timer function is discussed in the next subsection. Port A of the parallel interface is the combined global segment and address modifier register. An external buffer drives the VME address modifier lines and address line 23 and 22 if the 68e10 accesses the VME bus through the VME window in the local address map. The port A register of the PI/T must contain the correct address modifier and upper address bits. The register may be read and written by the 68010. Port B and three bits of port C take care of the interrupts to the VME bus. The three bits of port C encode the level on which the interrupt must be generated. When the 68010 writes the interrupt vector to port B, handshake pin H4 initiates the actual interrupt request at the selected level. During the interrupt acknowledge, some time later, the vector is read. The end of the read cycle is signaled to the parallel interface by a rising edge on handshake pin PAGE 44 H3. The PI then interrupts the 68919 to inform it of the fact that the vector has been read and that the interrupter module is ready to be used again. The next function of the PI is combining several interrupts to one interrupt request for the 68919. Handsha~e pins HI and H2 can be used as interrupt request inputs from devices that do not have interrupt vector generation. Together with the interrupt from H3 the 68239 generates one interrupt to the 68919 and provides a different interrupt vector for each of the handsha~e pins [LIT 4]. Piority of the handsha~e pin interrupts is programmable. HI is used for the interrupts from the serial controller. The 8274 is an Intel device and its interrupt ac~nowledge cylce does not conform to the 68919's. It is programmed in auto-vector mode and the 68239 now performs the interrupt request and provides the vector for the 68919. The last function of the 68239 is the control of the channel attention (CA) signal to the networ~ controller (82586) that may be present on the extension bus. The CA line can be set and reset by the 68919, it is an output bit of the port C register. PAGE 45 ADOR. II OOIF. P S ---, I A T - ~A%3 - AU ADORES S K1 me IRD I-- T"" CA PARALLEL 0 I C INTERFACE T INlERRUPTER I--VilE LEVEL Slml~ """"ii I-- 14 TA r I 8 VECTOR T , I .,1 :DATA Fig. 3. 18 Parall eli n t erf ace 3.2.4 Timers The 68818 board has its own clock generaters in order to be able to operate outside a VHE bus system. A 16 MHz crystal oscillator provides a TTL compatible square wave clock. This clock is used in various clocked state machines. From this clock an 8 Mhz clock signal and its inverse are obtained through a D-flipflip. The 8 MHz clock is used for most of the VLSI devices on the board. Only the serial controller (8274) has a 4 MHz clock obtained by dividing the cpu~s clock by two again. A second oscillator on the board (4.9152 MHz) provides the base frequency from which the baudrates for the serial channels are PAGE 46 derived. Two of the three timers in the 8254 have this frequency as input clocK. By programming the right division factors into its internal registers the entire range of baudrates may be optained at its outputs (appendix I). The third timer of the 8254 is not used yet, in future it might be used as watch dog timer for the operating system. The 68238 provides the last timer of the 68818 board. It is the time Keeping clocK of the operating system. This timer is programmed to generate interrupts at regular intervals so the system may Keep tracK of time and perform the necessary administrative tasKs that have to do with time. The timing interval length is programmable [LIT 4], the 68238's internal clock (8 MHz) is used as input for the timer. 11230 TIl IRD 1-__ BAd ORA TE A 1---- BAUORAH B Fig 3.11 Timers 3.2.5 Serial I/O Intels Multi-Protocol Serial Controller, MPSC (8274>, is the 68818 boards direct link to the outside world. The 8274 has two independent channels and as the name says supports several protocols (SDLC, HDLC, IBM bisync) , synchronous and asynchronous communication. RS232 receivers and transmitters link the 8274 to two 26 pin connectors, one for each channel. PAGE 47 RU32 CS --...; ADDRESS r------l CHUNEl A BAUD RATE A----I BAUDRATE B 'IPse ,...---""1 CHmEl B DATA---+ Fig. 3.12 Serial interface The baudrate clocks for the MPSC are provided by the 8254 timers. The clear to send signal can be jummpered to be directly taken from the request to send signal, or it can be taken from the Modems clear to send signal, depending on the capabilities of the receiving device. 3.2.6 Read only memory In the address map, the ROM space is situated in the upper part of the local I/O space, that means that ROM always ends at address BFFFFFh. The starting address of the ROM space depends on the size of the ROM's that are used (appendix 0). After a reset, the 68010 must read the initial system stackpointer and initial program counter before it can start program execution. These 4 words of start-up information must reside in ROM. The 68010 expects this information at address 000000h-000003h. Since there is no ROM at these addresses a trick must be used to read the information from the ROM. System reset will assert a SETUP signal which remains asserted until the end if the fourth read cycle of the 6S010. The address decoder uses this signal to select ROM instead of RAM PAGE 48 during these memory cycles. The address on the local address bus is not changed by the SETUP signal. However, the BOOT switch may chance address bit A03 during setup. BOOT0 will leave A93 unchanged 3.3 Local address decoder Inputs to the local address decoder are the entire local address, the memory address strobe,the data strobes, the setup signal and the RAH- and ROM-size lines. LiKe many other ~wild logic~ functions on the 68010 board, the address decoder is implemented in PAL~s. It is a two stage decoder, the first stage decodes the larger sections in the address space: PAGE 49 on-board RAM, Local I/O, ROM, VHE I/O window and VHE standard window. The second stage further decodes the local I/O space and the ROM space. The address decoder also generates the NOP bus error signal for some parts of the address range where no device is selected. NB. there are still parts where no device is selected and the NOP signal is not activeted, in particular some parts of the local I/O space and the space reserved for RAM extensions. ADDRESS I--r--SETUP STUEI PEA 10SEL ROMSEL SlUE! 10 CS'S CSROM Fig. 3.13 Local address decoder The first stage also generates the port enable signal (PEA) for the 8287 port A requests. This must be done in the first stage in order to minimize the delay from address valid to PEA asserted. It ensures minimum memory access time. 3.4 Local functions Local functions are a number of small uni ts performing a small but not un impor tan t task in the PAGE 58 ,system. They' are the halt and reset mechan i sm (subsection 3.1.5), time-out generator, control signal generation, DTACK generation and size selection of RAM and ROM. The time out bus error funtion is a so called one-shot device. The output of this device changes state a certain time after it was triggered. The 68818's time-out is triggered upon assertion of one of the data strobes. If no transfer acKnowledge (DTACK), negation of the data strobes or halt occurs before time-out, a bus error is generated. ! I + , IOTACK V(C) !TIMe-ouT I______ Fig. 3.14 Time-out timing No time-out is generated during DHA cycles or when the 68818 is in the halt state. A strobes unit uses the address and data strobes, the read/write signal and write Inhibit signal from the 68818 and MHU to generate the control signals for the local bus. The memory address strobe is asserted when the MHU asserts its MAS output and negated as soon as the 68818 negates its AS output. Data stobes are asserted after the MHU asserted its MAS output. If the MHU asserts its write inhibit output during a write cycle the data strobes are not asserted. The cycle will then be terminated by the MHU generating a bus error. Address and data strobes are put in the high impedance state during DHA cycles. From the local bus data strobes and the read/write signal the unit PAGE 51 generates the read and write strobes for the Intel devices on the board (8297, 8254 and 8274) . For devices that do not generate there own DTACK signal, an external transfer acknowledge must be generated. This unit asserts DTACK 599 nsec after one of the data strobes was asserted and one of the above mentioned devices was selected. The devices are: ROM, 8274, 8254, error register and ID register. 3.5 Dual ported memory The main purpose of dual ported memory is to allow two masters (68919 and VME bus), a more or less simultaneous access to the memory data. Each master has its own address and data busses and there is no need for one master to interfere with the other during memory cycles. The latter is the case for DHA; the processor has to release its control over the bus in order to enable a DHA device to gain access. The memory circuits themselves have only one address bus, a data input bus and a data output bus. Their address bus is small and the address has to be multiplexed into a row and colomn address by the RAM controller. The RAM controller also does the refresh of dynamic RAM chips. Figure 2.2 already showed that the dual ported RAM has 2 data and address busses. Since the RAM chips can only handle one address at a time a choice has to be made as to which address will be presented to the RAM for the next memory cycle. If data is to be read or written to the RAM it has to come from the correct data bus and must come at the correct time. At no time data may be presented to the RAM by both busses simultaneously. The 8297 Advanced Dynamic Ram Controller (ADRC) supports dual ported access. It arbitrates between the two address busses and provides signals that may be used for controlling the buffers in the data paths. An external multiplexer receives the two address busses and selects one of them. That is presented to the 8297. The controller takes this address and multiplexes it into a row and a colomn address that PAGE 52 goes to the memory chips (Fig. 2.4). LOCAL ADDRESS VM E ADDRESS ROW 81 8207 ADDRESS COLUMN II ADDRESS ERROR CORRECTION MEMORY DATA,& UN IT ______CHECK BITS ..;;..._..;....---lDUT 8ANKS 8208 I-_..:C:::.H:.:E.:::.CK:;.....B~I:..:.T.::.S .... II LOCAL_DATA MPX- DATA Fig. 2.4 68919 on-board memory, data flow The external multiplexer is controlled by the Mux/PCLK signal from the 8297. On order to start a memory cycle the 8297 must be informed that a port wants the memory and it needs to know the nature of the cycle (read or write). To do this each port has a Port Enable (PEA, PEB) request signal, a read and a write signal. If PEA is asserted and RDA or WRA is asserted, port A has a request pending; port B is similar (PEB and ROB or WRB). At the end of the current cycle (refresh or port B cycle) the 8297 will set the MUX signal so as to get the address from port A. It latches the address into the memory chips (RAS and CAS). In parallel the 8297 PAGE 53 will set its Port SELect output (PSEL) to port A and indicate to the external logic that this signal is valid by asserting PSEN (Port Select ENable). The PSEL and PSEN signals are used by a control unit that will enable the data buffers for a port A read cycle. During a read cycle the direction of the buffer is set from the memory to the 68919 prior to activating the buffer. As long as the buffer is enabled the direction will not change. After some delay (159 nsec from RAS asserted) the memory presents its data to the error correction unit (8296). Correct data will appear 67 nsec later at the data outputs of the 8296. The transparant latch (read latch) was enabled at the same time as the data buffer and so data goes through the latch, through the local data buffer to the 68919. Data arrives at the processors inputs just before it accepts the data from the bus. The data transfer acKnowledge to the 68919 was issued long before valid data was present, 68919 and memory run synchronously, this minimizes memory cycle time. The transparant latch does not latch data for 68919 read cycles. During VHE read cycles data is latched just b~fore the 8297 negates the RAS and CAS signals. Data remains latched until the data transfer acKnowledge (DTACK) to the VHE bus is negated by the 8297. For a write cycle the 8297 also starts by latching the row and colomn address into the memory chips. It selects the correct port with the PSEL signal and asserts PSEN. The buffer control mechanism may then enable the local or VHE bus buffers in order to get the data to the write latch (transparant). ~rite data is latched in the transparant latch immediately (125 nsec) after the data was presented to its inputs. It remains latched until data has been clocKed into memory. Before the output of the write latch can be enabled, the data outputs of the EDCU must be put in tri-state. The 8297 taKes care of this by asserting the disable byte marK (DBM) signal. The control unit will then negate the byte marK signals before opening the write latch output buffers. ChecK bits are generated by the 8296 and presented to the RAM inputs together with the actual data word. The 8297 then asserts the write enable signal to the memory chips. The control unit for the data buffers and latches PAGE 54 consists of a state machine and some combinational logic processing the signals coming from the 8207 and the address decoders for the VME bus and the local bus. Its outputs control the direction of the buffers, the strobes for the latches and all output enable signals. 16MHZ ClK STATE ~ MACHINE BUFFER ADDiESS CONTROL DECODER & 8207 OUTPUTS SIGNALS LOGIC Fig. 3.15 Data buffer control logic The mechanism is implemented using a field programmable sequencer (FPLS) and two PAL's. A 16 MHz clock frequency is needed for th~ sequencer. It has 15 inputs, 8 output state variables, 2 internal state variables and 18 different states. The sequencer is used for generating the enable signals for the buffers and the read latch and for generating the write latches strobe signal. Outputs of the DPIO block are also controlled by the sequencer, they will be discussed later. The state diagram of the sequencer is quite simple. From a starting state the machine can go to another state depending on the input signals at the time of the rising clock edge. All states, state transitions and all logic functions in the PAL's are listed in appendix B (for a more detailed description PAGE 55 see LIT. 8]). Errors that may occur during a memory read cycle must be reported to the 68818. The EDCU produces two output error signals: ERROR and CE, indicating that the RAM data is in error and the error is correctable (or not). Because the 8286 is completely asychronous and is always checking the incomming data the error signals will usualy be asserted. Only the 8287 knows when the signals are valid, this depends among other things on the RAM speed and master only or master/slave EDCU configuration. If the 8287 detects an error, it will inform the external world of this fact by asserting its error strobe (ESTB). This strobe will set one of two d-type flip-flops who~s outputs are the interrupt request lines for fatal and non-fatal memory errors to the 68818. The FF~s are reset by the corresponding interrupt acknowledge signals. 3.6 Dual port I/O and interrupt vector register Closely related to the memory is the dual ported I/O, the instruction buffer, semaphore and wake-up register. Although not actualy considered dual port I/O, the interrupt vector register is situated on the same spot and controlled in a similar manner as the semaphore; therefore it is also discussed here. As mentioned in chapter 2 the instruction buffer is part of the local memory of the 68~18, it starts at address 888488h and is 896 bytes long. A VNE module will access it by putting an I/O address modifier and a 15 bit address on the bus. The VME address decoder module uses the address modifier and address bits 18-15 to detect an access from the VME bus to the instruction buffer and for card selection. This initiates a request for memory access at the 8287. The local memory needs 19 bits for an address. Only the lower 9 are provided by the VME bus as an off-set in the instruction buffer. The buffers base address must be provided in some other way. The 68818 board uses the address multiplexer to do this. The base address PAGE 56 (999499h) has bit 19 set to high and bits 11-19 set to low. By disabling the multiplexers of address bits 11-19 (disabled meaning output set to low) only address bit 19 remains to be set; bits 1-9 are multiplexed as usual. The multiplex and set function for address bit 19 is implemented in a PAL function (appendix B). So an access to the instruction buffer is realy a memory access and as such it is taken care of by the 8296/8297. The wake-up register is not realy a register, it is only an address in the VHE I/O space that can be written to. Write data is not accepted by the 68919 board but the write cycle does set a local flipflop. The output of this flip-flop is an interrupt request line at level 5 of the 68919. In order to save extra hardware for generating a data transfer acknowledge to the VHE bus (to terminate the bus cycle) the 8297 is used to take care of this. The 8297 receives a request for a write cycle from port B. It does not know that it is not a normal memory write cycle. This is known to the buffer control unit however. This unit will not open any buffer during the write cycle to the wake up register. In order to prevent strange data from actualy being written into memory the write enable signal from the 8297 to the RAM chips is suppressed by external logic. The 8297 performs a normal write cycle and thus takes care of generating the VHE's DTACK signal. Second in the DPI/O block is a binary semaphore. P and V operations can be performed on the semaphore by the 68919 and by the VHE bus. A write operation to the semaphore's location will do the V operation. Write data is not used. A read operation at the same location will put the current value of the semaphore (high=occupied, low=free) on bit 9 of the data bus; the other bits are undefined. After the read operation the semaphore value is always high, occupied. This function is implemented as a synchonous state machine in a PAL (appendix B). The semaphore output has a tri~state buffer which is controlled by the buffer control unit. The 8297 arbitrates between ports for access to the semaphore. It is therefore not possible for a P and V operation to occur simultaneously. The third and last item in the dual port I/O block PAGE 57 is not realy a dual port I/O function. It is however situated and controlled similar to the semaphore. The interrupt vector register of the interrupter module is the 68239's port B register. This register must be programmed as double buffered ouput register [LIT. 4]. Its output data lines are therefore always active. The vector must be released onto the VME bus during the interrupt ac~nowledge cycle corresponding to the interrupt request generated by the interrupter module. This interrupt ac~nowledge is detected by the interrupter module itself. Again the 8297 will be used to save hardware for generating the DTACK signal. Upon recognition of the interrupt ac~nowledge, the interrupter module will request a read cycle for port B of the 8297. The 8297 arbitrates and after some time, port B is selected for memory access. The buffer control unit will then enable the VME data bus buffers and a tri-state buffer seperating the 68239 port B output from the multiplexed data bus. The interrupt vector thus goes to the VME bus. DTACK is then generated by the 8297 in order to terminate the cycle. A handsha~e pin, driven by the output enable signal of the interrupt vector register, will inform the 68239 that the vector has been read. PAGE 58 WEI lACK ,i WAlE WH IRD "J-", I· V VECTOR I DU TPU T , OU TPU T SEMAPHORE COmOL CONTRO L MPX-DATA Fig. 3.16 Dual port I/O and interrupt vector. The interrupt vector is released to the VME bus via the VME data buffer. Reason for this is the wish to mlmlnize the 68010 boards load on the VME bus. An output buffer directly on the VME data bus would increase the capacitive load on the bus. I tried to stick to the VME specifications where possible so the interrupt vectors output buffer had to be place on the HPX data bus. 3.7 VME address decoder Three address modifier types are recognized by the VME address decoder. 1) Standard address modifiers (priviledged / non-priviliged, program / data). If the upper four VME address bits are equal to the 6881e~s subsystem number, a memory access cycle is performed. Only the on-board memory may be accessed in this way. This PAGE 59 feature is primarily intended for use by VHE boards that do not support user defined address modifiers. 2) User defined address modifier. There are sixteen different user defined address modifiers (9-15). Each subsystem (68919+memory boards) has a subsystem number (SN) ranging from 9-15. If the user address modifier equals the SUbsystem number the VHE address operates in almost the same way as the address on the SUbsystems local bus would. The address map for this address modifier almost equals the address map of the subsystem itself. Only the VME I/O page window, the normal VME standard window and the dual port I/O can not be addressed. The first is obvious, you can not do an access from the VHE bus through the 68919 board to the VME bus. Dual port I/O is excluded because it is controlled by the 8297. An access to DPI/O would be done using the local bus on DHA basis. Since the 8297 uses synchronous timing on the local bus, but the VME bus is asynchronous, the timing does not match. It can not be matched because the 8297 is programmed to operate in synchronous or asynchronous mode only after reset. 3) I/O address modifier (priviledged / non-privi 1edged) • The address space for I/O address modifiers is only 64V- byte. THE KUNix machine uses the middle 32V- byte of this space for inter-processor communication. Each board has lV- byte reserved in this area. Starting at address 4999h the first lV- is for the subsystem with number 9, the second lV- for subsystem 1 and so on. The 68919 and the 186 boards have there instruction buffer from 999h to 37Fh within there reserved space. The waV-e-up register at address 389, must be written in order to generate an interrupt. The address of the semaphore is 382h. ATT8NTION: for the saV-e of clarification the addresses of the waV-e-up register and semaphore must have data strobe 9 (DS9) of the VME bus asserted. The VME specification does not specify whether this is the odd or even byte. Here it is taV-en to be the even byte, the 68919 however has its lower data strobe (LDS) for the odd byte. It is recommended only to use words in the entire interprocessor communication, this guards PAGE 69 against differences in the way bytes are arranged within a word by different processors in the system. 3.8 VME functions This section will discuss the VME data transfer bus requester, the VME bus master and VME interrupter modules on the 68919 board. 3.8.1 Bus requester module In order to get control over the VME bus, the 68919 board must first make a request and wait until the arbiter grants the bus to the board. The internal logic of the board asserts a Master Wants Bus signal (HWB) indicating to the bus requester that it must start a request cycle. If the arbiter has granted the bus to the 68919 board, the requester module asserts Master Granted Bus. These are the only two signals from the bus requester that are used internaly. The other in- and outputs are VME bus signals. Straps are used to select the level on which the requester will issue its request and waits for its bus grant of the VME bus (appendix F). The requester has two modes of operation, the release when done (RWD) and release on request (ROR) mode. In RWD mode the requester will negate its outgoing bus busy (BBSY) immediately after negation of the HWB signal. This means that the requester must start an entire new bus request cycle each time the HWB signal is asserted. The ROR mode will hold the BBSY signal asserted until the requester detects a request for the VME bus from some other master in the system. Then it will release BBSY so that the bus arbiter may grant the bus to this other module. If however nobody else wants the bus, the requester will not release it. If the requester's HWB signal is asserted the MGB signal may be asserted immediately because the requester still has the bus. There is no need for re-arbitration. The ROR mode is PAGE 61 faster in granting the bus to the master that last used it, the RWD mode is faster in granting the bus to the first that requests it. Fig. 3.17 Bus requester The bus requester is implemented as a synchronous state machine. It has the following states: IDLE, no activity whatsoever. PASSIVE, slave station in the bus grant daisy chain. ACTIVE, having bus mastership. HOLD, holding the bus but not using it (ROR mode onl y) The complete description of the state machine can be found in appendix B. All attempts to design an asynchronous bus requester (in a single progr~able device) have failed due to timing problems. An asynchronous bus requester has to deal wi th two~ input signals that may change simultaneously (MWB and ANYREQ or BGxIN). This maKes it almost impossible to design a completely asynchronous bus requester, using ROR mode, without introducing critical races or hazards. PAGE 62 3.8.2 Bus master module Arbitration of the VME bus may be done while a master or a slave is still driving the bus (BBSY released while the bus ~ycle is in progress). The requester has no knowledge of this. This is something the bus master module takes care of. ~t also takes care of the address and data strobe timing in relation to the address and data themselves. The master has bus (HHB) signal indicates that the master has been granted bus mastership (through the requester) and that the previously active VME master and slave have both relinquished control of the bus (VME address strobe and DTACK negated). The HHB signal is used to activate the address and data buffers. Data buffers will be enabled last because they are controlled by a synchronous state machine. Therefore the enable signal of the VME data buffer is used to activate the address and data strobes after some delay specified by the VME bus manual [LIT 1]. Delay is created by gating the signal through a number of PAL ports. INa lsa OTAel '. V 'IE IUS AS M us USB LOS MUTER - OS! E UOS mlEDa Fig. 3.18 Bus master PAGE 63 3.8.3 Interrupter module Interrupts to the VHE bus are generated using the 68239. It was mentiond already that 3 bits of port C are used to indicate the level on which the interrupt must be generated and that port B holds the interrupt vector. The port B handshake pin H4 initiates the actual interrupt request. The interrupt is acknowledged by a correct level on the address bus, lACK and IACKIN asserted on the VHE bus. The acknowledge will request a read cycle at the 8297 in order to claim the HPX-data bus and in· order to have the 8297 generate the DTACK signal. The interrupt vector is then released on the VHE bus. 1I l2 IRD D-7 l3 V START REDUEST ""'-"'::';"'--IM IITERRUPTER ,...... _ ... E READ VECTOR Fig. 3.19 Interrupter The logic functions of the interrupter are all implemented in PAL's (appendix S, LIT. 8). The lACK signal on the VHE bus is used to momentarily freeze the status of the interrupt request. If, after some time the IACKIN signal is asserted, there can be no problem of what to do: assert IACKOUT or accept the acknowledge localy. A request can never be asserted simultaniously with IACKIN asserted. The interrupter can thus be made asynchronous, in contrast to the bus PAGE 64 requester where there was no fore warning liV-e the lACK signal of a coming event. PAGE 65 4 CONCLUS IONS Af',ID RECOMHENDAT IONS With the design desribed in this report there is a prototype of a new processor board for THE KUNix machine. It supports: - 68080 and 68018 MPU's (SMhz version) - Hardware memory management - 1M byte on-board memory (dual ported) with error detection and correction + 10M off-board memory using a local bus extension. - 5 Different ROM sizes (4V--64V- words) 2 Serial channels, synchronous and asynchronous - Programmable timer interrupts - NetworV- controller as extension module - KUNix machine I/O page configuration for interprocessor communication (instruction buffer, semaphore and waV-e-up register) - 2 VME interrupt handlers VME interrupter module - ROR and RWD bus requester options - Stand alone operation However, the design is not yet tested. Although the principles of the design are believed to be correct, implementation details must be tested extensively before it can be said to be a reliably worV-ing system. Implementation of the logic functions in programmable logic (PAL's and FPLS) maV-e changes in the system easier. Test results may show that it might be possible to speed up the system to 10 or 12.5 Mhz. The main problem to overcome is the state machine controlling the data buffers. It is implemented in an FPLS device which has a limited clocV- rate. Delay's that may occur in other signals (MAS, RD, WR and DTACK) due to bUffering or logic operations, may also become a limiting factor for speed increase. PAGE 66 Compared to PAL's the design of the buffer control logic was much easier, it is also much easier to understand. PAL functions are often hard to see through especialy in a complex environment like we have here. Bottle-neck in system throughput is the memory. The 8297/96 are realy not suited for use in an 68999 system. They slow down the processor with 25%. Maximum processor speed can probably only be reached by using a cache memory [LIT 8]. In that case dual ported memory can not be supported. It might be interresting to have a closer look at the performance/cost picture for such a memory in an 68888 system. Two last conclusions on the new design: 1) The design is probably to expensive for stand alone applications even though part of the hardware could be left out then. There are cheaper modules for use in a stand-alone situation. 2) The existing design of the memory extension board has to be altered so that it can support the 68818 subsystem (68818 + memory). In particular the address decoding of the memory board will cause problems there. When the prototype has shown that the n~J design is correct, a final design must be made. For this final design it might be possible to incorporate more 68888-series devices like the LANCE (Ethernet controller) or the SIO (68564). These devices are not available at the moment. On some points it is possible to reduce the cost of the system: Use 8-bit comperators in stead of 9-bit. - Replace two 74LS74 by one 74LS376. - Optimize PAL functions and there distribution over the PAL's. - Use TTL logic for some functions now implemented in PAL's. - Combining the baudrate generators and the serial interface controller. There is a lot of activity at the moment in the development of systems like THE KUNix machine: 68888 + VME bus + intelligent I/O controllers. During my work I unfortunately have not seen much of this other activity. In my view a comparison, between THE KUNix PAGE 67 machine and other systems now on the marV-et or in development, must be made. It can only be of interrest for future developments to V-now what you are up against. At the moment the machine may be a JmarV-et leader J , but students worV- slow so, by the time the project leads to a sellable machine, it might be to late. THE KUNix machine incorporates the most sophisticated devices currently on the marKet, that can already be an advantage, lets Keep it this way. PAGE 68 5 LITRATURE [LIT 1] SIGNETICS, VMEbus Manufacturers Group; 'VMEbus Specification Manual Rev B' Aug. 1982 [LIT 2] MOTOROLA Semiconductors; 'MC68010, 16-bit virtual memory microprocessor' Dec. 1982 [LIT 3] MOTOROLA Semiconductors; 'Memory management unit' 1981 [LIT 4] MOTOROLA Semiconductors; 'Microprocessors data manual 1982' Dec. 1981 [LIT 5] INTEL; '8207 Advanced dynamic ram controller' Ju l. 1983 [LIT 6] INTEL; '8206 Error detection and correction unit' Mar. 1982 [LIT 7] Brinkman, R.M.; 'Een geavanceerde geheugen geheugenkaart voor de UNIX-machine' (Dutch) Nov. 1983 PAGE 69 [LIT 8] Heuvel, W.C.J van den; ~6S010 Board programmable logic function~ Sep. 1984 [LIT 9] Ei bner, J.A.; ~Simple cache steos up performance of 16-bit systems~ Electronic design, 22 Dec. 1983 PAGE 70 APPENDIX A SCHEMATIC DRAWINGS PAGE 71 " ~= -======~======. - ~ ,11 ii I I, II ~ ! ;! II 1 , 1[_1 ' I' I- ~"', ! i ,t-- I. :1 6 ..I U :t:t~ ~ l):t l):t Ol IIZ!.i' " UI~UU QOCOQCOOCQQ .. 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B' BOlll8 ""ALS2"tS.... LDCDIIl5 I O~ LOC00. 01 RI..OCOB I\B OIRVMEOIl ~ '-ENLOCOB EN '2~S .-ENVI1EOIl LOCOlll6 0' 03 LOC003 m5 IC63 me LOr-Dill., 3 02 • LDC002 ~ LOCOlll7 All B8 B8 01 • LOCOIll. Bil BII.6 08 1'2~::~ :g:~ 0" 00 .. LOC000 B" BA HI LOCOlll6 1\1 87 B1 '2 06 RA/ .3 LRO 86 LOCOIllS 07 A6 116 I MPXOIllS B6 I BOIllS 07 CLK .0 CLI( BS ,~ :~:~ LOCOIll. 1116 liS B5 " MPXOIll~ 85 I~ BOIll. 0S PC7 .... TJ ....Cf( 37 '-Tlnll\CK B. '5 1111 ,'2 LOCOlll3 illS A' II. 5 MPXOlll3 Bt 15 Boe3 09 .6 ., LOCOS2 'U A3 83 16 MPXOlll2 B3 '6 8Oe2 PC6'-PIACI( 36 .-PI II\CI( 83 811 .7 10 3S .-PURQ '7 BII'IIl LOCOlll1 03 A2 82 17 MPX081 B'2 8OS1 PCS'-PIRQ 8'2 02 ,. pc,,'onl\RE 31 .... CA B. 18 BAIIl8 LOCOIllS 0'2 Al B' 18 MPXOIllIll B. 'S BOlll0 .... S27.,INT 13 PC3-TOUT 33 .... TJnJRQ ~ PC2-TTN 32 .... VnE12 -11.1-52 ..:5- -11.1-62":5"- · 31 .... VMEl' .... ENTJREG PC. .... 413I1TIilQl/nE '"\6 PC0 313 .... vnET0 17 RS' 2911.111 18 28 A02 RS2 11 8A8e BIISB 19 RS3 27 "83 20 I BII87 BIIIIl7 RS~ 26 All" 13 BIIIIl6 2\ 2~ 11.8:5 BA86 RS" 1" SASI:5 811.11:5 OTACK .... OTACK BIIS~ BASI., CS .... SELPTT · .. RESET BASI:l SIIIIl3 .-nR BAII2 BASl2 BASl BABl .... WEK1ACK .... WEKIRQ .... ENJOAM .... nHB vnEOTIICKOUT ~ 0 ~~6 .-BOTIICK • 211' MPXOlll7 .-OSIOUT 15 21\3 0 Y' .-BOS' 7 MPXOSS Y3 .-BOSS '2112 MPXOIllS '-OSIIlOUT Y2 BI\nS .... ASOUT .... 8A5 ~ .\ 21\' MPXOIll. vneBERROUT Yt Blln~ LRO .-BVRITE ~~6 BBERR .1\. ~ MPXOlll3 06 'Y~ BIIM3 '-SOS' 5' '"3 MPXOlll2 .-BOS0 .... OSS #S3S' • .112 MPXOIll. IY3 Blln2 .1\. MPXOIllIll H2 Blln. ....8A5 /vneAS ,v. SIInlll .-BVRI TE vnEREIIO .... SGACK0 .... nHS .-vnEIIICKOUT .... SJACK VCC '-8LVORO ~ 81 81 88 I1B1XIIII IWl£SET.!L l£SET AIlt J5 ~1SIA8 vet tlI:l 13 6 86 RA 86 RA _I BSI]!. ~Sl , 31 21£ ~1fl1A1 11K 1lMD18 5' 1fl1l1.. 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J.-..: 18 12 19rfIClIU'1 lIE I9I1EIQlL 'I PALZI PAL21 9 ..~ II 71lS313 l1LS313 I 1(11 1'16 PIS "6tt' '28L8' 5 ~. 16 /RWDOPTlON 3 11 VCC 02 15 13 IYL00 IRQ2 05 ~ 11 IYL01 12 19 01 13 IVL02 11 /VMEI0 1211 01 18 1215 12 JVLlf21 10 /VMEll 02 17 ~~.11 IVL 11 09 /VMEI2 03 16 1217 10 IVL12 08 /LIRQ 01 08 139 15 GND l1P PSEL 05 V22 V23 /68SELOPIO 1216 1'! OILS /VMESELOP IO 1217 13/FORBIO ECCR/'t/ 08 12 8207WE 09 11 VCC PAL20 26 /BBREQ0 0 /VMEBREQX /BBREQI i 1 P17 22 /BBREQ2 0 "'16L8" 20 /BBREQ3 0 18 0 BBUSYOUT~ 16 /BBG00UT 0 /VMEBGXOUT 38 08 /BBBSY 14 139 leG /BBG0IN 0 IRQ7 12 /BBG10UT 0 10 BREQXOUT~ /BBGI IN 0 1218 38 11 /VMEBREQX /BBG20UT 0 12 ICG 06 /BBG2IN 0 (31 /BBG30UT 0 02 /BBG3IN 0 /VMEBGXIN FrC26 /VMEIACKIN 01 19 /BGACK STR2 /DSYIACKIN 02 18 /BGACKI /VMEAS 03 17 /VMEDTACKIN 01 16/LOCDPIO VMEA01 1211 lA 1A 12 /SYSRESET 05 15 /READ INTVEC /VMEJf21 02 lB 4B 13 LEQUA 06 11/0SYIACKOUT LEQUA 1213 1Y 'tY 11 /23f21IRQVME 07 13 /LIRQ VMEA02 01 2A 3A 1219 VMEA03 /XACK 08 12 /VMEI I 05 2B 3B 10 /VMEJ2 /BGACK0 1219 11 /68SELDPIO LEQUA 1216 2'1' 3'1' 1218 LEQUA PAL2f21 71136 JCS9 P18 "'16L8'" VME INTERRUPT LOGIC T TH:: 19 19 tHl 'VMEAS .01 19/10CAceESS IMIIB III 19 /DS00UT IENloeDB O1 /BRll ClK0 III 18 AM5 112 18 ISTACCESS I'H3 112 18/DS1OUT IENVMEDB 02 18 IBGACKll tBBREDll 112 AMi O3 17 VMESElHI GH IENVMEOB 113 17 /ASOUT MHB 03 17 STBBERREG IBBREDI 113 17 BREaXOUT AM3 O'1 16 16tKRAM lRD llt 16 lRO O'1 160lRVMEOB IBBRED2 llt 16 BBUSYOUT IS AMI 05 15 VMEA18 /MAS 05 IS VMEREAD 0S 15 D1RlOCOB IBBRED3 llS ll6 1'1 AMll It VMEAI9 /lOS 06 IlAS 06 1'1 IVMEBERRIN IVMEB6XIN llS 1'1 IVMEB6XOUT /SYSAM O7 13 VMEA20 IUOS 117 13 /ENIOAn IBERR 07 13 IlOCACCESS IMIIB 117 13/RVOOPTION VI1EA23 08 12 IIOAM /SELVMEST 118 12 /ENSTAM IEDeUFATIRD 08 12 IBERRVME ISYSRESET 118 12 IVMEDT ACK IN 11 Vt1EA22 O9 11 VMEA21 /SELVMEIO 119 II /EDCUCOR IRD 09 11 IBGll IVMEAS 119 PAl20 PAL211 PAl20 PAl211 PI9 P21 P23 Pill N N16lBN N16l8" N16l8" NIGRt lll elKll 2B vee ll2 ISElRAM 27 vee ll3 ISElSEM 26 PSEN ISElliEK llt 2S PSEL llS IVSEMRED 2'1 LOCDA TASTB IIOACCESS 01 19 IRE!J1Et'OIIR III 19 IIVREMl llS 23 IVI1EOmSTB IBIRD7 III 19 IVLl2 07 18 1ST ACCESS 02 1BIVMESElDPIO PSEL 02 18 MHB 22 VI1:READ IBIRD6 112 1VLlI 17 /REAOINTVEC 03 17 ISElINSTRBlf PSEN 03 tLOCACCESS 118 21 IMAS IBIRDS 03 17 IVLl0 09 IXACK 0'1 16 IVI1ESElRAM IlOS llt 16 /EI'flEMOlIlH IBGACK0 211 LRD IBIRDt 0'1 16 IVI1EIRDI 1050 OS IS IVMESELIlEK IOS0 llS 1'5 /EN'1EMOlill IENloeDB III 19 RESET IBIRD3 05 15 IVMEIRDIl VMEAll9 06 1'I /VMESElSEM IUDS 116 1'1 18111 IENVMEDB 11 IBSTBMEI10lll IBIRD2 116 1'1 vee VMEAllB 07 13 IVMEVSEM /OSI 117 13/BM0 IENIVREG 12 17 IREQMEI10lfR IB1RDl 117 13 lYL02 VtlEAll'l 08 12 IPEB /READ1NTVEC 118 12 /lVREAD IENSEMREG 13 16 IENMEMORl vee 118 12 lYL01 VtlEAll2 O9 11 VMEA01 IDBM 119 11 vce 1 IS /VSEn vee 119 11 IVl00 PAl211 PAL20 PAL211 28P P21 P20 P22 Pll6 N16lBN "16l8" N82S111S" N16l2" 7 vec),0'\ 02 /SHORTRESET '\ ~7u RES TRrti 01 16 07 DeHG n+ 555 vce 02 280K 15 1 IC90 0 ,JU RESET 01 03 i 1'\ ~ THLD OUT 03 I .c02 /RESET I~E ev IC /RE5ET 01 I 02 03 1 ~0'\ 0'\ 1 E 13 I IC IC "---::' 105 ~ ~ l~uF /MA5 05 12 I 05 1 06 DELRESET /STEP~ $ n+ IC 3K3 HLT~ $/VMEIACKOUT VCC 06 11 "'BOOTl~ /RESET~ JE-/8207RESET R Ll!L POR5T~ ~/5HORTRE5ET /SYSRESET~ ~ 08 09 DELRESET ~ ~ V25 ... VME I ~CKOUT 0~ R HALT Vl6PB /VMEI~CKOUTI ~ ~/800T0 05_ ~ R PAL20 279 01 3U IC87 '-----' 16 vec P8 07 /5WRE5ET 15 vee 0 0G_ 51 QH 02 4 A02 "16L8" A 1M RES TRrti 03 1'\ R DCHG 555 3.JQ /RE5 0'\ 0 1U vee 01 16 R i1 13 IC88 02 15 RES 279 05 In.-" 12 06 ~POR5T /RUN lC87 '----' THLD OUT 03 1'1 r CV 0'1 13 RUN 15 r 06 11 51 QH ~HLT 05 05 12 /5T 0.'17 07 ~ 06 11 ST "l- 07 10 BK 08 0 i ,IU 09 bR' -..1.. ----l, 08 O9 /BK 279 IC87 V27 16P 03r 52 V16PB V24 ~ 51 QH ~/5TEP 10 R '" 279 12 IC87 r 52 ~ 51 QH ~BREAKREQ /8207RESET ~8207RESET ~ET,BREAK ~ STEP InNT: Wv/n HFllVFI I T :K: FHA 'HI NF 1?5r;\SA4 [ArC: IPRINT: [MOn;1 19068'1 [2 120784 13 I E078~ 14 1Al'l7fl,\ IS 1(,; IPN: IRAr.K ;" IRR; TH-ElflJOHOVFN AFn; F llRI IEP: FR I hR0~- " 8 rEI10IlI 15 AI IfnA8 15 MI If:M0 IS 18 rEI10IlI Ii 1.8 Il!Wl Ii AI IfnA8 lIS 1.8 IfnA8 15 !8 If:nA8 IS AI IEllAI 81 I rEnAl 1'1 I 1f:l\A. 81 I 1f:I1.I 1 8'I I 1f:I1.I1 8'I 1 IEllAI 87 I rEnAl 1'1 I rEnAl 81 I IlG If:nA2 116 2 1'EllA2 116 2 rEnA2 iii 2 If:llA, 2 rEnAl 116 2 If:nA2 116 2 1'EllA2 116 2 rEnA2 iii 2 IEI1Al 12 3 IEI1Al 12 3 rEnAl 11 3 !(rIA, R ) rEnA) 12 l rEM:! 11 3 rEnA) 12 3 IEllAl 12 3 I'EllAI II 12/SCllllS IfnAI II rEnAl \I 1 DIN 12 1lf'O}81 If:M' .!I 1 011 Itl nEroJ. rEnAl II 1 DIN 12 1lf'0181 IEllAI II I IfnAI II 1 01. 12 rErIlll3 IfnAI II 1 DIN 12/SClIII I DIN 1 IIl\\S II llIIA5 II Il:I1AS II 5 riMS 18 S IlMS 1& S IlMS II 5 IEllAS II 5 IlMS II 5 5 5 lJ IBMIi 13 raw; 13 1fnA6 13 & If:MC 13 C raw; 13 , IfI1Ij; Il C IE/W; I) C IEIlA6 C & 6 llIIAl IS /lIIAl 19 1 r(MI ~, If:I1.II IS 1 IfnAl IS 1 1'EllA1 IS 1 rEnAl 13 1 1EllA1 89 1 1 11 l1 IfIWl II II llIIA8 81 1fnA8 II 8 lWT 111flOl87 riMY II 8 lWT l!I1ff'OO88 rt:nI.. 01 8 lWT lil1BOl01 IfnA8 II 8 IWI llIIAB 81 I lWT llIIA8 II 8 lWT 1E1Ol81 8 IWI Il11l18S 8 IWI JR.ISI11 IUSlI 11 tllAS8 81 tRASi 11 RAS llA~8 01 S JR.\SI 81 RAS JR.\S8 B1 RAS JR.\S8 B1 RAS RAS .QSI 15 ICA5I 15 .QSI 15 ICA5I 15 CAS lUSI IS (AS !C1.S8 IS CAS !CASI 15 AS ICASB 15 CAS CAS Il IJ Il Il IJ 'if 8J WI: 1lW( IJW( IE IE Im825li tflS8lS& tml25& Im825li Im825li nl nz nJ ns I1Il IfIIA8 15 AI 1I'J1A8 IS AI rEI10IlI lIS AI IfnA8 15 AI IfnA8 15 AI IfIIA8 15 .... If:nA8 t5 AI llIIA8 IS AI llIIAl 81 1 If!IAI 8'1 I If:MI 81 I llIIAl il 1 llIIAl 8'1 1 llIIAl 87 I rEnAl 81 I llIIAl 8'1 I 1& 1EllA2 IG 2 r6IAl ec 2 rEnAl 116 2 If:nA2 116 2 1EllA2 116 2 rEnA2 IG 2 If:nA2 1& 2 lEIIA2 Z lEIIAl 12 3 1EllA3 12 1f:IL\3 12 IfMJ 12 3 1f:I1.I) 12 3 lEIIAl 12 ) lEIIA3 12 3 rEnA3 12 3 3 3 12 lEIIAI 11 82 1EllA1 II 82 rff'OHS rfM' II I DIM II rfJllII. fEIlAl II I DIN 12/SClI89 1EllA1 11 1 DIN \18 IfnAl 11 I 1EllA1 11 I 1EllA1 II I DIN 82/SCl113 1 01. 111 1 DIN rEn.\5 18 5 1EllA5 18 IEllAS 18 5 rfl1.\S II 5 rEnAS 18 5 rEn.\5 II 5 rEn.\5 18 5 IlMS 18 5 5 IEIlA6 13 IEIlA6 13 riMe 13 6 raw; I) , IfI1Ij; I) 6 IBMIi 13 & IEIlA6 13 G IBMIi Il & 6 & 1EllA7 89 If!IAl 19 1 rfllAl .!1. I IEllAJ ll!l 1 1EllA1 ll!l 1 llIIAl 89 1 rEnAl 19 1 llIIAl 89 1 1 81 11 rErIlOl1 1f:IL\8 II 11 rff'OOI5 1(11.\8 81 8 IWI .!!11OOl88 1f:I1.I8 8' 8 IDIl 11 llIIA8 81 8 IWI It rErIlOll llIIA8 I' 8 IDIl II llIIA8 II 8 IDIl 12 IfIWl II 8 IDlT It rErIlOI3 llIIA8 8 IDIl 8 IDIl IUSlI 81 IiASI 81 tllAS8 11 1lAs0 81 lIAS JR.\S8 81 RAS 1iAS8 II JR.\S8 11 JR.\S8 11 RAS RAS RAS .QSI 15 /CASt 15 ICAst IS iCASI IS I(IS8 .!.5 rl~ !CASI IS rAS !CAst 15 !CASe IS AS CAS AS CAS Il Il 8J 83 WE IJ liE 8, iE 8J VE WE IJIf WE ffl582SG Iftimi Im825li Im825li Im825li 1fIS82S& "' n\1 nl2 nl3 ftl5 nl6 1'{r1A1 85 ,Ii rEI10IlI 115 AI lIIWI as A8 IfIWl IS AI IfIIA8 15 AI 1f:nA8t5 8'1 IfnAI 87 r61A. I rt:nI.l WI lfrlAl 87 I'EllAI 87 I llIIAl 1'1 1 I'OtAI 116 2 1f:I1.I2 l!6 . llIIA2 l!6 1fnA2 116 2 1EN2 116 2 If:nA2I16 IEIIAJ 12 1ff1AJ12 rfM' R 3 rt:nI.3 12 Iff1AJ 12 lEN] 12 3 3 82 I2 82 1fnA' II 1 011 82 ceoe 1f:I1.I1 II DIN 12 tOOl JiMI 11 DIN 82 CS02 llIIAI 11 I 01. C1lO3 1f:IL\1 \I I DIN Cl101 rEnAl 11 DIN C80S I'(I1.\S .!! 5 rt:nI.S \8 rEn.\5 18 llIIAS 18 5 rt:nI.S 18 5 IIl\\S II IEIlA6 I) flnA[ 13 C raw; 13 raw; I) IEIIA& .!! c rew; 13 C 1'(11.\1 19 '1 1fnA7 89 I IfnAl 89 llIIA7 89 1 rt:nI.l 19 1 IfnAl 89 IEIWl II 11 CSt5 101A9 II I lWT .!!CS18 1f:I1.I1 II 8 lWT J!.CS\l 1QA881 IDIl It CSl2 llIIAB 81 8 IDIl " CSIl rEnAB II B IDIl 11 CSll 8 IDlT .1lA'B .81 RAS illASI 81 RAS IQAst 81 S JR.\st 81 JR.\S811 RAS JR.IS881 RAS 5 'CA~I 15 (AS >CAst 15 CAS !CAse 15 CAS tCAS8 IS .QSI 1 CAS !CAse 15 AS 1l1W(; 8J we 8J 13 we 8J ~~~ 1fI58256 Im825li )fISI2S6 nil niB "19 n21 TH - IN HOVEN :r~- =';'"="':=~C_:==--'------iiI " ,--- llS rENe 85 IEIIA8 lIS All IfIIMl 15 AI rf'L\8 e::'...:,18 rlM8 IIi 'AI rENe IlM lIS All IlM 85 !I AI B1 If:IIAI 81 I IlII.II 11 I 8'1 ' ICIAI ~ I If:IIAI 11 I If:IIAI 11 1 rt:'tll~11 If:IIAI ll6 1f:IIAlll6 1f:IIAlll6 1f:IIA2 16 2 1EllA2 16 2 1f:IIA2 16 2 IfIL,II ,-:1 I rfJlAI I(. '--II 2 2 IEIIA2 12 fl IEhU 12 ) ) 1(1\\) 12 ) If:IIAJ .!1. ) If:IIAJ If:IIAJ !f'lAJ' :1.; J I 1f.IIIJ J{ 3 1f:IIAJ.!l J .!1. ) \I It It 12 \I 1(1\\1 It 82 reollS If:IIAI II 82 Dl~ 12 reoJI1 ~ rErl.\l . OI~ 82 reo182 If:IIAI I OIN In IfMI I I DI~ I OIN 116 IlII.II I 1:"'" 1 OI~ nPll!1ll "'i' I rinA~ ~ I(MS II 1f:IIA5 18 5 rfmll 5 1f:IIA5 II 5 1EllA5.l!- 5 .!!j r ....rrJlA~ iii'j "('". 5 1f:IIA5 " 5 I) !D I) I) If:IIAGU If:IIAElJ If:IIAG 13 If:MI; G !fMC i.Lj G IfIl.\G IJ E rfIIoI6 G If:MI; G G G G ~: If:IIAl 99 1f:IIA1 19 1 If:IIAl 119 1 If:IIAl 119 1 raul 19 1 rfILA; I rlMl 1 , 1f:IIA'1 99 'I 1 B 11 reo»J fOWl 81 II rmJIS rErl.\8 II II /1B'llOI6 1f:IIA8 .11 8 IlOUT 1'~ 'f'lA~ 8;. 8 IXXI! !.!.n(rtlOIll rEIII8 0i i IlOUT ~11fIOJll1 fOWl .81 8 IMlIT II tIBOlII2 1f:IIA8 81 8 IlOUT 1fM8 II 8 IlOUT 8 IMlIT 8 IlOUT i 81 IRASI II tRASI 81 RAS tRASI 81 RAS tRASI II RAS 1RAS,81 RAS IRASI RAS RAS '!lAS i '!\jRAS I IC.\SI IS 'rA~i ICAII \~ CIS l(i51 15 ICISI 15 tClSl IS CIS ICISI 15 CIS IC.\SI 15 CAS CAS ..0qrAs CIS CIS IJ ~'~. IJw; IJ 1311: IJ w; IJ II: 'IE ~\w: i IlE tllSl256 tllSl256 tII:II156 1f\'iI256 lfl5ll256 I 'll'llll:it: 1128 l13li ,InD.. __ ._J J~rr~ 1125 fl2G fl21 L ______... ---_._-- 8S IIBIII IS ,.. rEIII8~'-8-1 IfMI~!I IEN8 lIS All IEIIA8 IS 18 rENe All IEN8 IS AI If:IIAI 11 I rEnAl III 1 rEllAl f1 I nfM, !L, 1 IOIlI~1 rEnAl III I rEnAl ~11 I ll6 lG rf!1oI2 16 2 1f:IIA2 IG 2 !f!lAI ~ I 1EllA2 2 rElII2 IG 2 rEllA2 2 1f:IIA) 12 ) If:IIAJ 12 ) rElII3 12 3 IEIIoIJ 12 3 1f:IIA3 12 3 .~ 1<, 1 12 12 82 reIIl II I DIN 12· 'ne'lA' W 1 DI~ I.IInPllll8 rlMI.1 I Dl~ 119 rErl.\l It 1 DIN 82 reo I II If:IIAI 11 I DIN 112 rErl.\l 11 I OIN li3 rElIII +i1' DIN 82 III lfIOlis 1llII5 II rEnA5~5 tellS II S nelli' .!!' ~ =j:Ifl1AS .!! 5 IEI1oI.'i 'I 5 5 1EI1oI.'i" 5 rflIII) I) ISIIG 13 IBII£ 13 ISIIG I) 6 If:III6 13 G nlJlAC .~ c rfJlAG IJ, I G G 1EllA7 19 1 'f'lA1 ~;1 I rlMl If! J I I'Elll:I If! 1 rEllAl 19 ~ rEnA7 119 1 1f:IIA7 119 1 9 1DJl'I11 Il/IIIl 11 1f:IIA8 81 8 IDJl 11 reool1 99 II 8 IlOUT 11 reool5 ri'IA8 ~ 8 IXXI! linr'Ol88 fOWl II 9 IlOUT 11190)11 11 1llII9 1\ 12 9 IlOUT lI-1E11OO13 I1 tRASI" RAS 'RASI ~RAS ~,~~.m tRASI II RAS IRASI RAS 1RAS1" RAS tRASI "RAS 1(Al1 15 [IS "_ /cASI IS CAS !CASI 15 CAS !CASI 15 CIS !CASI IS CAS !CASI 15 CAS IJ IJ tl 'W[~ WI' IIJW( IJIo1: lllWE WE llE fIW56 IIIS82S6 \tI582SG 1IISll256 r "'~"Ist I llflSl25G I1J8 '''''I''nJi n32 lOS 1136 nJ1 1"- ._------ ffJ118 Ili AI rENe 8S A8 I£MI 8S All IEIIMl 15 All rENe IS A8 ri'1l9 ~I-' IEIIII 87 I lOlA, !!.j 1 IfMI .!L 1 1(1\\1 III I IEIIII B1 IfMI r1 I .~ 1 IG rElII2 116 1f:IIA1 IG 2 rEIIA2 IG 2 rfllli 2 1f1II2 ll6 1 IEllA2 1 riMJ .!.!..IJ Ifl1AJ .!1. 3 IEIIoIJ 12 ) IEIIoIJ 12 IElIAJ 12 3 IEI10IJ 12 3 !f1ll1 .!!..! 1 Dl~ 11 C838 r(tlll H I OIN 12 CllOI rf!1oI1 11 I 01. 82 C902 If:IIAI \I OIN 82 C803 If:IIAI 11 I DIN 12 CllOI rEnAl 11 I DIN 82 C8ll5 !f'lA\ .!!, 5 i 1fM\ 18 5 1EI1oI.'i" 5 tEIIAS" IEI1oI.'i II S I(lIIG 13 G rew; 13 G IEIIIG 13 IIEIIIG 13 G If'lAC ~~ G ~ ri'lAl -I I rlMl 99' J 1810\1 19 7 1f:IIA7 119 1(1\\7 19 7 1f'lA8 ~ 8 IXXIl 11 C818 rfMO II 9 OOUT 11 CDli Il/IIIl .1\ 9 IlOUT 11 CDI2 fOWl" 9 IlOUT 11 CDIJ 'CDI1 IEIIA9 I' 8 1nJ! 11 CBI5 .~JRAS .11AS1 B! RIS lRASI B! S tRASI 81 !lAS IRASI .,~ RAS tRASl 81 RAS lUSI I l\~rAS ICASI IS ICASI IS ICASI 15 CAS §ICASI 15 CIS ItAll 15 CAS 'ClSi CIS CAS L'r IIJ 83 ~l~ w: VI: IJ\IE IJII: IJ WE 1 II !f\.'i8'IS€ I ~2~ 11158256 1tlSll25G IIIS82S6 \tI582SG n,9. __ 1 n~L nIl 1\12 ii!LJ nl1 , ____. __.. ---L . I ...L. ..--l ...., . :i-=-~-= ,I :1 II NJI N "J2" C01 A01 B01 C01 /BBBSY J301 B008 LOC000 LOC008 "C02 "A02 "B02 "C02 J302 B009 LOC001 LOC009 D "C03 "A03 "B03 C03 J303 B010 LOC002 LOC010 D "C0'1 " I J30'\" C0'\ /BBG0INj' J30'1 BOll LOC003 r!'0'1 LOC011 D "C05 r!'05 , J305 C05 /BBG00UT J305 B012 LOC00'1 LOCOl2 D "C06 A06 B06 C06 /BBG 1IN J306 B013 LOC005 LOC013 D "C07 "A07 J307" C07 /BBG lOUT J307 B01'\ LOC006 LOCOI'l D "C08 "A08 J308 C08 , /BBG2 IN J308 BOIS LOC007 LOC015 D "C09 "A09 J309 C09 /BBG20UT J309 D C10 "A10 "B10 CI0 /BBG3 IN J310 /CLK /NWCIACK D "Cl1 "All J311 Cl1 /BBG30UT J311 /BBERR /J2EOCUBERR D I "C12 "A12 B12 C12 /BBREQ0 .13 12 /SYSRESET /UDS /RESET D "C13 "/'13 "J313 C13 /BBREQ 1 .13 13 /BLWORO /LDS /BRI D I " Al'1 J31 '\ Cl'\ /BBREQ2 J31 'I BAM5 "Cl 'I LRO /BGI D CIS "r!' 15 J315 CIS I /BBREQ3 J31 5 BA23 A23 D "C16 J316 C16 I BAM0, J316 BA22 /OTACK r!' 16 A22 I "C17 A17 B17 "CI7 BAM~"BI7 BA21 A2\ D I 18 "C18 "A18 "B18 I C18 BAM2 .13 BA20 D /MAS A20 D 19 " "J319 C19 BAM3 .13 BA 19 "C19 r!' 19 I AI9 D A20 J320 C20 20 BA 18 1 "C20 A18 D i "A21 J321 I C21 21 BA 17' "C21 /CA A17 D 1.13 " I C22 ! r!'22 I J322 D IJl22 BA16 "C22 /BGACKI i A16 r B23 C23 A23 , B23 C23 I BA15 /NWCIRQ A15 D "C2'\ "A2'1 " C2 ! /BIRQ7 J32'1 BA1'\ A07 "B2'1 Al'\ D '\ 25 "C25 "A25 25 C25 /BIRQ6 .13 BA13 A06 D .13 A13 D " A26 /BIRQ5 Jl26 BI\.12 "C26 A05 J326 A12 "C26 27 C27 "A27 J327 t27 /BIRQ'\ .13 BA 11 A0'1 All D " "A28 /BIRQ3 J328 BI\10 C28 A03 Jl28 A10 "C28 29 "C29 "A29 B29 C29 /BIRQ2 .13 BA09 A02 A091 D "C30 "A30 "B30 C30 BA08 A01 A081 D "C31 "A31 "B31 C31 +12V D +12V " -12V " " ::~I C32 A32 VCC' J332 vcc~oC32 /B I !,::8 VCC " VCC " I 1 C96FC C96FA C96FB C96FCj ~~ CIC ~ C2B C2C I I .on, rONN::r:~~~:~~~~~:~~ j 00000000000" "qPQDDDOODDDD I!! DDDDDDDDDDD "'D" c·····:: DDODDDDD j:: I.~~;;; ~ ~;;::1 lcSS ~ .r1 r1 r1 00000 r1 r1 019 2B DDC5, IC61 oCH DDC'S OCS6 jj bJbJbJ 26 7 2S 29 3B bJbJ 33 :::: , ::: •• •• IC73 CH ••• 21 ::.. ..:: .:::.. , •• •• C,9 ICH C,6 rCS7 'Cll( ~~ ~ ,,~ ,,~ .------rr--o 0D"DDODD',~ ~ DD D" n'" i::: " '" .. rv "'" ,,,. '" n, LJ lJ .. ~ ICS6 G;: •• ~U lCS7~ 3 C92 JCS9 22 ••• -u --u IC2' lC2 D 4<11 IC3S U D fCI2 :::••• ICS9 CII 23 22 ::: C29 U r1 ~ ." 4<11DD lCI3 ::: 27 DD . lC3B 26 r1 D :::... .. ~g ::: :: ICSS IC6 lC ICS IC7 CIB lC9 IC38 2 5 C32 IC'S C,3 IC'2 12 \3 H :C~; STR3 STR' ••" =// Tl= 57 11: UUUUUUUUUWWW:,:, uuuuuuuuuuu iiiDDDDDD DD j'<;;;l, 0:: DDDDDDDDDDD u H ~ ·.·. ·.·. ·.·. . .~, m,.~ ~ ·. ·. .~, ~ ·.·. ·. DOD "DO ,ODODD: Q0 ··.. ·. It ~ :;] aOJI ~ SS £s L.- '-- APPENDIX B PROGRAMMABLE LOGIC FUNCTIONS PAGE 85 Page 1 ABEL(tm) Version 1.00 - Document Generator 26-Sep-84 INTRODUCTIOij THE KUNix machine 68010 board Wi~ v.d. Heuvel. University of Technology Eindhoven. department of Electrical Engineering Date: 20-August-1984 General introduction into the PAL equations These documents describe the signals generated at the 68010 board with VHE interface. All signals are generated in programmable logic devices. The documents are a brief summary of .'LOGIC FUNCTIONS OK THE 68010 BOARD' [LIT. 8]. CONVENTIONS: Signal polarity: signals having an active low polarity at the in- or output pin of a device are indicated by an underscore () immediately following the name (MHB .MAS-). In the drawings of the 68010 board these signals are preceded by a slash (!MHB.!MAS). ABEL does not allow a slash to appear in a name. instead of a slash the underscore is used. Signal names ABEL does not allow a name to begin with 'a nunber. All names in t~e drawings of the 68010 board. are changed to begin with a letter (68 -) CPU. 8207 -) RN1CTRL). See also 'Signal polarity'. inversion sign := clocked assignment = immediate assignment =) greater then or equal == equal <= less then or equal Page 2 ABEL(tm) Version 1.00 - Document Generator 26-Sep-84 INTRODUCTION THE KUNix machine 68010 board Wim v.d. Heuvel, University of Technology Eindhoven, department of Electrical Engineering Date: 20-August-1984 General introduction to the PAL equations " DEVICE DEVICE DRAWING DEVICE NJJMBER TYPE NffilBER NA'1E ------Pl 16R4 7 BUS REQUESTER P2 14H4 1 INTERRUPT LEVEL SHIFTER PJ 16L8 1 INTERRUPT ACKNOWLEDGE DECODER p4 16R4 1 INTERRUPT DAISY CHAIn 0 P5 16R4 1 INTERRUPT DAISY CHAIN 1 P6 16L2 7 INTERRUPT SELECTOR P7 16L8 1 STROBES UNIT P8 16L8 8 HALT & RESET CONTROL P9 16R4 2 LOCAL BUS ARBITRATION & SEMAPHORE PI0 14H4 2 DTACK Pll 16L8 2 BUS ERROR P12 20LlO 3 LOCAL ADDRESS DECODER 1 P13 20LlO 3 LOCAL ADDRESS DECODER 2 P14 20L8 3 LOCAL ADDRESS DECODER 3 P15 20L8 5 D-RAl'1 CONTROL 1 P16 I6L8 5 D-RAM CONTROL 2 P17 I6L8 6 ~1E INTERRUPTER 1 PIS 16L8 6 VME INTERRUPTER 2 P19 16L8 7 VME ADDRESS DECODER 1 P20 16L8 7 \!tiE ADDRESS DECODER 2 P21 16L8 7 DATA TRANSFER BUS MASTER P22 16L8 7 BUFFER CONTROL 1 P23 I6L8 7 BUFFER CONTROL 2 p24 82S105 7 BUFFER CONTROL STATE MACHINE Page 1 ABEL(tm) Version 1.00 - Document Generator 26-Sep-84 BUS REQUESTER TIlE KUNix machine 68010 board Wi~ v.d. Heuvel, University of Technology Eindhoven, department of Electrical Engineerin3 Date: 20-August-1984 Equations for ~odule BUSREQUESTER Device PI Original Equations: BREQxOUT :'"' lAWB_ & !BBUSYOUT & SYSRESET_, !ANYREQ_ '"' lBBREQO_ # !3BREQ1_ /I !BBREQ2_ # !BBREQ3_; ! ~lEI3GR..~OUT := 1VHEBGRxIN & NHB & MGB & 1BBUSYOUT If l'l..'IEBGRxOUT- & ! ~IEBGRxW- & SYSRESET_; nfHJSYOUT :'"' V:U:::f3GRxOUT & lVtlEBGRxHI & !~llm it B3USYOUT-& !~HJB & SYSRESET {I E13USYOUT [. :mB & ANYREQ_ £. molDOPIION & SYSl{ZSET_; !:IG13 := Y:IEBGRxOUT & 1~IEnGRxIN & l:·nm /I VHEBGRxo'UT & BBUSYOUT & !:1Hi3 tUlB !>IGB & V:IEAS & V:'IEDTACKI~ & SYSRESET If n'IRE & n·mB & BBUSYOUT '& SYSRESET_; end of module BUS REQUESTER Page 1 ~BEL(tn) Version 1.00 - Document Generator 26-Sep-84 ItlTERRUPT LEVEL SHIFTER THE KU~ix machine 68010 board Wim v.d. Heuvel, University of Technology Eindhoven, department of Electrical Engineering Date: 20-August-1984 Equations for ~lodule I~TSHIFT Device P2 Original Equations: LA03 = ~'lEIACKOUTO & ~1EIACKOUTI & LA03IN # !~1EIAC LAO 2 V:·lEIACKOUTO & WlEIACKOUTI & LA02IN # !~1EIAC~OUTO & WIEIACKOUTI & I'lLOI # lV:1EIACKOUT1- & I'lLll; LAO 1 'l:--IEIACI~OUTO & Vl-IEIACKOUTl & LAOlIN # !W1EIACKOUTO & ~IEIACKOUTI & I'lLOO # l ~IEIACKOUTl- & I'l110; end of module ItITSHIFT Page 1 ABEL(tn) Version 1.00 - DOCUMent Generator 26-Sep-84 Ii:TERIWPT .\CKNOHLEDGE DeCODER THE KUNix macn1ne 68010 board Wim v.d. Heuvel. University of Technology Eindhoven. department of Electrical Engineering Date: 20-August-1984 Cquations for ~'lodule INTACKDEC Device P3 Original Equations: !BRE,U~POINT_ = ([FC2.FC1.FCO] 7) & lLAS_ & lLA04; lAUTOVEC = ([FC2.FC1.FCO] == 7) & ([LA03IN.LA02IN.LA01IN] == 7) & !LAS & w\04 # ([FC2.FC1.FCO] == 7) & ([LA03IN.LA02IN.LA01IN] == 5) & lLAS & LA04 II 1lACY-AUTO l- It 1lACKAUTOO ; IN:lIACK = ([FC2.FC1.FCO] == 7) & ([LA03IN.LA02IN.LAOlIN] == 7) & !LAS_ & LA04; !TI:-lIACK ([FC2.FC1.FCO] == 7) & ([LA03IN.LA02IN.LA01IN] == 6) & !LAS_ & LA04; !\~EKlACK = ([FC2.FC1.FCO] == 7) & ([LA03IN.LA02IN.LAOlIN] == 5) & lLAS_ & LA04; lDSYlIACK = ([FC2.FC1.FCO] == 7) & ([LA03IN.LA02In,LAOlIN] == 4) & !LAS_ & LA04; lPllACK = ([FC2,FC1,FCO] == 7) & ([LA03IN.LA02IN,LA01IN] == 3) & !LAS_ & LA04; lDSYOlACK ([FC2.FC1.FCO] == 7) & ([LA03IN,LA02IN,LA01IN] == 2) & !LAS ~ LA04; end of module lNTACKDEC ,''''.... ". Page 1 ADEL(tm) Version 1.00 - Document Generator 26-Sep-84 I~TERRUP'I' DAISY C1L\IN 'i'HE KUNix machine 63010 board Wim v.d. Heuvel) University of Technology Eindhoven) department of Electrical Engineering Date: 20-August-1984 Equations for Module ISTDAISY Device P4 Original Eeruations: IRQLO_ := IRQINO_; IRQLl- := mQIN1- ; IlQL2- := IRQIN2_; !IRQOUT_ !IRQI~O_ # !IRQIN1 # !IRQIN2_; ! IACKOUTO ! IACKIN & !lRQnW_ & ! lRQLO_ & lACKOUTl & lACKOUT2 &. !CLK !! ! lACKo"UTO &.! IACKlN & L\CKOUT1 &. lACKOUT2_ J !IACKOUT1 = !IACKlN & !IRQlN1 & !IRQL1 & lRQLO_ & lACKOUTO &. IACKOUT2 &! CUe # lIACKOUT1 & !IACKIN & IACKOUTO & lACKOUT2_ J ! lACKOUT2 ! lACKlN &! lRQm2 &! lRQL2 _ & IRQLO_ & lRQL1 & IACKOUTO & lACKOUT1 & !CLK II ! lACKOUT2 &! lACKU; & lACKOUTO & lACKOUT1 end of module lNTDAlSY '-..'- Page 1 AflEL(tm) Version 1.00 - Document Generator 26-Sep-84 VlTEI',JWPT SELECTOIt THE KUNix machine 68010 board \nm v.d. lIeuvel, University of Technology Eindhoven, department of Electrical Engineering Date: 20-August-1984 I:qua tions for :-1odule INTSELECT Device P6 Original Equations: I'f.1E IRQO_ = ([IVL02,IVL01,IVLOO] == 7) & IBIRQ7_ # ([IVL02,IVL01,IVLOO] == 6) & IBIRQ6_ # ([IVL02,IVL01,IVLOO] == 5) & IBIRQS # ([IVL02,IVL01,IVLOO] 4) & IBIRQ4_ # ([IVL02,IVL01,IVLOO] -- 3) & IBIRQ3 # ([IVL02,IVL01,IVLOO] == 2) & IBIRQ2- " ([IVL02,IVL01,IVLOO] == 1) & IBIRQ1=; I"HEIRQ1- ([IVL12,IVL11,IVL10] == 7) & IBIRQ7 # ([IVL12,IVL11,IVL10j 6) & IBIRQ6 # ([IVL12,IVL11,IVL10] == 5) & IBIRQS= # ([IVL12,IVL11,IVL10] == 4) & IBIRQ4_ # ([IVL12,IVL11,IVL10] 3) & ! 13IRQ3 # ([IVL12,IVL11,IVL10] -- 2) & IBIRQ2- if ([IVL12,IVL11,IVL1O] == 1) & !BIRQ1- ; end of module INTSELECT Page 1 ABEL(tn) V~rsion 1.00 - Document Generator 26-Sep-84 ~;TROnES U:UT THE KUNix machine 68010 board Him v.d. Reuvel, University of Technology Eindhoven, department of Electrical Engineering Date: 20-August-1984 Equations for Module STROBES Device P7 Original Equations: enable 'lAS BGACK_, !~lAS = I 11·L\S & I LAS enable LOS (!MAS & BGAC~); ! LOS !LLDS &!UIAS & LRD II ! LLDS & !I:1AS &! LRD & UIN_; enable UDS IUDS I LUDS & !L~AS & LRD If ILUnS & !U1AS &! L~D & HIN_; LOCDATASTL: ILDS II IUDS; ! ENAB = BGACKO & !"lHE II! BGACKO &! VHEAS_; !ENLDB I LAS & BGAC~; end of module STROBES Page 1 ABEL(tm) Version 1.00 - Document Generator 26-Sep-84 }~LT & RESET CONTROL THE KUNix machine 68010 board Wim v.d. Heuvel, University of Technology Eindhoven, department of Electrical Engineering Date: 20-August-1984 Equations for Module HLTRESCTRL Device P3 Original Equations: lHLTYO «[llLTYl ,HLTYO ] == [1,0]) II !HAS - # lSTEP_) & RESET_; 1HLTYI = « [HLTYl_,HLTYO_] == [0 ,0]) 11 !MAS_) & RESET_; HALT = ([!ILTYl_,HLTYO_] != [1,0]) .& HLT II lRESET_; 1SHORTRSSET_ = PORST it !SYSRESET_; lRESET8207 = lRESET & lDELRESET & 1300TO_; ! V:1E IACKOUT lVMEIACKOUTO 11 1~1EIACKOUTl_; end of module HLTP£SCTRL Page I A8EL(tm) Version 1.00 - Docunent Generator 26-Sep-84 LOCAL BUS ARnITRATIO~ & SDIAPHOr£ , THE KU;Ux machine 68010 board Wim v.d. lleuvel, University of Technology Eindhoven, department of Electrical Engineering Date: 20-August-1984 Equations for :'lodule ARBIT Device P9 Original Equations: !BGO !BG & !BRO & !BRLO & BGI if !BG & !BiO & ! BGD £.. BGl-' ! BGI ! HG & ! BTU &! BRLl & BRLO & BGO it !3G & ! BRI &! BGl £.. BGO=; SE1YO := !RESET # SE1YO £.. VS~l # !ENS}~lREG_; SE:IAPlIORE := ! RESET if SE,\lYO £.. ENSE:-1REC If SE:1APHORE & ! VSC1 ;{ SCIAPaOE>J:: £.. ! E:iS.6i'REG -' end of ~odule ARilIT Page 1 ABEL(tm) Version 1.00 - Docunent Generator 26-Sep-S4 DTAC1: TRE KUKix machine 68010 board Wim v.d. Reuvel, University of Technology Eindhoven, department of Electrical Engineering Date: 20-August-1984 Equations for ~odule DTACK Device PIO Original Equations: DTACKIN = lHHB & 1~1EDTACKIN It LOCDTACK; SELNODTACK = !SEL'lPSC It !5EL8254 It lSELERR # lCSROM_; ~lEDTACKOUT = BGACKO & l~\CK & ESTB & lVMEBERROUT It lBGACKO & lDTACK fI V:1EDTACKOUTF & ! ENVHEDB & ESTB & lVHEBERROUT; end of module DTACK -. .~ . ,'... Page 1 ABEL(tm) Version 1.00 - Document Generator 26-Sep-84 BUS ERROR TIlE KUNix oachine 68010 board Wim v.d. Heuvel, University of Technology Eindhoven, departoent of Electrical Engineering Date: 20-August-1984 Equations for Module BERR Device Pll Original Equations. 1\1i·1EBERROUT = 1BGACKO & 1BERR II 1LOCACCESS & l}1JlB # lESTB & lECCERROR- & lCORRERROR & laux & LOCK & wmSELSEH # lW1EBERROUT &-1~1EDATASTB_; lEDCUBERRFAT = lESTn & lECCERROR & lCORRERROR & HUX & -LOCK & lCPUSELSE1 II 1J2EDCUBERR_; ! EDCUBERRCOR = 1ESTB &. !ECCERROR £. COP..RERROR £. ~tuX £. LOCK & CPUSELS~I_; end of module llERR Page 1 AnEL(t~) Version 1.00 - Document Generator 26-Sep-84 LOCAL ADDP~SS DECODER 1 THE KUNix machine 68010 board Wi~ v.d. Heuvel, University of Technology Eindhoven, department of Electrical Engineering Date: 20-August-1984 Equations for ~odule LADECI Device P12 Original Equations: !CPUSELRA:-l = ([A23,A22,A21,A20,AI9,AIB,AI7,AI6,.X.,.X.,.X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X.] )= 0) & ([A23,A22,A21,A20,AI9,AIB,AI7,AI6, .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X.,.X.,.X.,.X.] (= Ah3FFFF) & !MAS & !RAM64K & SETUP - # ([A23:A22,A21,A20,AI9,AI8,AI7,AI6,.X.,.X.,.X., .X., .X.,.X., .X., .X., .X., .X., .X., .X., .X., .X.,.X., .X.] )= 0) & ([A23,A22,A21,A20,AI9,AI8,AI7,AI6, .X.,.X.,.X.,.X.,.X.,.X.,.X.,.X.,.X.,.X.,.X.,.X., .X.,.X.,.X.,.X.] (= AhFFFFF) & !MAS & ~164K & SETUP_; !SEL~1EST ([A23,A22,A21,A20,AI9,AIB,AI7,AI6,.X.,.X.,.X., •X. ,•X. ,• X. ,•X. ,•X. ,•X. ,•X. ,•X. ,•X. ,•X. ,• X. ,•X. , .X.] )= AhCOOOOO) & ([A23,A22,A21,A20,AI9,AI8, A17 ,1\16, •X. ,•X. ,•X. ,•x. ,. X. ,• x. ,. X. ,•X. ,•X. ,•X. , .X., .X., .X., .X., .X., .X.] (= AhFFFFFF) & !HAS_; !SELLOCIO ([A23,A22,A21,A20,AI9,AI8,AI7,A16,.X.,.X.,.X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X.,.X., .X., .X.] )= AhBCOOOO) & ([A23,A22,A21,A20,A19,A18, A17 , A16 ,•X. ,•X. ,•X. ,•X. ,• X. ,•X. ,•X. ,•X. ,• X. ,•X. , .X.,.X.,.X.,.X.,.X.,.X.] (= AhBCFFFF) & !MAS & L'IADO_; !SEL~1EIO ([A23,A22,A21,A20,A19,AI8,A17,A16,.X.,.X.,.X., •X. ,•X. ,•X. ,•X. ,•X. ,•X. ,•X. ,•X. ,•X. ,•X. ,•X. ,•X. , .X.] )= AhBDOOOO) & ([A23,A22,A21,A20,A19,A18, AI7,AI6,.X.,.X.,.X.,.X.,.X.,.X.,.X.,.X.,.X.,.X., .X. , .X. " X. , .X. , .X. , .X.] (= AhBDFFFF) & IMAS_; !SELROM ([A23,A22,A21,A20,A19,A1B,A17,A16,.X.,.X.,.X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X.] )= AhBEOOOO) & ([A23,A22,A21,A20,A19,A18,A17, A16, .X., .X., .X., .X., .X., .X., .X., .X., .X., .X.,.X., .X.,.X.,.X.,.X.,.X.] (= AhBFFFFF) & !MAS /I !HAS & !SETUP_; !PEA = ([A23,A22,A21,A20,A19,A18,A17,A16,.X.,.X. 1 .X.,.X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X.] )= 0) & ([A23,A22,A21,A20,A19,A18,A17,A16,.X.,.X.,.X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X.] (= Ah3FFFF) & !~AS & !RA~64K & SETUP Page 2 ABEL(tm) Version 1.00 - Document Generator 26-Sep-84 LOCAL ADDRESS DECODER 1 TIlE KUNix machine 68010 board Wim v.d. Heuvel, University of Technology Eindhoven, department of Electrical Engineering Date: 20-August-1984 Equations for ~odule LADECI Device P12 II ([A23, A22, A2l , A20, A19, A18, Al 7, A16, •x. , •X. , •x. , •x. , .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X.] )= 0) & ([A23,A22,A2l,A20,A19,A18,A17,A16,.X.,.X.,.X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X.] <= AhFFFFF) & !MAS & RA~64K & SETUP II !LOCDPIO_; !~WB = !SELvrtEST /I !SEL~[EIO II !MAS & !vrtEIACKOUT_; ISELNOPI ([A23,A22,A2l,A20,A19,A18,A17,A16,.X.,.X.,.X., .X., .X., .X., .X.,.X., .X., .X., .X., .X., .X., .X., .X. , .X.] )= AhBOOOOO) & ([A23,A22,A2l,A20,A19,A18, A17,A16,.X.,.X.,.X.,.X.,.X.,.X.,.X.,.X.,.X.,.X., .X.,.X.,.X.,.X.,.X.,.X.] <= AhBBFFFF) & !MAS # ([A23,A22,A2l,A20,A19,A18,A17,A16,.X.,.x.,7x., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X.] )= AhBCOOOO) & ([A23,A22,A21,A20,A19,A18, A17,A16,.X.,.X.,.X.,.X.,.X.,.X.,.X.,.X.,.X.,.X., .X.,.X.,.X.,.X.,.X.,.X.] <= AhBCFFFF) & !MAS & MADO_; end of module LADECI .-, Page 1 AUEL(tm) Version 1.00 - Document Generator 26-Sep-84 LOCAL ADDRESS DECOD[R 2 TIlE KUNix machine 68010 board Wim v.d. Heuvel, University of Technology Eindhoven, department of Electrical Engineering Date: 20-August-1984 Equa t ions for ~10dule LAOEC2 Device P13 Original Equations: lSEI.;r-1UO ([A08,A07,A06,A05,A04,A03,A02,AOl,.X.])= 0) & ([A08,A07,A06,A05,A04,A03,A02,AOl,.X.] <= Ah3F) & lSELLOCIO & LOCOATASTBi lSEL:.'l:1Ul ([A08,A07,A06,A05,A04,A03,A02,AOl,.X.])= Ah40) & ([A08,A07,A06,A05,A04,A03,A02,AOl,.X.] <= Ah7F) & lSELLOCIO_ & LOCDATASTBi lSELPIT ([A08,A07,A06,A05,A04,A03,A02,AOl,.X.])= Ah80) & ([A08,A07,A06,A05,A04,A03,A02,AOl,.X.] <= AhBF) & ISELLOCIO & LOCDATASTBi ISEV1PSC = ([A08,A07,A06,A05,A04,A03,A02,AOl,.X.] )= AhCO) & ([A08,A07,A06,A05,A04,A03,A02,AOl,.X.] <= AhC7) & lSELLOCIO_ & LOCDATASTB & !LDS_i !SEL8254 ([AOR,A07,A06,A05,A04,A03,A02,AOl,.X.])= AhC8) & ([A08,A07,A06,A05,A04,A03,A02,AOl,.X.] <= AhCF) & ISELLOCIO & LOCDATASTB & lLDS_i lSELERR = ([A08,A07,A06,A05,A04,A03,A02,AOl,.X.] )= AhDO) & ([A08,A07,A06,A05,A04,A03,A02,AOl,.X.] <= AhDl) & lSELLOCIO & LOCDATASTB & LRDi lSELLOCID (lA08,A07,A06,A05,A04,A03,A02,AOl,.X.] )= AhD2) & ([A08,A07,A06,A05,A04,A03,A02,AOl,.X.] <= Ah03) & lSELLOCIO_ & LOCDATASTB & lLDS & LRDj 1CPUVSE·1 ([A08,A07,A06,A05,A04,A03,A02,AOl,.X.] )= AhD4) & ([A08,A07,A06,A05,~04,A03,A02,AOl,.X.] <= AhD5) & lSELLOCIO & LOCDATASTB & lLDS & ILRDj lCPUSELS&1 = ([A08,A07,A06,A05,A04,A03,A02,AOl,.X.] )= - AhD4) & ([A08,A07,A06,A05,A04,A03,A02,AOl,.X.] <= AhD5) & ISELLOCIO_ & LOCDATASTB & !LDS & LRDi lCPUSELDPIO = ([A08,A07,A06,A05,A04,A03,A02,AOl,.X.] )= - AhD4) & ([A08,A07,A06,A05,A04,A03,A02,AOl,.X.] <= AhD5) & !SELLOCIO & LOCDATASTB & ILDS_j end of module LADEC2 " .- ':;,. Page 1 ABEL(tm) Version 1.00 - Docunent Generator 26-Sep-84 LOCAL ADDRESS OECODErr 3 THE KUNix machine 68010 board Wi~ v.d. Heuvel, University of Technology Eindhoven, depart~ent of Electrical Engineering Date: 20-August-1984 Equations for Module LADEC3 Device P14 Original Equations: ! CSRat !:IAS & LOCDATASTB & ! SELR~1 &! ROHS12K & ROH256K & ROM128K & ROH64K- # !fIAS & LOCDATASTB & ! SELROt1 & A16 & RO:lS12K & ! Rm-12S6K & R~1l28K & RO~164K # !MAS &LOCDATASTB & !SELRG1 & A16 & A1S & ROt-lS12K & ROM2S6K & !Rm1l28K- & Rm164K II !MAS -& LOCDATASTB &! SELROtC & A16 & A1S & A14 & Ro:1512K & Rm12S6K & ROM12SK &! ROM64K II !:IAS &-LOCDATASTn-& !SELROH -& A16 & A15 & A14 & A13 &RO:1512K & ROM256K & ROM128K & ROM64K # !MAS & LOCDATASTB & !SELROM & !SETUP_; ! SELNOP !:lAS & LUCDATASTB &! SELROH & SETUP &!A16 & RO:lST2K II !:IAS -& LOCDATASTB & !SELROtl & SETUP & !A15 & Rm1512K & ROM256K II !:IAS & LOCDATASTR & !SELR Ra1AlS A15 II ROttS12K & ROM256K_; ~nd of module LADCC3 Page 1 ABEL(tm) Version 1.00 - Document Generator 26-Sep-84 D-RA:-1 CONTROL 1 THE KUNix machine 68010 board Wim v.d. Heuvel, University of Technology Eindhoven, department of Electrical Engineering Date: 20-August-1984 Equations for :lodule Rl~lCTRLl Device P15 Original Equations: !:1UXEtI = SELINSTRBUF If :mx; !'IPXA1 a = ~mx & !AI0 If l2-fUX & SELINSTRBUF & !~tEA10; !:lPXA09 = >1UX & !A09 II !ilUX & !VMEA09; !BSO = !:'lUX & lRM64K & lV:1EA17 If l~tUX & lW-t64K & 1~IEA19 If ~mx & lRN164K & lA17 II ~1UX & RAa64K -o. 1A19; 1\~E RA.'lCTRUlE & FORBIDWD & (l CPUSELRAM_ & PSEL II 1V:-IESELRA:l o.! PSEL) 11 1DTIH & RA'1CTRLHE; end of oodule RX{CTRL1 Page 1 AilEL(tm) Version 1.00 - Document Generator 26-Sep-84 D-RA:l cmHROL 2 THE KUNix machine 68010 board Wim v.d. Heuvel. University of Technology Eindhoven, departrJent of Electrical Engineering Date: 20-August-1984 Equations for Hodule RAHCTRL2 Device P16 Original Equations: IPBRD WIEREAD & (!DSO_ # IDS1_); ! PBHll IVHEREAD & (I DSO_ II IDS 1_) ; LOCK = PSEL & PSEN # l~AS & MUX & LOCK fI lPSEL & PSEN # I\~EAS & l~UX & LOCK; 1F\.JR = ~lUX & ILDS & IUDS II l:otuX & 1DSO &! DS1_; !V1EDATASTB = IDSO # lDS1_; end of module RN1CTRL2 Page 1 AUEL(tm) Version 1.00 - Document Generator 26-Sep-84 ~lE INTERRUPTER 1 THE KUNix machine 68010 board \~im v.d. Heuvel, University of Technology Eindhoven, departoent of Electrical Engineering Date: 20-August-1984 J::quations for :'lodule v:iEINTl Device P17 Original Equations: IRQl = ([WtEI2_,VaE11_,'r.·lElO_l == 6) & 1LIRQ_; mQ2 = ([~lEI2_,\R·lEIl_,\f.·tEIO_1 == 5) & lLlRQ_; IRQ3 ([V!lE12_,V:IE11_,V}lEIO_] -- 4) & lLIRQ_; IRQ4 = ([W1E12_, W·IEll_, Vt-lElO_l == 3) & 1LlRQ_; IRqS ([WtEI2_,WIEII ,~lEIO 1 -- 2) & lLIRQ IRQ6 «~1EI2 _, \R·1E 11 , Vt1EIO] 1) & ! LlRQ IRQ7 = (['r.·1EI2_,VME11_,'r.·tEIO_] 0) & lLlRQ_; ! FORBlDWD = PSEL & ! CPUSELDPIO & ! ECCRI-l II lPSEL & !~ESELDPIO & lECCRW II 1FORBIDlJD & RA'1CTRlilE; end of I:lodule ~1EINTI Page 1 ABEL(tm) Version 1.00 - Docu~ent Generator 26-Sep-84 ~lE INTERRUPTER 2 THE KUNix machine 68010 board ~im v.d. Heuvel, University of Technology Eindhoven, department of Electrical Engineering Date: 20-August-1934 Equations for ~odule ~lEINT2 Device PIS Original Equations: ILIRQ_ = ! PITlRQVUE_ & \f.-lEIACKIN II ILIRQ_ & XACK_; ! DSYI/\CKOUT =!'r.lElACKIN & IDSYlACKeI & (LIRQ II ILIRQ_ & ILEQUA & I ~lEAS=) & XACK= & VNEDTACKIN # IDSYIACKOUT & l~lEAS & SYSRESET_; ! READINTVEC = IV:'lEIACKH: & IDSYIACKli-i & ! LIR~ & IVMEAS & LEQUA; I LOCDPIO ICPUSELDPIO & BGACl:O_; IBGACK IBGACK.O II! BGACK1_; end of module V:-lEINT2 Page 1 ABEL(tm) Version 1.00 - Document Generator 26-Sep-84 VHE ADDRESS DECODER 1 THE KUNix machine 68010 board Wim v.d. Heuvel, University of Technology Eindhoven, department of Electrical Engineering Date: 20-August-1984 I:quations for :1odule 'f.1EADECl Device P19 Original Equatiol,~' IIONI 1'f.·1EAS & ([.-\;1S,A'14,AH3,.X.,N-ll,AHO) == [l,O,l,.X., 0,1));- ISTACCESS 1V:1EAS & ISYS~1 & RA~64K & ([~IEA23,~IEA22, V:'1EA21~Vt'1EA20, Vl-iEA19 , V:1EA18, •X. ,• x. ,.x. ,.x. ,.x. , .X., .X., .X., .X., .X., .X., .X.,.X., .X., .X., .X., .X., .X.) )= 0) & ([V:'IEA23,VXEA22,\~EA2l,VMEA20, V:·1EA19 , v:.1EA18, •X. ,• X. ,•X. ,• X. ,•X. ,•X. ,•x. ,. X. , •X. ,• X. ,•X. ,•X. ,•x. ,. X. ,•X. ,•X. ,•X. ,•X.] <= "hFFFFF) II IVNEAS [. ISYSMI & IRA:164K & ([ VXEA23 , VMEA22, Vi1EA21 , V:1EA20, VHEA19, Vt1EA18, •x. , .x. ,. x. , .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X.,.X.,.X.) )= 0) & ([V:1EA23,~~!EA22,\~EA21, ~EA20,V:1EA19,~lEA18,.X.,.X.,.X.,.X.,.X.,.X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X.] <= "h3FFFF) 1/1V:IEAS & ~1ESELHIGH & «[MI5,N14,A:13,.X.,A..~l, A~O) == T1,l,l,.X.,l,O]) # ([ A:15 , A'-14 , A'O ,•X. ,1\.'1 1, N-1O ] == [1, 1, 1, •X. , 0 , 1) ) ) ; ILOCACCESS = !~IEAS & !SYSA:1 & ([~1EA23,VMEA22,VMEA21, v~EA20,W1EA19,V:1EA18,.X.,.X.,.X.,.X.,.X.,.X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X., .X.] )= "hBCOOOO) & ([WoIEA23, VMEA22 , VHEA21 , VHEA2D, VMEA19,VMEA18,.X.,.X.,.X.,.X.,.X.,.X.,.X.,.X., •X. ,•X. ,•X. ,•X. ,•X. ,•X. ,• X. ,•X. ,•x. ,.X.] <= "hBFFFFF); end of module ~lEADEC1 Page 1 ABEL(tm) Version 1.00 - Docunent Generator 26-Sep-84 ~1E ADDRESS DECODER 2 THE Kmax machine 68010 board Him v.d. Heuvel. University of Technology Eindhoven. department or Electrical Engineering Date: 20-August-1984 Equations for :-Iodule V:IEADEC2 Device P20 Original Equatio~s: ISELINSTRBUF = IIOACCESS & ([.X••• X•••X•••X.,.X.,.X., -V:·IEA09. V;IEA08, VtiEA07 ,•x. , .x.•.x. ,.x. ,VMEA02, V:·IEAOI,.X.] )= 0) & ([.X.,.X.,.X.,.X.,.X.,.X•• ~EA09,V:1EA08.V:1EA07••X•••X••• X•••X••V:1EA02, VAEA01 ••X.] <= Ah37F); I v:·mS"CLRA'-I ISTACCESS # ISELINSTRBUF l\T.'lESEUIEK = IIOACCESS & IOSO & 1~IEREAO & ([.X•••X•••X•• •X•••X••• X~.V:1EA09:V:1EA08.Y:IEA07•• X•••X•••X•• •X•• ~lEA02.~IEA01••X.] == Ah380); IVi1EVSE:l IIOACCESS & IOSO c. !VMEREAO & ([.X•••X.,.X•• •X•••X•••X•• VHEA09. Vi"IEA08. V:1EA07 , .X. " x. , .X. ,•x. , \T.'IEA02,V:·1EAOI ••X.] == "h382); !\~ESELS21 = !IOACCESS & IOSO & V:1EREAO & ([.X•••X.,.X., .x. ,•X. , .:C. V:'1EA09~v:iEA08. V:IEA07 ••X•••X•••x.• •X••VHEA02. 'V:IEAOI ••X.] =7 Ah382); ! PElI = (! STACCESS t.~! IOACCESS . if lREAOINTVEC_) & XACK_; !VHSSELOPIO = !IOACCESS & !OSO & «[.x.,.x•••x••• x•••x•• •X•• v:lEA09.~IEA08.~EA07••X•••x.•.x.•.X••v:lEA02. Y:IEAOI ••X.] == Ah380) & 1~IEREAD # ([.x•••x•••x.,.x.,.x.••X•• V:1EA09.~EA08. VHEA07).X.t.X·t·x.,.X.,~1EA02,~1EAOl,.X.]- Ah332)); end of module V:1EADEC2 Page 1 ABEL(tQ) Version 1.00 - Document Generator 26-Sep-34 DATA TRANSFER BUS HASTER THE KUNix machine 68010 board Wim v.d. Heuvel, University of Technology Eindhoven, department of Electrical Engineering nate: 20-August-1984 Equations for ~1odule DTBHASTER Device P21 Original Equations: ISTROBEDELO = !H\m & I;1HB & IEN'f.'1EDB_; ISTROREDELl = l!lWB & !:tHB & ISTROBEDELO_, ISTR03EDEL = !STROBEDEL1 & IMAS_; IDS10UT IUDS & ISTROBEDEL_; IDSOOUT !LDS & ISTROBEDEL_; IASOUT = !HAS & ISTROEEDEL fI !ASOUT & l'tAS & IUHB_; IENSTN·l = ISEL'P.-IEST & WHB_; IENIO~l ISEL~1EIO & !MHB_; end of module DT~lASTER Page 1 ABEL(tm) Version 1.00 - Docu~ent Generator 26-Sep-84 BUFFER CONTROL 1 THE KUNix machine 68010 board Wim v.d. Heuvel, University of Technology Eindhoven, department of Electrical Engineering Date: 20-August-1984 Equations for Module BUFCTRLI Device P22 Original Equations: ! BHO DB~'1 & PSEL & ! LDS II nIDi & !PSEL & !nSO II ! EN~'1E:'l D\{1L_; !BMI = DBH & PSEL & IUDS # D~l & !PSEL & !DSI II !EN:U::''1molLH_; ! E}MEi.'lDl~LL = ! RE~1E11DUR & ! BHO & PSEL & PSEN & !LDS II !REq1EHmiR & !&'10 & ! PSEL & PSEN & ! DSO II ! REqlEMDWR= & !ENME'lDWLL_; !ENHEHD\JLH = !RE~m'lmm & !BMI & PSEL & PSEN & IUDS II ! RE~lDlD~iR & !ml & !PSEL & PSEN & ! DSI # !REq1DiDHF-=: & ! E~'lEi'1mvLH_; !IVREAD !READI~ITVEC & !PSEL & PSEN & !DSO_, end of module BUFCTRLI Page 1 AREL(t1i1) Version 1.00 - Document Generator 26-Sep-84 BUFFEH. CONn.OL 2 & iliA CHANNEL 0, THE KUNix machine 68010 board \lim v.d. IIeuvel, University of Technology Eindhoven, department of Electrical Engineering Date: 20-August-1984 Equations for Module BUFCTRL2 Device P23 Original Equations: DIRLOCDB = (BGACKO & !LRD ff ! BGACKO & WiEREAD) & ENLOCDB II DIRLOCDB & !ENLOCDB_, DIRvaEDB (lHHB &! LRD fl ~1HB- & WIEREAD) & EN~1EDB II DIR~1EDB & !ENLOCDB_; STBBERREG = LAS & !BERR II! EDCUFATIRQ_ II !EDCUCORIRQ_; !BRO = !LOCACCESS & BGACKO_; !BGACKO = !LOCACCESS & (!BGO_ # !BGACKO_); ! BERRIf.H: end of module 3UFCTRL2 Page 1 ABEL(tn) Version 1.00 - DocuQcnt Generator 26-Sep-84 BUFFER CONTROL STATE :-lACHI,m THE KUNix machine 68010 board \Jim v.d. Heuvel, University of Technology Eindhoven, department of Electrical Engineering Date: 20-August-1984 Equations for Ylodule BUFCTRL3 Device P24 Original Equations: RENLC>.CDB := ([PO,Pl,P2,P3,P4,PSJ == [1,1,1,1,1,1]) & PSEL & PSEN & ISELlLo\}l & l~lAS & LRD # ([PO,Pl,P2,P3,P4,PSJ =~ [1,1,1,1,1,1]) & PSEL & PSEN & ISELSEH & l~lAS & LRD # ([PO,Pl,P2,P3,P4,PS] == [1,1,1,1,1,1]) & IMH3 & !MAS & LRD II ([PO,Pl,P2-;P3,P4,PS] == [1,1,1,1,1,1]) & ! LOCACCESS & I BGACf~O & v: l[READ U ([PO,Pl,P2,P3,P4,psT == [1,1,1,1,1,1]) & PSEL & PSEN & !SELMa & !:tAS & ILRD # ([PO,Pl,P2,P3,P4,PS] == [1,1,0,1,1,0]) # ([PO,Pl,P2,P3,P4,PS] -- [1,1,1,1,1,1]) & !)1HI3 & l.'lAS & I LRD # ([PO,P1,P2-;P3,P4,PS] == [1,1,1,0,0,1]) & LOCDATASTB & l~mH & I LRD q ([PO,Pl,P2,P3,P4,PS] == [1,1,1,1,1,1]) & ILOCACCESS & I~GACKO & I~EREAD # ([PO,P1,P2,P3,P4,psT == [1,1,1,0,1,0}) & IV:1EDATASTB & ILOCACCESS & Iv:1E~~EAD; ENLOCDB := «[PO,Pl,P2,P3,P4,PS) == [1,1,1,1,1,0]) # ([PO,Pl,P2,P3,P4,PS] == [1,1,1,1,0,1])) & C'lAS {I IPSEN) # «[PO,Pl,P2,P3,P4,PS) == [1,0,1,0,0,1]) # ([PO,Pl,P2,P3,P4,PS] == [1,0,0,0,0,1])) & MAS # «[PO,Pl,P2,P3,P4,PS] == [0,0,1,0,1,0]) # ([PO,Pl,P2,P3,P4,PS] == [0,0,0,0,1,0})) & (LOCACCESS # BGACKO )- # ([PO,Pl,P2,P3,P4,PS] -- [1,0,1,0,0,1}) & ILOCDATASTB & IMAS # ([PO,Pl,P2,P3,P4-;PS] -- [0,0,1,0,1,0]) & WIEDATASTB & !LOCACCESS # ([PO,Pl,P2,P3,P4,PS] =~ [1,1,0,1,0,0]) & IPSEN; REN~lEDB := ([PO,Pl,P2,P3,P4,PS) == [1,1,1,1,1,1]) & !PSEL & PSEN & ISELP~l & V.1EREAD # ([PO,Pl,P2,P3,P4,PS] == [1,1,1,1,1,1}) & IPSEL & PSEN & ISELSfl1 & W1EREAD # ([PO,Pl,P2,P3,P4,PSJ-== [1,1,1,1,1,1}) & IPSEL & PSEN & IIVREAD & v.-1EREAD # ([PO,Pl,P2,P3,P4,PS]-== [1,1,1,1,1,1]) & Page 2 AllEL(tm) Version 1.00 - Document Generator 26-Sep-84 BUFFER CO:.lTROL STATE HACHHlE THE KU~ix machine 68010 board \-liUl v.d. Heuvel, University of Technology Eindhoven, departr.lent of Electrical Engineering Date: 20-August-1984 Equations for :lodule BUFCTRL3 Device p24 !MHll & !MAS & LRD # ([PO,Pl,P2:P3,P4.PS] == [1.1.1.1.1.1]) & !LOC~CCESS & !BGACKO & W1EREAD U ([PO,Pl.P2,P3.P4,psT == [1.1.1.1.1,1]) & ! PSEL & PSEU & !SELRM-l & ! VMEREAD II ([PO,Pl,P2,P3,P4,P5] == [0,1,0,1,1,0]) # ([PO.Pl.P2,P3.P4.PS] [1,1.1,1.1.1]) & !~lHB & !)lAS & !LIm # ([PO.Pl,P2:P3.P4.PS] == [1,1.1.0,0.1]) & LOCDATASTB & !HHll & !LRD # ([PO.Pl,P2.P3.P4.PS] == [1.1.1.1.1,1]) & !LOCACCESS & !BGACKO & !W1EREAD # ([PO,Pl,P2,P3,P4,psT == [1,1,1,0,1,0]) & !~lEDATASTB & !LOCACCESS & !VMEREAD; ENVi-lEDB := (([PO,Pl,P2,P3,P4,PS] == [0,1,1,1,1,0]) # ([PO,Pl,P2.P3,P4,PS] [0.1,1,1.0,1]) # ([PO,Pl,P2,P3,P4,PS] -- [0,1,1,0,1,1]) # ([PO,Pl,P2,P3,P4,PS] -- [0,0,1,0,1,0]» & V:·IEDATASTB # (([PO,Pl:P2,P3,P4,PS} == [1,0,1.0,0,1]) # ([PO,Pl,P2.P3,P4.PS] == [1.0,0,0,0,1]» & HAS # ([PO,Pl,P2,P3,P4,PS] -- [0,1,0,1,0,0]) & IPSEN # (([PO,Pl,P2,P3,P4,PS] == [0,0,1,0,1,0]) # ([PO,Pl,P2,P3,P4,PS] == [0,0,0,0,1,0]» & (LOCACCESS II BGACKO )- # ([PO,Pl,P2,P3,P4,PS] == [1,0,1,0,0,1]) & !LOCDATASTll & !~AS_; RENIVREG := ([PO,Pl,P2,P3,P4,PS] == [1,1,1,1,1,1]) & !PSEL & PSEN & IIVREAD & ~1EREAD; ENIVREG := ([PO,Pl,P2,P3,P4,PS] == [0,1,1,0,1,1]) & VHEDATASTll_; . RVSB·l := ([PO,Pl,P2,P3,P4,PS] == [1,1,1,1,1,1]) & (PSEL & PSEN & !VS~1REQ & IMAS & ILRD II !PSEL & PSEN &" !VSEMREQ_ & IVHEREAD) ; VS~1 := ([PO,Pl,P2,P3,P4,PS] == [1,1,0,1,0,1]) & IPSEN; RENS~lREG := ([PO,Pl,P2,P3,P4,PS] == [1,1,1,1;1,1]) & (PSEL & PSEN & !SELS~l & !MAS & LRD Page 3 AHEL(tm) Version 1.00 - DOCllr.1ent Generator 26-Sep-84 BUFFEI~ CmiTROL STATE :lACur:;[ THE :~max machine 6R010 board (Hr.l v.d. ileuvel. Universitj' of Technology Eindhoven. departl'lent of Electrical Engineering flate: 20-August-1984 Equations for ~odule 3UfCTRL3 Device P24 II !PSEL & PSE~; & ! SELSE!! & vrlEREAD); E:~SEm.EG := ([PO.P1.P2.P3.P4.PS] -- [1.1.1.1.0.1]) & (MAS_ 11 !PSE~) 1 ([PO.P1.P2.P3.P4.PS) == [0.1.1.1.0.1]) & V.·lEDATASTB_; RREQ:IE.:1D\lP,-:= ([PO.P1.P2.P3.P4.PS] -- [1.1.1.1.1.1]) & (PSEL & PSEil & !SELRRI & !:lAS &ILRD II !PSEL & PSE~ & !SEL~l & !~EREAD) # ([PO.P1.P2.P3.P4.P5] [1.1.0.1.1,0]) # ([PO,P1,P2,P3,P4,P5] == [0,1,0,1,1,0]); REQ:·l2'W\,fP,-:= «[PO,P1,P2,P3,P4,P5] [1.1,0,1,0,0]) II ([PO,P1,P2,P3,P4,PS] [0,1,0,1,0,0])) & ! PSE;~; RD::1E:·1JRL := ([PO,P1,P2,P3,P4,P5] == [1,1,1,1,1,1]) & (PSEL & PSEN & I SEUL~l & !MAS & LRD /1 !?SEL & PSEN & !SELRAH & v,'lEREAD); EN"·mmRL := ([PO,P1,P2,P3,P4,P5] == [1,1,1,1,1,0]) & (HAS_ # ! PSE~l) # ([PO t Pl,P2,P3,P4,P5] == [0,1,1,1,1,0]) & V:·IEDATASTB_; P~STB{1E:1D\.J.L := «[PO,Pl,P2,P3,P4,P5] == [1,1,0,1,1,0]) # ([PO,P1,P2,P3,P4,P5] [0,1,0,1,1,0])) ; ST~lE'ID\fL := «[PO,P1.P2,P3,P4,P5] == [1,1,0,1,0,0]) it ([PO.P1,P2,P3,P4,PS} == [0.1,0,1,0,0])) & IPSEN; RPO := ([PO,Pl,P2,P3,P4,PS] == [1.1,1,1,1,1]) & (!PSEL & PSEN &! SELl-WI & V:1EREAD # !PSEL & PSEN-& !SELSDl & VMEREAD II !PSEL & PSEN &II VREAD- 5. VMEREAD it !PSEL & PSEN & ISELRNC & !Vi-lEREAD it !LOCACCESS & IBGACKO -& ~lEREAD # !LOCACCESS- & !llGACKO- & !VMEREAD) II ([PO,P1,P2:P3,P4,PS} ~= [0,1,0.1,1,0]) Page 4 ABEL(to) Version 1.00 - Document Generator 26-Sep-84 BUFFSR COilTROL STATE HACHINE THE KUNix machine 68010 board Wim v.d. Heuvel. University of Technology Eindhoven. departoent of Electrical Engineering Date: 20-August-19n4 Equations for ~odule 3VFCTRL3 Device P24 # ([PO.P1.P2.P3.P4.P5j == [1,1.1.0,1.0]) & IV.,lEDATASTB & !LOCACCESS & !VHEREAD; PO := «[PO.P1.P2.P3,P4.P5] == [0.1.1.1,1,0]) # ([PO,P1.P2.P3.P4.P5] [0,1,1.1,0.1]) # ([PO.Pl.P2,P3,P4,PSJ == [O,l,I,O,I,l]) # ([PO.Pl,P2.P3.P4,P5] [0.0.1.0,1.0]» & v:-mDATASTB # «[PO.Pl~P2.P3.P4.P5] -- [0.0.1.0,1.0]) # ([PO.Pl.P2.P3.P4.P5] -- [0,0.0,0.1,0]» & (LOCACCESS !I BGACKO )- # ([PO,Pl.P2.P3.P4.P5] [0,1.0.1.0.0]) & IPSEN; RP1 .- ([PO.Pl,P2.P3.P4.P5] -- [l,1.1,1.1,1)) & (n1HB_ & !HAS & LRD II !~ClB & mAS & ! LRD I.f !LOCACCESS &! BGACKO & VHEREAD ;I !LOCACCESS- & !BGACKO- & !VHEREAD) # ([PO,Pl,P2~P3.P4.P5] -- [1,1.1.0.0.1]) & LOCDATASTB [, !~lI!B & ! LRD # ([PO~P1,P2.P3.P4.P5] -- [1,1.1.0.1.0]) & !V1EDATAST3 & !LOCACCESS & !\~EREAD; PI := «[PO.Pl.P2,P3.P4.P5] == [1.0,1.0,0.1]) 3 ([PO,Pl,P2,P3.P4.P5] == [1,0.0.0.0.1]» & MAS # «[PO,Pl.P2.P3.p4.P5] == [0.0.1.0.1,0]) # ([PO,Pl.P2,P3.P4,P5] == [O,O.O,O,l,OJ» & (LOCACCESS It BGACKO )- # ([PO.Pl.P2.P3,P4,P5J -- [O,O,l,O.l,OJ) [, ~lEDATASTB & !LOCACCESS # ([PO.Pl.P2~P3,P4.P5] == [l,O,l,O.O,lJ) & !LOCDATASTB & !t1AS_; RP2 := ([PO.Pl.P2,P3.P4,P5] == [1.1,1,1.1,1]) & (PSEL & PSEN & !VSEMREQ & !MAS & !LRD 1/ 1PSEL & PSEN &" !VSEMREQ & 1VI-IEREAD # PSEL & PSEN & lSELRNI &" lMAS & !LRD # !PSEL & PSEN & !SELRA~ & lVMEREAD # !MHB & !MAS & ILRD 11 !LOCACCESS &" !BGACKO & !VMEREAD) # ([PO.P1,P2~P3,P4,P5] == [1,1,0.1,1,0]) # ([PO.Pl.P2.P3,P4.P5] == [0.1.0,1.1,0]) # ([PO.P1.P2.P3.P4,P5] -- [1.1,1,0.0.1]) & LOCDATASTB & !~lHB &! LRD Page 5 ABEL(tm) Version 1.00 - Document Generator 26-Sep-84 BUFFER CONTROL STATE >{ACHI~E THE KUNix machine 68010 board Wim v.d. Heuvel. University of Technology Eindhoven. department of Electrical Engineering Date: 20-August-1984 Equations for :1odule BUFCTRL3 Device P24 It ([PO.Pl.P2.P3.P4.PS] == [1.1.1.0.1,0]) & !Vt1EDATA::'fH & !LOCACCESS & !VMEREADj P2 := ([PO,Pl,P2,P3,P4.PS] == [1,1,0,1,0,1]) & !PSEN' # ([PO.Pl,P2,P3,P4,PS] == [1,1,0,1,0,0]) & IPSEN # ([PO,Pl,P2,P3,P4,PS} [0,1,0,1,0,0]) & IPSEN # ([PO,Pl,P2,P3,P4,PS] -- [1,0,0,0,0,1]) & MAS # ([PO,Pl,P2,P3,P4,PS] [0,0,0,0,1,0]) & (LOCACCESS_ /1 BGACKO_) ; RP3 := ([PO,Pl,P2,P3,P4,PS] == [1,1,1,1,1,1]) & (IPSEL & PSEN & ! IVREAD & V>1EREAD il !ItHB & !MAS- & LRD II UHB- & !MAS- & ! LRD # !LOCACCESS & !BGACKO & ~1EREAD if !LOCACCESS- & !BGACKO-" I ~tEREAD) # ([PO,Pl,P2~P3,P4,PS] ~= [1,0,1,0,0,1]) & !LOCDATIISTB " !HIIS # ([PO,Pl,P2,P3,P4~PS] [0,0,1,0,1,0]) & ~1EDATASTB & !LOCACCESS # ([PO,Pl,P2,P3,P4,P5] -- [1,1,1,0,0,1]) & LOCDATASTB & !t1HB & I LRD II ([PO~Pl,P2,P3,P4,PS] == [1,1,1,0,1,0]) & !VHEDATASTB & ILOCACCESS &!Vt-tEREADj P3 := ([PO,Pl,P2,P3,P4,PS] == [0,1,1,0,1,1]) & ~tEDATASTB # «[PO,Pl,P2,P3,P4,PS] == [1,0,1,0,0,1]) # ([PO,Pl,P2,P3,P4,PS] == [1,1,1,0,0,1]) # ([PO,Pl,P2,P3,P4,PS] == [1,0,0,0,0,1])) & MAS # «[PO,Pl,P2,P3,P4,PS] == (0,0,1,0,1,0]) # ([PO,Pl,P2,P3,P4,PS] -- [1,1,1,0,1,0]) # ([PO,Pl,P2,P3,P4,P5] == [0,0,0,0,1,0])) & (LOCACCESS II BGACKO_); RP4 := ([PO,Pl,P2,P3,P4,P5] == [1,1,1,1,1,1]) & (PSEL & PSEN & !SELSEM & !MAS & LRD # !PSEL & PSEN-& !SELSfl1 & VMEREAD II PSEL & PSEN & !VSEHREQ- & !MAS & !LRD # !PSEL & PSEN & !VSEMREQ & !VMEREAD # !tinB & !!-lAS & LRD - /I l:1HB- & mAS- & !LRD) # ([PO~Pl,P2,P3,P4,PS] -- [1,0,1,0,0,1]) & !LOCDATASTB & lHAS # «(PO,P1,P2,P3,P4~PS] == [1,1,0,1,1,0]) Page 6 ABEL(tm) Version 1.00 - Document Generator 26-Sep-84 BUFFER CONTROL STATE MACHINE THE KUNix m~achine 68010 board Wim v.d. Heuvel, University of Technology Eindhoven, departraent of Electrical Engineering Date: 20-August-1984 Equations for Module BUFCTRL3 Device P24 # ([pO,r1,p2,p3,P4,PS] - [0,1,0,1,1,0]) II ([PO,P1,P2,P3,P4,PS] [1,1,1,0,0,1]) & LOCDATASTB & !)tHB & ! LRD; P4 := ([PO,P1,P2,P3,P4,PSJ == [1,1,1,1,0,1]) & (MAS_ 1/ IPSEN) II ([PO,P1,P2,P3,P4,PS] -- [0,1,1,1,0,1]) & VMEDATASTB # ([PO,P1,P2,P3,P4,PS] [1,1,0,1,0,1]) & IPSEN 1/ «[PO,P1,P2,P3,P4,PSJ == [1,0,1,0,0,1]) fr ([PO,P1,P2,P3,P4,PS] == [1,1,1,0,0,1]) II ([PO,Pl,P2,P3,P4,PS] == [1,0,0,0,0,1])) & MAS 1/ «[PO,P1,P2,P3,P4,PS] == [1,1,0,1,0,OJ) 1/ ([PO,P1,P2,P3,P4,PS] == [0,1,0,1,0,0])) & IPSEN; RPS := ([PO,P1,P2,P3,P4,PS] == [1,1,1,1,1,1]) & (PSEL & PSEN & ! SELlWl & !~lAS & LRD II !PSEL & PSEN-& !SELP~~ & VMEREAD 1/ !LOCACCESS & ! BGACKO & ~'lEREAD It PSEL & PSEN & ! SELRAtl- & !HAS & !LRD 1/ !PSEL & PSEN & !SEL~l & !~lEREAD i! !LOCACCESS &! BGACKO & !VaEREAD) If ([PO,P1,P2~P3,P4,PSJ ~- [0,0,1,0,1,0]) & !LOCACCESS & ~1EDATASTB II ([PO,P1,P2,P3,P4,PS] == [1,1,0,1,1,0]) 1/ ([PO,P1,P2,P3,P4,PS] -- [0,1,0,1,1,0]) II ([PO,P1,P2,P3,P4,PS] == [1,1,1,0,1,0]) & !V.1EDATASTB & !LOCACCESS & !~lEP~AD; PS := ([PO,P1,P2,P3,P4,PS] -- [1,1,1,1,1,0]) & (HAS_ tt !PSEN) 1/ ([PO,P1,P2,P3,P4,PS] == [0,1,1,1,1,0]) & VMEDATASTB II «[PO,P1,P2,P3,P4,PS] == [0,0,1,0,1,0]) II ([PO,P1,P2,PJ,P4,PS] == [1,1,1,0,1,0]) II ([PO,P1,PZ,P3,P4,P5] == [0,0,0,0,1,0])) & (LOCACCESS II BGACKO )- # «[PO,P1,P2,P3,P4,P5] == [1,1,0,1,0,0]) II ([PO,P1,P2,P3,P4,P5] == [0,1,0,1,0,0])) & IPSEN; end of module BUFCTRL3 APPENDIX C TIMING DIAGRAMS PAGE 117 i , I'! L L Ie ¢ [1-,1;. I C L /r. /LH5 / ,L t:l n 5 '11¢ 1111 ZI L '1//7 71 1t111S , L iii i l 1.-1.0 I I 'r---r---..,..-~_--t-----,. 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DATI} J...... ------I-- V;1tPl1rl1 , Vt1 t " Rl ;- E c. Vc {.. E. r- () I.- D C. II L nf,f> APPENDIX D LOCAL ADDRESS MAP PAGE 125 1) 099-097 data, 098-015 undefined. Access to even byte only causes TIME-OUT PAGE 126 APPENDIX E VHE ADDRESS HAP PAGE 127 E99999 E3FFFF RAM system14 64k chips E99999 EFFFFF RAM system14 256k chips F99999 F3FFFF RAM system15 64k chips F99999 FFFFFF RAM system15 256k chips The above map shows that the system number (SN) determines the off-set of the 68919's on-board memory in the VHE standard address space. PAGE 128 VME address map: I/O address modifier BYTE ADDRESS DEVICE / DATA BUS REMARK SYSTEM VALID DATA FROM TO NUHBER 4999 437F BUFFER /9 015 - 099 instructions 4389 4381 WAKE-UP /9 write only 4382 4383 SEMAPHORE/9 099 read/write 4499 477F BUFFER /1 015 - 099 instructions 4789 4781 WAKE-UP /1 write only 4782 4783 SEMAPHORE/1 099 read/write 4899 487F BUFFER /2 015 - 099 instructions 4B89 4B81 WAKE-UP /2 write only 4882 4B83 SEMAPHORE/2 099 read/write 7C99 7F7F BUFFER /15 015 - 099 instructions 7F89 7F81 WAKE-UP /15 write only 7F82 7F83 SEMAPHORE/15 099 read/write 8999 837F BUFFER /16 015 - 099 instructions 8389 8381 WAKE-UP /16 write only 8382 8383 SEMAPHORE/16 099 read/write BC99 BF7F BUFFER /31 015 - 099 instructions BF89 BF81 WAKE-UP /31 write only BF82 BF83 SEMAPHORE/31 099 read/write System numbers 9-15 are 68919 systems, 16-31 are I/O systems (186). Both semaphore and wake-up register must have DS9 asserted for access to them. Use of word transfers is prefered. PAGE 129 1) 088-087 data, 088-015 undefined. Access to even byte only causes TIME-OUT The system address modifier that creates this address map is the user definable address modifier (81xxxx) with the lower four bits equal to the system number (SN). The above map is only valid for 68818 systems. PAGE 138 APPENDIX F STRAP USAGE PAGE 131 ROM and RAM size selection (STR1) USED DEVICE CONNECT STRAP 1 PIN TO PIN 641'. chip RAM 2 1 2561'. chip RAM 4 3 2732 ROM 6 5 2764 ROM 14 13 10 9 27128 ROM 16 15 10 . 9 8 7 27256 ROM 18 17 10 9 8 7 27512 ROM 20 19 12 11 8 7 PAGE 132 Bus requester level selection (STR2) LEVEL CCtf'o,IECT STRAP 2 PIN TO PIN 9 26 25 16 15 14 13 1 24 23 12 1 1 10 9 2 22 21 8 7 6 5 3 29 19 4 3 2 1 PAGE 133 APPENDIX G ERROR REGISTER BIT SPECIFICATION PAGE 134 Error register bit list BIT SIGNAL REMARK 8 /EDCUCORIRQ 8= non-fatal memory error 1 MHB 1= VME bus cycle 2 /BGACK 8= DMA cycle 3 /EDCUFATIRQ 8= fatal memory error 4 /SELNOP 8= address error 5 /BERRTIM 8= time-out 6 /BERR\JME 8= bus error from VME 7 /BERRMMU 8= page fault MMU a /CAS8 8= banK 8 selected 9 /CAS1 8= banK 1 selected 18 cbo8 syndrome bi t 8 11 cbo1 syndrome bit 1 12 cbo2 syndrome bi t 2 13 cbo3 syndrome bi t 3 14 cbo4 syndrome bit 4 15 cbo5 syndrome bi t 5 PAGE 135 APPENDIX H LOCAL BUS EXTENSION SPECIFICATION PAGE 136 Local bus extension specification SIGNAL PIN REMARK A91-A23 A39-A24, LOCAL ADDRESS BUS C39-C1S OF 68919 LOCD99- A91-A98, LOCAL DATA BUS LOCD1S C91-C98 OF 68919 /CLK A19 INVERSE OF 68919 CLOCK /UDS A12 UPPER DATA STROBE /LDS A13 LOWER DATA STROBE LRD A14 READ / WRITE OF 68919 /DTACK A16 DATA TRANSFER ACKNOWLEDGE /MAS A18 MEMORY ADDRESS STROBE /CA A21 CHANNEL ATTENTION TO NETWORK CONTROLLER /BGACKl A22 BUS GRANT ACKNOWLEDGE FROM ~ DEVI CE ON THE EXTENSION BUS /NWCIRQ A23 INTERRUPT REQUEST FROM MASTER DEVI CE ON EXTENSION BUS (DAISY CHAIN) /NWCIACK " C19 INTERRUPT ACKNOWLEDGE TO EXTENSION BUS (DAI SY CHAIN) /J2EDCUBERR ell BUS ERROR FROM EXTENSION BUS, FATAL MEMORY ERROR ONLY /RESET C12 MEMORY RESET /BRl C13 BUS REQUEST FROM NETWORK /BGl C14 BUS GRANT TO NETWORK -12V A31 12 VOLT NEGATIVE POWER SUPPLY +12V C31 12 VOLT POSITIVE POWER SUPPLY Vcc A32,C32, 5 VOLT POWER SUPPLY All pin numbers are for VHE connector -J2-. PAGE 137 APPEJ\IDIX I BAUDRATE PROGRAMMING PAGE 138 Baudrate progr~ing BAUORATE OIVISIOt'II FACTOR (Hz) 19299 256 9699 512 4899 1924 2499 2948 1299 4996 699 8192 399 16384 159 32768 75 65536 PAGE 139 I 010 W \~ ::J , < " Ii \ :t U l) U U w < > 'I e '" z '"w'" Ii \ II .J '"01 U'" Q I \ E - " ro~ .. ~ (l' t-l%~ a: .J.J.J ~ -l-