EE1009 Load Board Design REPRINT.Indd

LOAD BOARD DESIGN

Designing the Optimal Board for IC Testing by Jeff Sherry, P.E., Johnstech International

Designing a load board or circuit board for IC be measured across a wide bandwidth, consistent testing sounds like a routine task that involves a performance across a broad frequency range is few basic requirements and some common-sense crucial for accurate signal reproduction. approaches. But it’s not always that simple. With Be sure to consider the proper substrate thick- new technologies and increasingly complex de- ness. This is important in determining the geometry Dsign requirements, there now are more issues than of the rest of the load board because the distances ever to consider in optimizing a load board. from the ground plane or planes will affect the im- Some factors, like substrate material selec- pedance of the signal line. Standard high-frequency tion, are fundamental. Others differ with spe- materials are only stocked in 5-, 8-, 10-, 15-, 20-, cific designs, including board layout; component 32-, and 64-mil thicknesses. Usually, 4 mils is the placement; the number, placement, and size of thinnest available substrate material. vias; load board grounding; and pad sizes. These Figure 1 shows the E-fields of a Johnstech 0.5-mm pitch Pad ROL™ 200 Contactor with the load board laid out to accommodate both the ROL 200 technology and soldering of the device to the board. As shown in the figure, the E-fields are very large on the load board trace beyond the contact/load board interface point, and the edges of the contact also have fairly high E-field radiation. Sharp corners on the trace stub have higher E- field concentrations so it is best to radius edges and reduce the stub lengths. The E-fields on the left side of the model are reduced in magnitude primarily due to a cutout in the housing above the traces. The top right side of the model (the green box) is the DUT. Many load boards are designed to test parts on Figure 1. High-Frequency Structure Simulator 3-D E-Field Model of a Contactor/Load Board Interface the production floor in a removable contactor. Often, the load board/contactor system is com- factors all help minimize crosstalk. Many times, pared with the process of directly soldering parts modeling ties all of these components together to boards to calibrate out extra losses. to determine if the electrical performance will be Whenever a test contactor is used, it will met before the board is fabricated. increase the amount of ground inductance because the device will come to rest some distance Substrate Material Selection above the load board. For that reason, it is vital Choosing the correct substrate material is to design the load board with lower ground in- critical for good load board design. The most ductance than is needed to make sure you still important individual electrical parameters are a can test parts to specifications in production low dielectric constant and a low dissipation fac- and that extra parameters or losses due to the tor or loss tangent. Also, if the system is going to contactor don’t affect yields. LOAD BOARD DESIGN

In cases where the system is repeat- ponent placement. Using a universal its performance, especially at elevated able, these extra losses can be cali- arrangement allows a specific contac- frequencies or at gains above 30 dB. brated out. If the gain of an amplifier tor to accommodate several different Figure 2 shows a typical board lay- is measured, the amount of lost gain types of packaged devices. out with via structures. Placing ground is affected by how low the ground The placement of tuning elements traces that are periodically attached to inductance is in the test contactor. closely follows the criteria outlined a load board ground plane is the best for the placement of decoupling com- way to isolate two signal traces and Board Layout ponents. Elements comprising phase- improve board isolation or crosstalk. Typically, when laying out a load locked loops (PLLs) are particularly This model shows a GSSG configura- board, it is better not to introduce any sensitive to noise. tion, which usually is best for routing stubs that will act as antennas and A common practice with high- high-frequency signals. degrade the performance. This often speed digital devices is to embed There are two basic types of vias: occurs when the board is laid out for all the elements of the clock recov- standard and micro. The design choice two different technologies or when ery PLL internal to the chip itself. depends on factors such as frequency devices are soldered to the board in However, the capacitors that set the of operation, trace density, parasitics, addition to testing with a contactor. corner of the low-pass filter of the and economics and includes a basic Solder mask should be removed loop are external to the device. They trade-off between density and cost. from the area under the contactor to are placed on the load board. If a via is used for mounting a com- make sure it sits flat and the devices For optimum performance, these ponent, then it must be large enough are presented in a coplanar fashion. capacitors must be located directly to accommodate the lead of the com- This provides the added benefit adjacent to the terminals to which they ponent with adequate allowance for of increased contact and contactor belong. Since they are susceptible to plating buildup and solder. Small via life. If it is necessary to run parallel noise pickup, they must be shielded holes require small drill bits, and laser traces, it’s best to route signals in using a guard-ring trace around these systems are used for vias that are less differential format ground-signal- capacitors on the PCB or load board. than 4 mils in diameter. signal-ground (GSSG) to reduce the The drill bits used for these small susceptibility to noise. Vias holes are more prone to breaking than Using screw-on connectors for high- The number, placement, and size of big drill bits, adding to the fabrication frequency RF signals also can improve vias are important considerations in a costs of the load board. Also, small bits performance. The best performance successful load board design because wander off center, a characteristic that comes when the connectors are in vias route signals between layers and increases production costs since boards line rather than vertical through the act as vertical shields between traces. A must be drilled in small batches. board. Any posts on the connectors, via hole is a location in a PCB used for Microvias, which are made by pho- both grounds and signals, should be either mounting a through-hole com- toimaging, laser ablation, or plasma flush to prevent any unwanted stubs ponent or routing traces between lay- etching, generally are used in very high and degraded performance. ers. Since vias typically carry electrical trace density designs. Microvias can signals or currents, they are plated for be 2 mils or smaller. Accordingly, the Component Placement continuity. Vias can serve as a path to density of pads can increase fourfold. Ideally, decoupling components ground from traces on one layer of a Microvias also can be placed directly are located right behind the contactor PCB to the ground plane. in pads, creating even more space contacts they are meant to decouple. savings over standard vias. This is particularly important at high Via hole diameter depends on the frequencies. If this is not done, the thickness of the PCB or load board. decoupling can actually exacerbate the Standards have been established and situation because the length of circuit documented for this purpose includ- trace or wire between the target contact ing MIL-STD-275E, which lists the and its decoupler acts as an antenna. acceptable hole diameter for a stand- This allows noise to enter or exit the ard via as T/4 where T is the board circuit. This same length of circuit Figure 2. Typical Board Layout and Via Structure thickness. trace or wire can form a resonant cir- In most instances, vias are the most The more vias between the top layer cuit with the decoupling components direct path to ground. In high-speed ground traces and the ground plane, and cause sporadic oscillations. digital and RF designs, ground paths the lower the effective ground induc- Since it is desirable to have the must be short and direct to avoid in- tance and the better performance. decoupling components located right troducing extraneous noise into the Typically, the lower the loss tangent, behind the contact they are to decouple, circuitry. In many cases, boards have the less loss occurs in the substrate. the frame of the contactor may need to an insufficient number of vias to ad- A low dielectric constant and a hard be modified for the decoupling com- equately test a part without impacting substrate are important for high-fre- LOAD BOARD DESIGN

0 Layout A 1.50 -5 0.75

-10 0.35

-15 NOMINAL POINT OF CONTACT -20 Layout B 2.30 -25 1.15

-30 0.35 Return Loss (dB) Loss Return -35 NOMINAL POINT OF CONTACT -40 0.5-mm Pitch ROL200 Contact With Layout A - Modeled GSG Data Layout C 0.5-mm Pitch ROL200 Contact With Layout B - Modeled GSG Data 0.500 -45 0.20 0.5-mm Pitch ROL200 Contact With Layout C - Modeled GSG Data FULL R -50 0.35 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Frequency (GHz) NOMINAL POINT OF CONTACT Figure 3. Effects of Load Board Pad Stubs on RF Return Loss quency testing in production. The RF can be more than 20 dB at lower fre- trace widths that are 50 Ω and that or sensitive traces usually are on the quencies and at least 10 dB at higher support the contact and land on perimeter of the package so it is best frequencies. pads that don’t create stub effects. to route them on the top layer of the Guidelines for load board ground- The return loss degrades rapidly the substrate to reduce losses. These will ing optimization include the follow- larger the stub becomes beyond the be either microstrip line structures or ing: contact and load board interface. coplanar waveguide structures. • The length and area of the ground Large board mismatches and stubs Typically, the impedance of the path are very important to match the create mismatch losses that will DUT will be 50 Ω, matching the test DUT. affect the insertion loss of the sys- equipment. To get the largest band- • Ground inductance should be mini- tem, creating changes in measured width, the contactor and load board mized to optimize higher frequency gains of amplifiers or other active also should be designed for 50 Ω to performance. components. prevent mismatch errors. If matching • Ground resistance should be low to If insertion loss bandwidth is speci- is done on the load board for a par- minimize power supply voltage drop. fied as the 1-dB loss point, the pad that ticular frequency of test with lumped • Grounding via fences controls cross- is longer than needed can create a large elements, the performance generally talk between signals by creating a wall stub, decreasing the 1-dB bandwidth will be worse if you use a different between signal lines. by almost three times compared with contactor technology. an optimum pad with a very small Pad Size and Shape stub. For this modeled system, the Load Board Grounding Both the pad size and shape affect bandwidth is 37 GHz for the optimum Increasing the number of paths to the reflections and radiations and con- pad layout and only 14+ GHz for the ground also reduces the ground in- sequently the bandwidth. As a simple pad that would allow soldering the ductance and tends to increase the example, three pad layouts were cho- device to the load board. The trace bandwidth of the system. Positioning sen to calculate the effects. In Figure width doesn’t affect the response much vias periodically about 1/20 wave- 3, Layout B is the largest pad with as long as the width is designed to be length apart between the ground pad or square corners, Layout A is slightly close to 50 Ω. trace and the ground plane effectively smaller, and Layout C is smaller yet places a shield box around the signal and with rounded corners. Using the Minimizing Crosstalk trace. The higher the frequency of the 15-dB point to define the bandwidth When routing high-frequency traces signal trace, the closer the vias need from the return loss yields 4, 7, and on the load board, it is vital to note that to be to control crosstalk. 24 GHz, respectively, for Layouts B, right angles tend to radiate more energy Isolation and crosstalk can be miti- A, and C. because signals propagate in straight gated by simply placing a ground trace This suggests some rules for board lines. Changes in line width result in between two signals. The improvement layout around the contactor: pick changes in impedance and cause reflec- LOAD BOARD DESIGN

tions. Placing a ground trace between ger traces run side by side, the more In conclusion, many factors play high-frequency lines creates a barrier crosstalk. into designing a load board that will so signals remain confined. • If parallel traces cannot be eliminated, result in an effective test of the DUT. Placing a via fence like the one route the signal as a differential pair. Neglecting just one of the factors, shown in Figure 2 further prevents such as substrate thickness and mate- unwanted signals from appearing Electrical Performance Model rial selection, via placement, signal on adjacent traces. Clock lines have Modeling typically is used in the routing, or grounding, can result in higher frequencies, and good clock design phase to determine the system redesigning the load board. Modeling, edges require the 3rd and 5th harmon- performance and usually includes all if done correctly, will tie everything ics. Decoupling components should the system parts: load board, contactor, together. Accurate models that pre- be located close to the device. For and device. Modeling helps predict dict performance will identify issues best contactor performance, match the performance. If done properly, it of- early and often result in a successful trace impedance to the device. ten results in the correct design of a first design.

A Few Basic Tricks of the Trade • Provide Relief in the Housing Above Traces to Reduce ground plane with vias reduces the size of the ground loop Impedance Changes and improves the crosstalk between signal lines. Since housing material has a higher dielectric constant • Proximity to Ground Plane Affects Trace than air, if the housing rests on the trace, it will lower the Impedance impedance. The amount of reduction depends on the A 50-Ω line on the edge of the board might become a dielectric constant of the material and the configuration of much lower impedance as the traces get close to each other, the load board. For best performance, make sure there is a the device, or the ground plane. The closer the traces are relief in the housing although reducing the trace width where to the ground plane or ground traces, the more it tends to the housing rests could help in returning the impedance lower the impedance. back to 50 Ω. • Shorten the Ground Path to Lower Ground • Route Parallel Traces in a Differential Configuration Inductance to Reduce Signal Degradation The farther the device ground pad or plane is from the The longer that traces run parallel and the closer they ground plane in the load board, the more path inductance are together, the more crosstalk and signal degradation increases. This also could cause devices to break into can occur. This is a particularly important factor in RF oscillations. Shortening the ground path or adding extra and digital test systems. Also, the longer the contacts are paths, such as more vias, helps to lower the ground parallel and the closer they are together, the higher the risk inductance. of more crosstalk. Routing parallel traces in a differential The overall effective ground path inductance to the board configuration reduces this signal degradation by canceling ground plane can be further reduced by including extra wire out the noise. bonds or ground traces in the device, adding extra contacts in • Use Vias to Improve Crosstalk Between Signals the test contactor, adding extra vias from load board ground Periodically tying the top ground plane to the internal pad to ground plane, or using a thinner substrate material.

As traces move from the edge of high-performance load board on the About the Author the board to a device, they tend to first try. Jeff Sherry is a senior RF/high- get closer together, reducing their To optimize performance, modeling speed digital R&D engineer at John- impedance. One effective method for matching networks generally is used stech International. He has 25 years maintaining impedance of the traces to improve the test results, especially of semiconductor industry experience is to narrow traces slightly as they get if only one frequency is of interest or in designing and modeling microwave closer to a contactor and the DUT. a narrow bandwidth of frequencies is circuits up to 100 GHz. A licensed In summary, to minimize cross- important. If the frequency is changed professional engineer, Mr. Sherry talk: or contactor performance changes, received a B.S.E.E. and an M.S.E.E. • Isolate high-frequency traces using the match will not work as well after from the University of Minnesota ground lines. the change and often can degrade the and an advanced technology degree • Isolate high-frequency traces using performance. Obviously, it is impor- through Honeywell. Johnstech, 1210 via fences. tant that all the components of the New Brighton Blvd., Minneapolis, • Move clock traces away from other system have the required bandwidth MN 55413, 612-378-2020, e-mail: signal lines. needed to test the DUT. Matching to [email protected] • Route sensitive lines first: high fre- optimize performance usually is suc- quency, clock lines. cessful at one or a limited number of • Reduce parallel trace runs. The lon- frequencies.