LOAD BOARD DESIGN Designing the Optimal Board for IC Testing by Jeff Sherry, P.E., Johnstech International Designing a load board or circuit board for IC be measured across a wide bandwidth, consistent testing sounds like a routine task that involves a performance across a broad frequency range is few basic requirements and some common-sense crucial for accurate signal reproduction. approaches. But it’s not always that simple. With Be sure to consider the proper substrate thick- new technologies and increasingly complex de- ness. This is important in determining the geometry Dsign requirements, there now are more issues than of the rest of the load board because the distances ever to consider in optimizing a load board. from the ground plane or planes will affect the im- Some factors, like substrate material selec- pedance of the signal line. Standard high-frequency tion, are fundamental. Others differ with spe- materials are only stocked in 5-, 8-, 10-, 15-, 20-, cific designs, including board layout; component 32-, and 64-mil thicknesses. Usually, 4 mils is the placement; the number, placement, and size of thinnest available substrate material. vias; load board grounding; and pad sizes. These Figure 1 shows the E-fields of a Johnstech 0.5-mm pitch Pad ROL™ 200 Contactor with the load board laid out to accommodate both the ROL 200 technology and soldering of the device to the board. As shown in the figure, the E-fields are very large on the load board trace beyond the contact/load board interface point, and the edges of the contact also have fairly high E-field radiation. Sharp corners on the trace stub have higher E- field concentrations so it is best to radius edges and reduce the stub lengths. The E-fields on the left side of the model are reduced in magnitude primarily due to a cutout in the housing above the traces. The top right side of the model (the green box) is the DUT. Many load boards are designed to test parts on Figure 1. High-Frequency Structure Simulator 3-D E-Field Model of a Contactor/Load Board Interface the production floor in a removable contactor. Often, the load board/contactor system is com- factors all help minimize crosstalk. Many times, pared with the process of directly soldering parts modeling ties all of these components together to boards to calibrate out extra losses. to determine if the electrical performance will be Whenever a test contactor is used, it will met before the board is fabricated. increase the amount of ground inductance be- cause the device will come to rest some distance Substrate Material Selection above the load board. For that reason, it is vital Choosing the correct substrate material is to design the load board with lower ground in- critical for good load board design. The most ductance than is needed to make sure you still important individual electrical parameters are a can test parts to specifications in production low dielectric constant and a low dissipation fac- and that extra parameters or losses due to the tor or loss tangent. Also, if the system is going to contactor don’t affect yields. LOAD BOARD DESIGN In cases where the system is repeat- ponent placement. Using a universal its performance, especially at elevated able, these extra losses can be cali- arrangement allows a specific contac- frequencies or at gains above 30 dB. brated out. If the gain of an amplifier tor to accommodate several different Figure 2 shows a typical board lay- is measured, the amount of lost gain types of packaged devices. out with via structures. Placing ground is affected by how low the ground The placement of tuning elements traces that are periodically attached to inductance is in the test contactor. closely follows the criteria outlined a load board ground plane is the best for the placement of decoupling com- way to isolate two signal traces and Board Layout ponents. Elements comprising phase- improve board isolation or crosstalk. Typically, when laying out a load locked loops (PLLs) are particularly This model shows a GSSG configura- board, it is better not to introduce any sensitive to noise. tion, which usually is best for routing stubs that will act as antennas and A common practice with high- high-frequency signals. degrade the performance. This often speed digital devices is to embed There are two basic types of vias: occurs when the board is laid out for all the elements of the clock recov- standard and micro. The design choice two different technologies or when ery PLL internal to the chip itself. depends on factors such as frequency devices are soldered to the board in However, the capacitors that set the of operation, trace density, parasitics, addition to testing with a contactor. corner of the low-pass filter of the and economics and includes a basic Solder mask should be removed loop are external to the device. They trade-off between density and cost. from the area under the contactor to are placed on the load board. If a via is used for mounting a com- make sure it sits flat and the devices For optimum performance, these ponent, then it must be large enough are presented in a coplanar fashion. capacitors must be located directly to accommodate the lead of the com- This provides the added benefit adjacent to the terminals to which they ponent with adequate allowance for of increased contact and contactor belong. Since they are susceptible to plating buildup and solder. Small via life. If it is necessary to run parallel noise pickup, they must be shielded holes require small drill bits, and laser traces, it’s best to route signals in using a guard-ring trace around these systems are used for vias that are less differential format ground-signal- capacitors on the PCB or load board. than 4 mils in diameter. signal-ground (GSSG) to reduce the The drill bits used for these small susceptibility to noise. Vias holes are more prone to breaking than Using screw-on connectors for high- The number, placement, and size of big drill bits, adding to the fabrication frequency RF signals also can improve vias are important considerations in a costs of the load board. Also, small bits performance. The best performance successful load board design because wander off center, a characteristic that comes when the connectors are in vias route signals between layers and increases production costs since boards line rather than vertical through the act as vertical shields between traces. A must be drilled in small batches. board. Any posts on the connectors, via hole is a location in a PCB used for Microvias, which are made by pho- both grounds and signals, should be either mounting a through-hole com- toimaging, laser ablation, or plasma flush to prevent any unwanted stubs ponent or routing traces between lay- etching, generally are used in very high and degraded performance. ers. Since vias typically carry electrical trace density designs. Microvias can signals or currents, they are plated for be 2 mils or smaller. Accordingly, the Component Placement continuity. Vias can serve as a path to density of pads can increase fourfold. Ideally, decoupling components ground from traces on one layer of a Microvias also can be placed directly are located right behind the contactor PCB to the ground plane. in pads, creating even more space contacts they are meant to decouple. savings over standard vias. This is particularly important at high Via hole diameter depends on the frequencies. If this is not done, the thickness of the PCB or load board. decoupling can actually exacerbate the Standards have been established and situation because the length of circuit documented for this purpose includ- trace or wire between the target contact ing MIL-STD-275E, which lists the and its decoupler acts as an antenna. acceptable hole diameter for a stand- This allows noise to enter or exit the ard via as T/4 where T is the board circuit. This same length of circuit Figure 2. Typical Board Layout and Via Structure thickness. trace or wire can form a resonant cir- In most instances, vias are the most The more vias between the top layer cuit with the decoupling components direct path to ground. In high-speed ground traces and the ground plane, and cause sporadic oscillations. digital and RF designs, ground paths the lower the effective ground induc- Since it is desirable to have the must be short and direct to avoid in- tance and the better performance. decoupling components located right troducing extraneous noise into the Typically, the lower the loss tangent, behind the contact they are to decouple, circuitry. In many cases, boards have the less loss occurs in the substrate. the frame of the contactor may need to an insufficient number of vias to ad- A low dielectric constant and a hard be modified for the decoupling com- equately test a part without impacting substrate are important for high-fre- LOAD BOARD DESIGN 0 Layout A 1.50 -5 0.75 -10 0.35 -15 NOMINAL POINT OF CONTACT -20 Layout B 2.30 -25 1.15 -30 0.35 Return Loss (dB) Loss Return -35 NOMINAL POINT OF CONTACT -40 0.5-mm Pitch ROL200 Contact With Layout A - Modeled GSG Data Layout C 0.5-mm Pitch ROL200 Contact With Layout B - Modeled GSG Data 0.500 -45 0.20 0.5-mm Pitch ROL200 Contact With Layout C - Modeled GSG Data FULL R -50 0.35 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Frequency (GHz) NOMINAL POINT OF CONTACT Figure 3.