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Adaptation of an ARM Compatible System on Chip As an IP-Module in a FPGA

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IT 14 008 Examensarbete 30 hp Januari 2014 Adaptation of an ARM compatible System on chip as an IP-module in a FPGA Emanuel Wahlqvist Institutionen för informationsteknologi Department of Information Technology Abstract Adaptation of an ARM compatible System on chip as an IP-module in a FPGA Emanuel Wahlqvist Teknisk- naturvetenskaplig fakultet UTH-enheten In the world of today a fast prototyping and low time to market are very important factors when developing products. Any effort to minimize these parameters as well as Besöksadress: making systems easier to maintain is effort well placed. Syntronic is a consultant Ångströmlaboratoriet Lägerhyddsvägen 1 company dealing in electronic and software development, testing and maintenance. Hus 4, Plan 0 They see the soft core processor, implemented in a Field Programmable Gate Array, as a step towards more versatile platforms. As a first effort this thesis presents the Postadress: specification, implementation and testing of a System on Chip based on a open source Box 536 751 21 Uppsala ARMv2a compatible processor designed in Verilog. The system aims at applications where performance is not the highest priority but rather small FPGA area and Telefon: possibility to connect many different sensor types. The final result is a system that is 018 – 471 30 03 able to execute both assembler and C code in simulations. There was no hardware Telefax: available for testing but the synthesis procedure shows promising results. The final 018 – 471 30 00 system include interfaces for UART, SPI and I2C along with support for up to 32 General Purpose Input Output pins. All steps required for modifying and customizing Hemsida: the system is also presented along with the tools used. http://www.teknat.uu.se/student Handledare: Stig Silver Ämnesgranskare: Leif Gustafsson Examinator: Philipp Rümmer IT 14 008 Tryckt av: Reprocentralen ITC Acknowledgements I would like to thank: • Stig Silver at Syntronic for trusting in me to solve this problem. • Lars Johansson, my supervisor at Syntronic, for guidance, knowledge and help along the way. • Robert Adenmark who, despite being on parental leave, showed me in the right direction on more FPGA detailed issues. • Leif Gustafsson, my supervisor at Uppsala University, for reading, correcting and giving knowledgeable input to this report and for directing my attention to related studies in this subject. And all others at Syntronic who in some way aided me in this work. Emanuel Wahlqvist Contents 1. Introduction 1 1.1. FPGAfundamentals .............................. 2 1.1.1. CLB . 2 1.1.2. RAM blocks . 3 1.1.3. Routing net . 3 1.2. FPGAs and processors . 3 1.3. WhyARM ................................... 4 1.4. HDL design with Verilog . 4 1.4.1. Example design . 5 2. Related work 7 2.1. Optimizations.................................. 7 3. Specification 8 3.1. Core alternatives . 9 3.1.1. Considerations . 9 4. HDL Design 11 4.1. Target . 12 4.2. Amberproject ................................. 12 4.3. Clock and reset manager . 12 4.4. The Amber core . 13 4.4.1. ARMv2a Instruction Set Architecture . 14 4.4.2. Pipeline . 16 4.4.3. Pipeline hazards . 17 4.5. Wishbonebus.................................. 20 4.5.1. Wishbone signals . 20 4.5.2. Protocol . 21 4.5.3. De-multiplexer(Demux). 23 4.6. Memory . 25 4.6.1. Cache . 26 4.6.2. Boot memory . 27 4.6.3. Main . 27 4.6.4. Flash memory . 28 4.7. I2C........................................ 29 4.7.1. I2Cprotocol............................... 29 4.7.2. I2Ccontroller.............................. 30 4.8. SPI........................................ 31 4.8.1. SPI protocol . 31 4.8.2. SPI controller . 32 4.9. UART . 33 4.9.1. UART protocol . 33 4.9.2. UART controller . 34 4.10.EthernetMAC ................................. 38 4.11. GPIO . 38 4.11.1. GPIO controller . 38 4.12.Timers...................................... 39 4.12.1. Registers . 39 4.12.2. Setting up a timer . 41 4.13. Interrupt controller . 41 4.13.1. Registers . 42 4.14.Testmodule................................... 45 4.15. Verilog test bench . 47 4.15.1. UART . 48 4.15.2. SPI . 48 4.15.3. I2C.................................... 48 4.15.4. GPIO . 49 5. Configuration 50 5.1. Parameters . 50 5.2. Adding or removing a peripheral . 51 6. Tools 53 6.1. Xilinx ISE 14.5 . 53 6.1.1. Synthesis . 53 6.1.2. Simulation . 56 6.1.3. Bulk simulation . 58 6.1.4. Debug switches . 59 6.2. Sourcery CodeBench for ARM processors . 59 6.3. Amber specific tools . 59 6.3.1. amber-elfsplitter . 60 6.3.2. amber-elfsplitter-memcontents . 60 6.3.3. check mem size............................. 60 6.4. Installation . 61 7. Testing 62 7.1. Assemblertests................................. 62 7.1.1. SPItest(spi.S)............................. 62 7.1.2. I2Ctest(i2c.S) ............................. 63 7.1.3. UART test (uart tx.S)......................... 66 7.1.4. GPIO (gpio.S) . 67 7.2. Ctests...................................... 68 7.2.1. Libraries . 68 7.2.2. boot-loader-serial . 69 7.2.3. dhry . 69 7.2.4. hello-world . 69 7.2.5. spi-timer . 69 7.3. Linuxtest.................................... 69 8. Result 70 9. Conclusion 71 9.1. Specification . 71 9.2. Implementation . 71 9.2.1. Target independence . 71 9.2.2. Peripheral integration . 71 9.3. Documentation . 72 9.3.1. Peripheral controllers . 72 9.4. Testing ..................................... 72 9.5. Compiler optimization issue . 73 10.Discussion 74 10.1. Pros and cons with the Amber SoC . 74 10.2. Peripherals . 75 11.Future work 76 12.Bibliography 78 A. I2C test output I B. Linux test output V List of Figures 1.1. SimplesketchofFPGAlayout ........................ 2 4.1. Diagram showing the complete system design . 11 4.2. Overview of the a23 verilog structure. 13 4.3. Example of pipelined execution. 16 4.4. Example of control hazard handling. 18 4.5. Wishbone handshake . 21 4.6. Wishbone single read cycle . 22 4.7. Wishbone single write cycle . 22 4.8. Wishbone synchronous burst cycle . 23 4.9. Schematic of the wishbone demultiplexer . 24 4.10. Tri-state buffers on SDA and SCL. 29 4.11. I2Ctransfer.................................... 29 4.12. SPI transfer timing diagram. 32 4.13. UART in half duplex mode. 33 4.14. UART in full duplex mode with RTS and CTS. 34 4.15. A UART transfer. 34 4.16. Structural schematic of the UART controller. 35 4.17. GPIO pin tri-state buffer connection. 38 4.18. Interrupt vectors and masks. 42 4.19. Fast interrupt vectors and masks. 42 6.1. Xilinx ISE design flow. 54 6.2. Simulation script organization . 57 7.1. SPI transfer of first word. 63 7.2. SPI transfer of second word. 63 7.3. Start condition and sending slave address plus write bit (0x20) . 63 7.4. Sending register address 0x01 . 64 7.5. Sending data 0xa5 . 64 7.6. Sending data 0x5a and a stop condition . 64 7.7. Start condition and sending slave address plus write bit (0x20) . 64 7.8. Sending register address 0x01 . 64 7.9. Start condition and sending slave address plus read bit (0x21) . 64 7.10. Reading data 0xa5 . 65 7.11. Reading data 0x5a and stop condition . ..
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